Download Delta Tau PMAC2A User's Manual

^1 HARDWARE REFERENCE MANUAL
PMAC2A-PC/104 CPU
^3 PMAC2A-PC/104 CPU Hardware Reference
^4 4xx-603670-xAxx
^5 July 29, 2008
Single Source Machine Control
Power // Flexibility // Ease of Use
21314 Lassen Street Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 // www.deltatau.com
Copyright Information
© 2008 Delta Tau Data Systems, Inc. All rights reserved.
This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are
unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained
in this manual may be updated from time-to-time due to product improvements, etc., and may not
conform in every respect to former issues.
To report errors or inconsistencies, call or email:
Delta Tau Data Systems, Inc. Technical Support
Phone: (818) 717-5656
Fax: (818) 998-7807
Email: [email protected]
Website: http://www.deltatau.com
Operating Conditions
All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain
static sensitive components that can be damaged by incorrect handling. When installing or
handling Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials.
Only qualified personnel should be allowed to handle this equipment.
In the case of industrial applications, we expect our products to be protected from hazardous or
conductive materials and/or environments that could cause harm to the controller by damaging
components or causing electrical shorts. When our products are used in an industrial
environment, install them into an industrial electrical cabinet or industrial PC to protect them
from excessive or corrosive moisture, abnormal ambient temperatures, and conductive materials.
If Delta Tau Data Systems, Inc. products are exposed to hazardous or conductive materials and/or
environments, we cannot guarantee their operation.
REVISION HISTORY
REV.
1
DESCRIPTION
UPDATED JUMPER DESCRIPTIONS PGS. 6 & 30
DATE
CHG
APPVD
05/17/06
CP
S. MILICI
2
REVS: J4, E20-23, CONNECTOR PINOUTS,
& BOARD DIAGRAMS
10/04/06
CP
P. SHANTZ
3
CORRECTED TYPO IN I-VARIABLE SETTINGS, P. 17
01/22/08
CP
S.MILICI
4
CORRECTED USER FLAGS FOR PINS 25 & 26, P.36
07/29/08
CP
C.COKER
PMAC2A PC104 Hardware Reference Manual
Table of Contents
INTRODUCTION .......................................................................................................................................................1
Board Configuration..................................................................................................................................................1
Base Version .........................................................................................................................................................1
Board Options ...........................................................................................................................................................1
Option 2A: PC/104 Bus Stack Interface ..............................................................................................................1
Option 5xF: CPU Speed Options.........................................................................................................................1
Option 6: Extended Firmware Algorithm ............................................................................................................1
Option 6L: Multi-block Lookahead Firmware.....................................................................................................1
Option 10: Firmware Version Specification.........................................................................................................2
Option 12: Analog-to-Digital Converters.............................................................................................................2
Additional Accessories..............................................................................................................................................2
Acc-1P: Axis Expansion Piggyback Board...........................................................................................................2
Acc-2P: Communications Board .........................................................................................................................2
Acc-8TS Connections Board.................................................................................................................................3
Acc-8ES Four-Channel Dual-DAC Analog Stack Board......................................................................................3
Acc-8FS Four-Channel Direct PWM Stack Breakout Board................................................................................3
HARDWARE SETUP .................................................................................................................................................5
Clock Configuration Jumpers....................................................................................................................................5
Reset Jumpers............................................................................................................................................................5
CPU Configuration Jumpers .....................................................................................................................................6
Communication Jumpers...........................................................................................................................................6
ADC Configuration Jumpers.....................................................................................................................................6
Encoder Configuration Jumpers ................................................................................................................................6
Single-Ended Encoders.........................................................................................................................................6
Differential Encoders............................................................................................................................................6
MACHINE CONNECTIONS.....................................................................................................................................9
Mounting ...................................................................................................................................................................9
Power Supplies..........................................................................................................................................................9
Digital Power Supply............................................................................................................................................9
DAC Outputs Power Supply .................................................................................................................................9
Flags Power Supply............................................................................................................................................10
Overtravel Limits and Home Switches....................................................................................................................10
Types of Overtravel Limits..................................................................................................................................10
Home Switches....................................................................................................................................................10
Motor Signals Connections .....................................................................................................................................10
Incremental Encoder Connection .......................................................................................................................10
DAC Output Signals ...........................................................................................................................................11
Pulse and Direction (Stepper) Drivers ...............................................................................................................11
Amplifier Enable Signal (AENAx/DIRn).............................................................................................................11
Amplifier Fault Signal (FAULT-) .......................................................................................................................12
Optional Analog Inputs ...........................................................................................................................................12
Compare Equal Outputs ..........................................................................................................................................12
Serial Port (JRS232 Port) ........................................................................................................................................12
Machine Connections Example: Using Analog ±10V Amplifier ............................................................................13
Machine Connections Example: Using Pulse and Direction Drivers ......................................................................14
SOFTWARE SETUP ................................................................................................................................................15
PMAC I-Variables...................................................................................................................................................15
Communications......................................................................................................................................................15
Operational Frequency and Baud Rate Setup ....................................................................................................15
Filtered DAC Output Configuration........................................................................................................................16
Parameters to Set up Global Hardware Signals.................................................................................................17
Parameters to Set Up Per-Channel Hardware Signals ......................................................................................18
Table of Contents
i
PMAC2A PC104 Hardware Reference Manual
Effects of Changing I900 on the System .............................................................................................................18
How does changing I900 effect other settings in PMAC ....................................................................................20
Effects of Output Resolution and Servo Interrupt Frequency on Servo Gains....................................................21
Using Flag I/O as General-Purpose I/O...................................................................................................................22
Analog Inputs Setup ................................................................................................................................................22
CPU Analog Inputs.............................................................................................................................................22
HARDWARE REFERENCE SUMMARY .............................................................................................................23
Board Dimensions ...................................................................................................................................................23
From v106 to 107................................................................................................................................................23
From v107 to 108................................................................................................................................................24
From v108 to 109................................................................................................................................................25
Board Layout...........................................................................................................................................................26
Connectors and Indicators .......................................................................................................................................27
J3 - Machine Connector (JMACH1 Port)...........................................................................................................27
J4 - Machine Connector (JMACH2 Port)...........................................................................................................27
J8 - Serial Port (JRS232 Port)............................................................................................................................27
TB1 – Power Supply Terminal Block (JPWR Connector) ..................................................................................27
LED Indicators ...................................................................................................................................................27
E-POINT JUMPER DESCRIPTIONS ....................................................................................................................29
E0: Forced Reset Control .......................................................................................................................................29
E1: Servo and Phase Clock Direction Control .......................................................................................................29
E2: CPU Frequency Select .....................................................................................................................................29
E3: Normal/Re-Initializing Power-Up/Reset..........................................................................................................29
E4: CPU Frequency Select .....................................................................................................................................30
E8: Phase Clock Lines Output Enable....................................................................................................................30
E9: Servo Clock Lines Output Enable....................................................................................................................30
E10 – E12: Power-Up State Jumpers .....................................................................................................................30
E13: Power-Up/Reset Load Source........................................................................................................................31
E14: Watchdog Disable Jumper .............................................................................................................................31
E15A, B, C: Flash Memory Bank Select................................................................................................................31
E16: ADC Inputs Enable.........................................................................................................................................31
E18 – E19: PC/104 Bus Address............................................................................................................................32
E20-E23: ENCODER SINGLE ENDED/DIFFERENTIAL SELECT
(Note: v107 and above only) ..............32
CONNECTOR PINOUTS.........................................................................................................................................33
TB1 (JPWR): Power Supply ..................................................................................................................................33
J4 (JRS232) Serial Port Connector..........................................................................................................................33
J3 (JMACH1): Machine Port Connector .................................................................................................................34
J3 JMACH1 (50-Pin Header) ..................................................................................................................................35
J4 (JMACH2): Machine Port CPU Connector ........................................................................................................36
SCHEMATICS ..........................................................................................................................................................38
ii
Table of Contents
PMAC2A PC104 Hardware Reference Manual
INTRODUCTION
The PMAC2A PC/104 motion controller is a compact, cost-effective version of Delta Tau’s PMAC2
family of controllers. The PMAC2A PC/104 can be composed of three boards in a stack configuration.
The CPU provides four channels of either DAC ±10V or pulse and direction command outputs. The
optional axis expansion board provides a set of four additional servo channels and I/O ports. The optional
communications board provides extra I/O ports and either the USB or Ethernet interface for faster
communications.
Board Configuration
Base Version
The base version of the PMAC2A PC/104 ordered with no options provides a 90mm x 95mm board with:
• 40 MHz DSP563xx CPU (80 MHz 560xx equivalent)
• 128k x 24 internal zero-wait-state SRAM
• 512k x 8 flash memory for user backup and firmware
• Latest released firmware version
• RS-232 serial interface
• Four channels axis interface circuitry, each including:
•
12-bit ±10V analog output
•
Pulse-and-direction digital outputs
•
3-channel differential/single-ended encoder input
•
Four input flags, two output flags
•
Three PWM top-and-bottom pairs (unbuffered)
PMAC2A-PC/104 Base Board shown
• 50-pin IDC header for amplifier/encoder interface
• 34-pin IDC header for flag interface
• PID/notch/feed forward servo algorithms
• 1-year warranty from date of shipment
• One CD-ROM per set of one to four PMACs in shipment (Cables, mounting plates, mating
connectors not included)
Board Options
Option 2A: PC/104 Bus Stack Interface
Option 2A provides the PC/104 bus interface allowing bus communications between a PC/104 type
computer and the PMAC2A PC/104 motion controller.
Option 5xF: CPU Speed Options
•
•
Option 5CF: 80 MHz DSP563xx CPU (160 MHz 56002 equivalent)
Option 5EF: 160 MHz DSP563xx CPU (320 MHz 56002 equivalent)
Option 6: Extended Firmware Algorithm
Option 6 provides an Extended (Pole-Placement) Servo Algorithm firmware instead of the regular servo
algorithm firmware. This is required only in difficult-to-control systems (resonances, backlash, friction,
disturbances, changing dynamics).
Option 6L: Multi-block Lookahead Firmware
Option 6L provides a special lookahead firmware for sophisticated acceleration and cornering profiles
execution. With the lookahead firmware PMAC controls the speed along the path automatically (but
without changing the path) to ensure that axis limits are not violated.
Introduction
1
PMAC2A PC104 Hardware Reference Manual
Option 10: Firmware Version Specification
Normally the PMAC2A PC/104 is provided with the newest released firmware version. A label on the
memory IC shows the firmware version loaded at the factory. Option 10 provides for a user-specified
firmware version.
Option 12: Analog-to-Digital Converters
Option 12 permits the installation of two channels of on-board analog-to-digital converters with ±10V
input range and 12-bits resolution. The key component installed with this option is U20.
Additional Accessories
Acc-1P: Axis Expansion Piggyback Board
Acc-1P provides four additional channels axis interface circuitry for a total of eight servo channels, each
including:
• 12-bit ±10V analog output
• Pulse-and-direction digital outputs
• 3-channel differential/single-ended encoder input
• Four input flags, two output flags
• Three PWM top-and-bottom pairs (unbuffered)
Acc-1P Option 1: I/O Ports
Option 1 provides the following ports on the Acc-1P axes expansion board for digital I/O connections.
• Multiplexer Port: This connector provides eight input lines and eight output lines at TTL levels.
When using the PMAC Acc-34x type boards these lines allow multiplexing large numbers of
inputs and outputs on the port. Up to 32 of the multiplexed I/O boards may be daisy-chained on
the port, in any combination.
• I/O Port: This port provides eight general-purpose digital inputs and eight general-purpose digital
outputs at 5 to 24Vdc levels. This 34-pin connector was designed for easy interface to OPTO-22
or equivalent optically isolated I/O modules when different voltage levels or opto-isolation to the
PMAC2A PC/104 is necessary.
• Handwheel port: this port provides two extra channels, each jumper selectable between encoder
input or pulse output.
Acc-1P Option 2: Analog-to-Digital Converters
Option 2 permits the installation on the Acc-1P of two channels of analog-to-digital converters with ±10V
input range and 12-bits resolution. The key component installed with this option is U20.
Acc-2P: Communications Board
Without any options, the PMAC2A PC/104 communicates through the RS-232 serial interface (using the
optional Acc-3L flat cable) or PC/104 bus. This board provides added communication and I/O features.
Acc-2P Option 1A: USB Interface
Option 1A it provides a 480 Mbit/sec USB 2.0 interface.
Acc-2P Option 1B: Ethernet Interface
Option 1B provides a 100 Mbit/sec Ethernet.
Acc-2P Option 2: DPRAM Circuitry
Option 2 provides an 8K x 16 dual-ported RAM used with USB, Ethernet or PC/104 bus applications. If
using for USB or Ethernet communications, Acc-2P-Opt-1A or Acc-2P-Opt-1B must be ordered. If used
2
Introduction
PMAC2A PC104 Hardware Reference Manual
for PC/104-bus communications, PMAC2A PC/104 Option-2A must be ordered. The key component
installed with this option is U17. USB/Ethernet and PC/104 bus communications cannot be made
simultaneously it is jumper selectable.
Acc-2P Option 3: I/O Ports
Option 3 provides the following ports on the Acc-2P communications board for digital I/O connections.
• Multiplexer Port: this connector provides eight input lines and eight output lines at TTL levels.
When using the PMAC Acc-34x type boards these lines allow multiplexing large numbers of
inputs and outputs on the port. Up to 32 of the multiplexed I/O boards may be daisy-chained on
the port, in any combination.
• I/O Port: this port provides 16 general-purpose digital I/O lines at TTL levels and these can be
configured as all inputs, all outputs or eight inputs and eight outputs.
• Handwheel port: this port provides two extra channels, each jumper selectable between encoder
input or pulse output.
Acc-8TS Connections Board
Acc-8TS is a stack interface board to for the connection of either one or two Acc-28B A/D converter
boards. When a digital amplifier with current feedback is used, the analog inputs provided by the Acc28B cannot be used.
Acc-8ES Four-Channel Dual-DAC Analog Stack Board
Acc-8ES provides four channels of 18-bit dual-DAC with four DB-9 connectors. This accessory is
stacked to the PMAC2A PC/104 board and it is mostly used with amplifiers that require two ±10 V
command signals for sinusoidal commutation.
Acc-8FS Four-Channel Direct PWM Stack Breakout Board
Acc-8FS it is a 4-channel direct PWM stack breakout board for PMAC2A PC/104. This is used for
controlling digital amplifiers that require direct PWM control signals. When a digital amplifier with
current feedback is used, the analog inputs provided by the Option 12 of the PMAC2A PC/104 (the
Option 2 of the Acc-1P or the Acc-28B) could not be used.
Introduction
3
PMAC2A PC104 Hardware Reference Manual
4
Introduction
PMAC2A PC104 Hardware Reference Manual
HARDWARE SETUP
On the PMAC2 PC/104 CPU, there are a number of jumpers called E-points or W-points. That customize
the hardware features of the CPU for a given application and must be setup appropriately. The following
is an overview grouped in appropriate categories. For an itemized description of the jumper setup
configuration, refer to the E-Point Descriptions section.
Clock Configuration Jumpers
E1: Servo and Phase Clock Direction Control – Jumper E1 should be OFF if the board is to use its
own internally generated phase and servo clock signals. In this case, these signals are output on spare
pins on the J8 RS-232 serial-port connector, where they can be used by other PMAC controllers set up to
take external phase and servo clock signals.
Jumper E1 should be ON if the board is to use externally generated phase and servo clock signals brought
in on the J8 RS-232 serial port connector. In this case, typically the clock signals are generated by
another PMAC controller and output on its serial port connector.
If E1 is ON for external phase and clock signals, and these clock signals are not brought in on the serial
port connector, the watchdog timer will trip almost immediately and shut down the board.
E2 and E4: CPU Frequency Control Jumpers – When the PMAC I46 I- variable is set to zero jumpers
E2 and E4 on the base PMAC2A PC/104 board control the frequency at which the CPU will operate (or
attempt to operate). Generally, this will be the highest frequency at which the CPU is rated to operate.
Note that it is always possible to operate a CPU at a frequency lower than its maximum rating. While it
may be possible to operate an individual processor at a frequency higher than its maximum rating,
particularly at low ambient temperatures, performance cannot be guaranteed at such a setting, and this
operation is done completely at the user’s own risk.
• If jumpers E2 and E4 are both OFF, the CPU will operate at a 40 MHz frequency.
• If E2 is ON and E4 is OFF, the CPU will operate at a 60 MHz frequency.
• If E2 is OFF and E4 is ON, the CPU will operate at an 80 MHz frequency.
If I46 is set to a value greater than 0, the operational frequency is set to 10MHz * (I46 + 1), regardless of
the jumper setting. See the Software Setup section for details on this.
E8: Phase Clock Lines Output Enable – Jump pin 1 to 2 to enable the Phase clock line on the J8
connector. Remove jumper to disconnect the Phase clock line on the J8 connector.
E9: Servo Clock Lines Output Enable – Jump pin 1 to 2 to enable the Servo clock line on the J8
connector. Remove jumper to disconnect the Servo clock line on the J8 connector.
Reset Jumpers
E0: Forced Reset Control – Remove E0 for normal operation. Installing E0 forces PMAC to a reset
state, this configuration is for factory use only; the board will not operate with E0 installed.
E3: Re-Initialization on Reset Control – If E3 is OFF (default), PMAC executes a normal reset,
loading active memory from the last saved configuration in non-volatile flash memory. If E3 is ON,
PMAC re-initializes on reset, loading active memory with the factory default values.
E13: Firmware Load Jumper – If jumper E13 is ON during power-up/reset, the board comes up in
bootstrap mode which permits loading of firmware into the flash-memory IC. When the PMAC
Executive program tries to establish communications with a board in this mode, it will detect
automatically that the board is in bootstrap mode and ask what file to download as the new firmware.
Jumper E13 must be OFF during power-up/reset for the board to come up in normal operational mode.
Hardware Setup
5
PMAC2A PC104 Hardware Reference Manual
CPU Configuration Jumpers
E15A-E15C: Flash Memory Bank Select Jumpers – The flash-memory IC in location U10 on the
PMAC2A PC/104 base board has the capacity for eight separate banks of firmware, only one of which
can be used at any given time. The eight combinations of settings for jumpers E15A, E15B, and E15C
select which bank of the flash memory is used. In the factory production process, firmware is loaded only
into Bank 0, which is selected by having all of these jumpers OFF.
E10-E12: Power-Up State Jumpers – Jumper E10 must be OFF, jumper E11 must be ON, and jumper
E12 must be ON, in order for the CPU to copy the firmware from flash memory into active RAM on powerup/reset. This is necessary for normal operation of the card. (Other settings are for factory use only.)
E14: Watchdog Timer Jumper – Jumper E14 must be OFF for the watchdog timer to operate. This is a
very important safety feature, so it is vital that this jumper be OFF for normal operation. E14 should only
be put ON to debug problems with the watchdog timer circuit.
W1: Flash chip select – Jumper W1 in position 1-2 selects a 28F320J3A part for the U10 flash chip.
Jumper W1 in position 2-3 selects a 28F320J5A part for the U10 flash chip. This jumper is installed in
the factory and must not be changed from its default state.
Communication Jumpers
E18-E19: PC/104 Bus Base Address Control – Jumpers E18 and E19 on the PMAC2A PC/104 CPU
determine the base address of the card in the I/O space of the host PC. Together, they specify four
consecutive addresses on the bus where the card can be found. The jumpers form the base address in the
following fashion:
E18
E19
Address (hex)
Address (dec.)
OFF
OFF
ON
ON
OFF
ON
OFF
ON
$200
$210
$220
$230
512
528
544
560
The default base address is 528 ($210) formed with jumper E18 removed and E19 installed. This setting
is necessary when using the USB or Ethernet ports of the Acc-2P communications board.
ADC Configuration Jumpers
E16: ADC Enable Jumper – Install E16 to enable the analog-to-digital converter circuitry ordered
through Option-12. Remove this jumper to disable this option, which might be necessary to control
motor 1 through a digital amplifier with current feedback.
Encoder Configuration Jumpers
E20-E23: Encoder Single Ended/Differential Select – PMAC has differential line receivers for each
encoder channel, but can accept either single-ended (one signal line per channel) or differential (two
signal lines, main and complementary, per channel). A jumper for each encoder permits customized
configurations, as described below.
Single-Ended Encoders
With the jumper for an encoder set for single-ended, the differential input lines for that encoder are tied to
2.5V; the single signal line for each channel is then compared to this reference as it changes between 0
and 5V.
When using single-ended TTL-level digital encoders, the differential line input should be left open, not
grounded or tied high; this is required for The PMAC differential line receivers to work properly.
Differential Encoders
Differential encoder signals can enhance noise immunity by providing common-mode noise rejection.
Modern design standards virtually mandate their use for industrial systems, especially in the presence of
PWM power amplifiers, which generate a great deal of electromagnetic interference.
6
Hardware Setup
PMAC2A PC104 Hardware Reference Manual
Connect pin 1 to 2 to tie differential line to +2.5V
• Tie to +2.5V when no connection
• Tie to +2.5V for single-ended encoders
Connect pin 2 to 3 to tie differential line to +5V
• Don’t care for differential line driver encoders
• Tie to +5V for complementary open-collector encoders (obsolete)
Hardware Setup
7
PMAC2A PC104 Hardware Reference Manual
8
Hardware Setup
PMAC2A PC104 Hardware Reference Manual
MACHINE CONNECTIONS
Typically, the user connections are made to terminal blocks that attach to the JMACH connectors by a
flat cable. The following are the terminal blocks recommended for connections:
• 34-Pin IDC header to terminal block breakouts (Phoenix part number 2281063) Delta Tau
part number 100-FLKM34-000
• 50-Pin IDC header to terminal block breakouts (Phoenix part number 2281089) Delta Tau
part number 100-FLKM50-000
Mounting
The PMAC2A PC/104 is typically installed using standoffs when stacked
to a PC/104 computer or as a stand-alone controller. At each of the four
corners of the PMAC2A PC/104 board, there are mounting holes that can
be used for this.
The PMAC2A PC/104 CPU is placed always at the bottom of the stack.
The order of the Acc-1P or Acc-2P with respect to the CPU does not
matter.
Power Supplies
Baseboard mounted at
the bottom of the stack
Digital Power Supply
3A @ +5V (±5%) (15 W) with a minimum 5 msec rise time
(Eight-channel configuration, with a typical load of encoders)
The PMAC2A PC/104, the Acc-1P and the Acc-2P each require a 1A @ 5VDC power supply for
operation. Therefore, a 3A @ 5VDC power supply is recommended for a PMAC2A PC/104 board
stack with Acc-1P and Acc-2P boards.
• The host computer provides the 5 Volts power when installed in the PC/104 bus and cannot
be disconnected. In this case, there must be no external +5V supply, or the two supplies will
"fight" each other, possibly causing damage. This voltage could be measured on the TB1
terminal block or the JMACH1 connector.
• In a stand-alone configuration, when PMAC is not plugged in a computer bus, it will need an
external 5V supply to power its digital circuits. The 5V power supply can be brought in
either from the TB1 terminal block or from the JMACH1 connector.
• When an ACC-2P is used, a minimum rise time of 5 msec is a requirement of the power
supply. In addition, the power supply ramp-down time should not exceed 20 msec. While
solutions to this issue can involve complex circuitry that minimizes power loss during normal
operation, the simplest method of quickly bringing down the power rail is to add a bleeddown resistor between VCC and GND. The resistor should be large enough that it does not
cause unnecessary power consumption, while still discharging the bulk capacitance as
quickly as possible. Specific resistor values will depend on the overall design of the system,
but in general the voltage drop-off time should not exceed 20 msec. A value that has been
found to work for some systems is 18k.
DAC Outputs Power Supply
0.3A @ +12 to +15V (4.5W)
0.25A @ -12 to -15V (3.8W)
(Eight-channel configuration)
• The host computer provides the ±12 Volts power supply in the case PMAC is installed in the
PC/104 bus. With the board stack into the bus, it will pull ±12V power from the bus
automatically and it cannot be disconnected. In this case, there must be no external ±12V
Machine Connections
9
PMAC2A PC104 Hardware Reference Manual
•
supply, or the two supplies will fight each other, possibly causing damage. This voltage
could be measured on the TB1 terminal block.
In a stand-alone configuration, when PMAC is not plugged in a computer bus, it will need an
external ±12V supply only when the digital-to-analog converter (DAC) outputs are used. The
±12V lines from the supply, including the ground reference, can be brought in either from the
TB1 terminal block or from the JMACH1 connector.
Flags Power Supply
Each channel of PMAC has five dedicated digital inputs on the machine connector: PLIMn, MLIMn
(overtravel limits), HOMEn (home flag), FAULTn (amplifier fault), and USERn. A power supply
from 5 to 24V must be used to power the circuits related to these inputs. This power supply can be
the same used to power PMAC and can be connected from the TB1 terminal block or the JMACH1
connector.
Overtravel Limits and Home Switches
When assigned for the dedicated uses, these signals provide important safety and accuracy functions.
PLIMn and MLIMn are direction-sensitive over-travel limits that must conduct current to permit
motion in that direction. If no over-travel switches will be connected to a particular motor, this
feature must be disabled in the software setup through the PMAC Ix25 variable.
Types of Overtravel Limits
PMAC expects a closed-to-ground connection for the limits to not be considered on fault. This
arrangement provides a failsafe condition. Usually, a passive normally close switch is used. If a
proximity switch is needed instead, use a 5 to 24V normally closed to ground NPN sinking type
sensor.
Home Switches
While normally closed-to-ground switches are required for the overtravel limits inputs, the home
switches could be either normally close or normally open types. The polarity is determined by
the home sequence setup, through the I-variables I9n2.
Motor Signals Connections
Incremental Encoder Connection
Each JMACH1 connector provides two +5V outputs and two logic grounds for powering encoders
and other devices. The +5V outputs are on pins 1 and 2; the grounds are on pins 3 and 4. The
encoder signal pins are grouped by number: all those numbered 1 (CHA1+, CHA1-, CHB1+, CHC1+,
etc.) belong to encoder #1. The encoder number does not have to match the motor number, but
usually does. Connect the A and B (quadrature) encoder channels to the appropriate terminal block
pins. For encoder 1, the CHA1+ is pin 5 and CHB1+ is pin 9. If there is a single-ended signal, leave
the complementary signal pins floating – do not ground them. However, if single-ended encoders are
used, check the setting of the resistor packs (see the Hardware Setup section for details). For a
differential encoder, connect the complementary signal lines – CHA1- is pin 7, and CHB1- is pin 11.
The third channel (index pulse) is optional; for encoder 1, CHC1+ is pin 13, and CHC1- is pin 15.
10
Machine Connections
PMAC2A PC104 Hardware Reference Manual
Example: differential quadrature encoder connected to channel #1:
DAC Output Signals
If PMAC is not performing the commutation for the motor, only one analog output channel is
required to command the motor. This output channel can be either single-ended or differential,
depending on what the amplifier is expecting. For a single-ended command using PMAC channel 1,
connect DAC1+ (pin 29) to the command input on the amplifier. Connect the amplifier’s command
signal return line to PMAC’s GND line (pin 48). In this setup, leave the DAC1- pin floating; do not
ground it.
For a differential command using PMAC channel 1, connect DAC1 (pin 29) to the plus-command
input on the amplifier. Connect DAC1- (pin 31) to the minus-command input on the amplifier.
PMAC’s GND should still be connected to the amplifier common.
Any analog output not used for dedicated servo purposes may be utilized as a general-purpose analog
output by defining an M-variable to the command register, then writing values to the M-variable. The
analog outputs are intended to drive high-impedance inputs with no significant current draw. The
220Ω output resistors will keep the current draw lower than 50 mA in all cases and prevent damage to
the output circuitry, but any current draw above 10 mA can result in noticeable signal distortion.
Example:
Pulse and Direction (Stepper) Drivers
The channels provided by the PMAC2A PC/104 board or the Acc-1P board can output pulse and
direction signals for controlling stepper drivers or hybrid amplifiers. These signals are at TTL levels.
Amplifier Enable Signal (AENAx/DIRn)
Most amplifiers have an enable/disable input that permits complete shutdown of the amplifier
regardless of the voltage of the command signal. PMAC’s AENA line is meant for this purpose.
AENA1- is pin 33. This signal is an open-collector output and an external 3.3 kΩ pull-up resistor can
be used if necessary.
Machine Connections
11
PMAC2A PC104 Hardware Reference Manual
Amplifier Fault Signal (FAULT-)
This input can take a signal from the amplifier so PMAC knows when the amplifier is having
problems, and can shut down action. The polarity is programmable with I-variable Ix25 (I125 for
motor 1) and the return signal is ground (GND). FAULT1- is pin 35. With the default setup, this
signal must actively be pulled low for a fault condition. In this setup, if nothing is wired into this
input, PMAC will consider the motor not to be in a fault condition.
Optional Analog Inputs
The optional analog-to-digital converter inputs are ordered either through Option-12 on the CPU or
Option-2 on the axes expansion board. Each option provides two 12-bit analog inputs analog inputs
with a ±10Vdc range.
Compare Equal Outputs
The compare-equals (EQU) outputs have a dedicated use of providing a signal edge when an encoder
position reaches a pre-loaded value. This is very useful for scanning and measurement applications.
Instructions for use of these outputs are covered in detail in the PMAC2 User Manual.
Serial Port (JRS232 Port)
For serial communications, use a serial cable to connect your PC's COM port to the J8 serial port
connector present on the PMAC2A PC/104 CPU. Delta Tau provides the Acc-3L cable for this
purpose that connects the PMAC to a DB-9 connector. Standard DB-9-to-DB-25 or DB-25-to-DB-9
adapters may be needed for your particular setup.
12
Machine Connections
PMAC2A PC104 Hardware Reference Manual
If a cable needs to be made, the easiest approach is to use a flat cable prepared with flat-cable type
connectors as indicated in the following diagram:
DB-9 Female
1
DB-9 Male
1
PMAC (DB-9S)
PC (DB-9)
1 (No connect)
2 (TXD/)
3 (RXD/)
4 (DSR)
5 (Gnd)
6 (DTR)
7 (CTS)
8 (RTS)
9 (No connect)
1 (No connect)
2 (RXD)
3 (TXD)
4 (DTR)
5 (Gnd)
6 (DSR)
7 (RTS)
8 (CTS)
9 (No connect)
Machine Connections Example: Using Analog ±10V Amplifier
Machine Connections
13
PMAC2A PC104 Hardware Reference Manual
Machine Connections Example: Using Pulse and Direction Drivers
14
Machine Connections
PMAC2A PC104 Hardware Reference Manual
SOFTWARE SETUP
Note:
The PMAC2A PC/104 requires the use of V1.17 or newer firmware. There are
few differences between the previous V1.16H firmware and the V1.17 firmware
other than the addition of internal support for the Flex CPU design.
PMAC I-Variables
PMAC has a large set of Initialization parameters (I-variables) that determine the "personality" of the card
for a specific application. Many of these are used to configure a motor properly. Once set up, these
variables may be stored in non-volatile EAROM memory (using the SAVE command) so the card is
always configured properly (PMAC loads the EAROM I-variable values into RAM on power-up).
The programming features and configuration variables for the PMAC2A PC/104 are described fully in the
PMAC2 User and Software manuals.
Communications
Delta Tau provides software tools that allow communicating with of the PMAC2A PC/104 board by
either its standard RS-232 port or the optional USB or Ethernet ports. PEWIN is the most important in
the series of software accessories, and it allows configuring and programming the PMAC for any
particular application.
Operational Frequency and Baud Rate Setup
Note:
Older PMAC boards required a start-up PLC for setting the operational frequency
at 80 MHz. That method is not compatible with the PMAC2A PC/104 board and
will shutdown the board when used.
The operational frequency of the CPU can be set in software by the variable I46. If this variable is set to
0, PMAC firmware looks at the jumpers E2 and E4 to set the operational frequency for 40, 60, and 80
MHz operation. If I46 is set to a value greater than 0, the operational frequency is set to 10MHz * (I46 +
1), regardless of the jumper setting. If the desired operational frequency is higher than the maximum
rated frequency for that CPU, the operational frequency will be reduced to the rated maximum. It is
always possible to operate the Flex CPU board at a frequency below its rated maximum. I46 is used only
at power-up/reset, so to change the operational frequency, set a new value of I46, issue a SAVE command
to store this value in non-volatile flash memory, then issue a $$$ command to reset the controller.
To determine the frequency at which the CPU is actually operating, issue the TYPE command to the
PMAC. The PMAC will respond with five data items, the last of which is CLK Xn, where n is the
multiplication factor from the 20 MHz crystal frequency (not 10 MHz). n should be equivalent to
(I46+1)/2 if I46 is not requesting a frequency greater than the maximum rated for that CPU board. n will
be 2 for 40 MHz operation, 4 for 80 MHz operation, and 8 for 160 MHz operation.
Software Setup
15
PMAC2A PC104 Hardware Reference Manual
If the CPU’s operational frequency has been determined by (a non-zero setting of) I46, the serial
communications baud rate is determined at power-up/reset by variable I54 alone according to the
following table:
I54
Baud Rate
I54
Baud Rate
0
1
2
3
4
5
6
7
600
900
1200
1800
2400
3600
4800
7200
8
9
10
11
12
13
14
15
9600
14,400
19,200
28,800
38,400
57,600
76,800
115,200
For a saved value of 0 for I46, the serial baud rate is determined by the combination of I54 and the CPU
frequency as shown in the following table.
I54
Baud Rate for
40 MHz CPU
Baud Rate for
60 MHz CPU
Baud Rate for
80 MHz CPU
Disabled
900
1200
1800
2400
3600
4800
7200
9600
14,400
19,200
28,800
38,400
57,600
76,800
115,200
1200
1800* (-0.1%)
2400
3600* (-0.19%)
4800
7200* (-0.38%)
9600
14,400*(-0.75%)
19,200
28,800*(-1.5%)
38,400
57,600*(-3.0%)
76,800
115,200*(-6.0%)
153,600
Disabled
0
600
1
900* (-0.05%)
2
1200
3
1800* (-0.1%)
4
2400
5
3600* (-0.19%)
6
4800
7
7200* (-0.38%)
8
9600
9
14,400*(-0.75%)
10
19,200
11
28,800*(-1.5%)
12
38,400
13
57,600*(-3.0%)
14
76,800
15
Disabled
* Not an exact baud rate
Filtered DAC Output Configuration
The PMAC2 PC104 is a PMAC2 style board with default +/-10V outputs produced by filtering a PWM
signal. This technique has been used been for some time now by many of our competitors. Although this
technique does not contain the same levels of performance as a true Digital to Analog converter, for most
servo applications it is more than adequate. Many of our customers using this product have migrated over
from the PMAC1 style board with a true 16-bit DAC. This document is meant for explaining the
tradeoffs of PWM frequency vs. resolution in the PMAC2PC104 base configuration as well as a
comparison to the PMAC1 style 16 bit DACs.
Both the resolution and the frequency of the Filtered PWM outputs are configured in software on the
PMAC2PC104 through the variable I900. This I900 variable also effects the phase and servo interrupts.
Therefore as we change I900 we will also have to change I901 (phase clock divider), I902 (servo clock
divider), and I10 (servo interrupt time). These four variables are all related and must be understood
before adjusting parameters.
16
Software Setup
PMAC2A PC104 Hardware Reference Manual
Since the PMAC2PC104 uses standard PMAC2 firmware the following I-variables must be set properly
to use the digital-to-analog (filtered DAC) outputs:
I900
I901
I902
I903
I906
I907
I9n6
Ix69
I10
=
=
=
=
=
=
=
=
=
1001
5
3
1746
1001
1746
0
1001
3421867
;
;
;
;
;
;
;
;
;
PWM frequency 29.4kHz, PWM 1-4
Phase Clock 9.8059kHz
Servo frequency 2.451kHz
ADC frequency
PWM frequency 29.4kHz, PWM 5-8
ADC frequency
Output mode: PWM
DAC limit 10Vdc
Servo interrupt time
n = channel number from 1 to 8
x = motor number from 1 to 8
Parameters to Set up Global Hardware Signals
I900
I900 determines the frequency of the MaxPhase clock signal from which the actual phase clock
signal is derived. It also determines the PWM cycle frequency for Channels 1 to 4. This variable
is set according to the equation:
I900 = INT[117,964.8/(4*PWMFreq(KHz)) - 1]
The PMAC2 PC/104 filtered PWM circuits were optimized for 30KHz. I900 should be set to
1088 (calculated as 27.06856KHz)
I901
I901 determines how the actual phase clock is generated from the MaxPhase clock, using the
equation:
PhaseFreq(kHz) = MaxPhaseFreq(kHz)/(I901+1)
I901 is an integer value with a range of 0 to 15, permitting a division range of 1 to 16. Typically,
the phase clock frequency is in the range of 8 kHz to 12 kHz. 9KHz is standard, set I901 = 5
(calculated as 9.02285 KHz).
I902
I902 determines how the servo clock is generated from the phase clock, using the equation:
ServoFreq(KHz) = PhaseFreq(KHz)/(I902+1)
I902 is an integer value with a range of 0 to 15, permitting a division range of 1 to 16. On the
servo update, which occurs once per servo clock cycle, PMAC2 updates commanded position
(interpolates) and closes the position/velocity servo loop for all active motors, whether or not
commutation and/or a digital current loop is closed by PMAC2. Typical servo clock frequencies
are 1 to 4 kHz. The PMAC standard is 2.26 KHz, set I902 = 3 (calculated as 2.25571 KHz).
I10 tells the PMAC2 interpolation routines how much time there is between servo clock cycles. It
must be changed any time I900, I901, or I902 is changed. I10 can be set according to the
formula:
I10 = (2*I900+3)(I901+1)(I902+1)*640/9
I10 should be set to 3718827.
Software Setup
17
PMAC2A PC104 Hardware Reference Manual
I903
I903 determines the frequency of four hardware clock signals used for machine interface channels 1-4;
This can be left at the default value (I903=*). The four hardware clock signals are SCLK (encoder sample
clock), PFM_CLK (pulse frequency modulator clock), DAC_CLK (digital-to-analog converter clock),
and ADC_CLK (analog-to-digital converter clock).
Parameters to Set Up Per-Channel Hardware Signals
I9n6
I9n6 is the output mode; “n” is the output channel number (i.e. for channel 1 the variable to set would be
i916, i926 for channel 2 etc.). On Pmac1 there is only one output and one output mode, DAC output. On
PMAC2 boards, each channel has 3 outputs, and there are 4 output modes. Since this is board was
designed to output filtered PWM signals we want to configure at least the first output as PWM. Therefore
the default value of 0 is the choice. For information on this variable consult the PMAC1/PMAC2
software reference manual.
Ix69
Ix69 is the motor output command limit. The analog outputs on PMAC1 style boards and some PMAC2
accessories are 16-bit DACs, which map a numerical range of -32,768 to +32,767 into a voltage range of 10V to +10V relative to analog ground (AGND). For our purposes of a filtered PWM output this value
still represents the maximum voltage output; however the ratio is slightly different. With a true DAC,
Ix69=32767 allows a maximum voltage of 10V output. With the filtered PWM circuit, Ix69 is a function
of I900. A 10V signal in the output register is no longer 32767 as was in PMAC1, a 10V signal is
corresponds to a value equal to I900. Anything over I900 will just rail the Dac at 10V. For Example:
Desired Maximum Output Value = 6V
Ix69=6/10 * i900
Desired Maximum Output Value = 10V
Ix69= I900 + 10 ; add a little headroom to assure a full 10V
Effects of Changing I900 on the System
It should now be understood that a full 10 volts is output when the output register is equal to i900. The
output register is suggested m-variable Mx02 (I.e. M102-> Y:$C002,8,16,S ; OUT1A command value;
DAC or PWM). With default setting of I900, 10Volts is output when m102 is equal to i900, or 1001.
Since the output register is an integer value the smallest increment of change is about 10mV (1/1001 *
10V). Some users may want to calibrate their analog output using Ix29. Ix29 is an integer similar to
Mx02 except the value is added to the output register every servo cycle to apply a digital offset to the
output register. Therefore the resolution of our output signal affects how Ix29 should be set. As
mentioned earlier, with the default parameters, 1 bit change in the output register changes the analog
output by about 10mV. Therefore if there is an analog output offset less than 5mV, Ix29 cannot decrease
your offset. By increasing I900 you increase your resolution, so if you double i900, 1 bit change in the
output register corresponds to about 5mV. So with Ix29 you can only change the offset in increments of
5mV.
You can see above that by increasing I900 you increase the resolution of our command output register.
This sounds like a good thing, right? There are tradeoffs when you change I900 between resolution and
ripple.
18
Software Setup
PMAC2A PC104 Hardware Reference Manual
By increasing I900 we are essentially decreasing our PWM Frequency. The two are related by the
following equation:
I900 = INT[117,964.8/(4*PWMFreq(KHz)) - 1]
Passing the PWM signal through a 10KHz low pass filter creates the +/-10V signal output. The duty
cycle of the PWM signal is what generates the magnitude the voltage output. The frequency of the PWM
signal determines the magnitude and frequency of ripple on that +/-10V signal. As you lower the PWM
frequency and subsequently increase your output resolution, you increase the magnitude of the ripple as
well as slow down the frequency of the ripple as well. Depending on the system, this ripple can affect
performance at different levels.
So what do we mean by ripple? Ripple is the small signal that will you will see on top of the +/-10V
signal if you put an oscilloscope on it. In other words if I command a 4V signal out of the PMAC2PC104
and scope it, I will see a small sinusoidal type wave centered on 4V. At the default PWM frequency and
output resolution this will have a magnitude of about 230mV and a frequency of about 33kHz. This is
typically faster than any of the control loops so the amplifier essentially filters it out of the system.
Say I wanted to double the resolution of my output signal, I would merely double my I900 value from
1001 to 2002. How does this affect the ripple? From a test I calculated the ripple magnitude to increase
from around 230mV to about 700mV. The frequency of the ripple decreased from about @30kHz to
@15kHz. Here are some measurements taken with a PMAC2PC104:
I900 Value
Output
Voltage
PWM
Approximate
Approximate
Resolution
Output Change
Frequency
Ripple
Ripple
Signed
Per 1bit increment
Magnitude
Frequency
In output register
1001
@11 bit
9.9mV
29.4177 KHz
230mV
30KHz
2002
@12 bit
4.99mV
14.72 Khz
700mV
15KHz
4004
@13bit
2.49mV
7.36 Khz
2V
7Khz
How does the ripple affect servo performance? It really depends on the system. For most servo systems
the mechanics can’t respond anywhere near these frequencies. Some systems with linear amplifiers it will
effect the performance especially as you lower the PWM frequency and effectively the ripple frequency,
i.e. galvanometers, etc. In the overall majority of the servo world, these ripple frequencies will not show
in the system due to mechanical and electrical time constants of most systems. This will happen
regardless of the amplifier used.
So why is the recommended setup for 30KHz? A few reasons, the first is aesthetics. Nobody wants to
put a scope on an output signal and see 1 or 2V of hash. If you increase that frequency the hash is
minimized. The second reason is response of the output with respect to the servo filter. If you increase
the output resolution and thus lower the PWM frequency far enough you will notice some lag in the
system from the delays between the output register value actually being picked up by the slower PWM
frequency.
For high response systems we suggest using Acc8es and a true 18bit DAC. However the filtered PWM
technique will be more than adequate for most applications.
Software Setup
19
PMAC2A PC104 Hardware Reference Manual
How does changing I900 effect other settings in PMAC
I900 is does not only set the PWM frequency for the PWM outputs but it also sets the Max Phase
Frequency.
MaxPhase Frequency = 117,964.8 kHz / [2*I900+3]
PWM Frequency = 117,964.8 kHz / [4*I900+6]
The Max Phase Frequency is then divided by I901 to generate the frequency for the phase interrupt and its
routines. If you change I900 you have to change I901 to keep the same phase interrupt.
PHASE Clock Frequency = MaxPhase Frequency / (I901+1)
The Phase Clock Frequency setting also effects the servo interrupt frequency. If you change the phase
interrupt frequency then you must change I902 to keep the same servo interrupt.
Servo Clock Frequency = PHASE Clock Frequency / (I902+1)
When you change the servo interrupt you must always change the servo interrupt time, i10, to match or all
of your timing will be off in PMAC.
I10=8388608/(Servo Frequency (KHz)) = 8388608 * ServoTime(msec)
If you decide to change I900 be sure to reset Ix69 to the proper safety setting per the following formula:
Ix69=MaxVolts/10 * I900
Examples:
Default Example:
I900=1001
I901=2
I902=3
Ix69=1024
I10=1710933
MaxPhase Frequency = 117,964.8 kHz / [2*1001+3] = 58.835KHz
PWM Frequency = 117,964.8 kHz / [4*1001+6] = 29.418KHz
PHASE Clock Frequency = MaxPhase Frequency / (2+1) = 19.61KHz
Servo Clock Frequency = PHASE Clock Frequency / (3+1) = 4.90KHz
I10=8388608/(4.902943) = 1710933
Ix69=10V/10 * I900 = 1001 add headroom to 1024
Now lets say I wanted to double my resolution:
I900=2002
MaxPhase Frequency = 117,964.8 kHz / [2*2002+3] = 29.44KHz
PWM Frequency = 117,964.8 kHz / [4*2002+6] = 14.72KHz
In order to save headroom on firmware routines that trigger off the phase and servo interrupts it is best to
keep those frequencies about the same as above. Some systems may want higher phase and servo
20
Software Setup
PMAC2A PC104 Hardware Reference Manual
interrupt frequencies for better servo performance, but our default frequencies are typically more than fast
enough for many applications. We will discuss tuning parameter a bit later in this document.
I901= 29.44KHz/19.61KHz -1 = @0.5 set it at 1 or 14.72KHz
This is not exactly the same since I901 is an integer value but pretty close. Since we are doing any
commutation with a +/-10V signal it doesn’t make that much of a difference. The Servo Frequency we
will be able to get close though:
I902=14.72KHz/4.9 – 1 = 2.004 or 2 which is @4.9KHz
For a 10V max signal output:
Ix69=i900 + headroom = 2024
We must set I10 whenever we change the servo clock but since we kept it basically the same, I19 stays
pretty much the same. Without rounding it works out to the following:
I10 = 8388608/4.906613 = 1709653
For precise timing within your motion application it is important not to round off when calculating I10.
Effects of Output Resolution and Servo Interrupt Frequency on Servo
Gains
When you change your output resolution and/or servo interrupt timing your tuning parameters will no
longer respond the same. The system will have to be tuned again in order to achieve the desired
performance. There is an approximate relation of output resolution to servo loop gains . If you were
switching an application from a PMAC style 16bit Dac to a PMAC2Pc104 with default resolution of
about 11bits you can expect a change of your gains in order to get similar response.
The max output value of the output command with a 16bit Dac is 32767. With the PMAC2Pc104 at its
default parameters the max output value is 1001. If you had equal servo interrupt frequencies the
proportional gain on the PC104 system would have a proportional gain 1001/32767 or about 1/32 smaller.
This is more a rule of thumb than an exact formula. It is always recommended to go through a full tuning
procedure when changing output resolution.
If you decide to change the Servo Interrupt Frequency, then you are also changing the dynamics of the
servo filter and thus the system. You will need to retune the system in order to get the desired
performance. If you increase the servo frequency you will need to lower the proportional gain in order to
achieve similar performance. The reason you increased the frequency in the first place was more likely to
achieve a higher performance so relations here are not very helpful.
If you desire to change servo interrupt frequency in order to have your foreground PLCs execute more
often you can also adjust Ix60 to keep your gains the same, see the Pmac1/2 Software Reference Manual
for a further description of this parameter.
Software Setup
21
PMAC2A PC104 Hardware Reference Manual
Using Flag I/O as General-Purpose I/O
Either the user flags or other not assigned axes flag on the base board can be used as general-purpose I/O
for up to 20 inputs and 4 outputs at 5-24Vdc levels. The indicated suggested M-variables definitions,
which are defined in the PMAC2 Software reference, allows accessing each particular line according to
the following table:
Flag
Type
HOME
PLIM
MLIM
USER
AENA
5-24 VDC Input
5-24 VDC Input
5-24 VDC Input
5-24 VDC Input
5-24 VDC Output
#1
M120
M121
M122
M115
M114
Channel Number
#2
#3
M220
M221
M222
M215
M214
M320
M321
M322
M315
M314
#4
M420
M421
M422
M415
M414
Note:
When using these lines as regular I/O points the appropriate setting of the Ix25
variable must be used to enable or disable the safety flags feature.
Analog Inputs Setup
The optional analog-to-digital converter inputs are ordered either through Option-12 on the CPU or Option2 on the axes expansion board. Each option provides two 12-bit analog inputs with a ±10Vdc range. The
M-variables associated with these inputs provided a range of values between +2048 and –2048 for the
respective ±10Vdc input range. The following is the software procedure to setup and read these ports.
CPU Analog Inputs
I903 = 1746
WX:$C014, $1FFFFF
M105->X:$0710,12,12,S
M205->X:$0711,12,12,S
22
;Set ADC clock frequency at 4.9152 MHz
;Clock strobe set for bipolar inputs
;ADCIN_1 on JMACH1 connector pin 45
;ADCIN_2 on JMACH1 connector pin 46
Software Setup
PMAC2A PC104 Hardware Reference Manual
HARDWARE REFERENCE SUMMARY
The following information is based on the PMAC2A PC/104 board, part number 603670-100.
Board Dimensions
From v106 to 107
(E20-23 added and 15A is in a different location:
Hardware Reference Summary
23
PMAC2A PC104 Hardware Reference Manual
From v107 to 108
W1 removed:
24
Hardware Reference Summary
PMAC2A PC104 Hardware Reference Manual
From v108 to 109
E20 in same location but rotated 90 degrees:
Hardware Reference Summary
25
PMAC2A PC104 Hardware Reference Manual
Board Layout
1
2
3
4
5
6
A
26
B
C
D
E
F
Feature
Location
Feature
Location
Feature
Location
E0
E1
E2
E3
E4
E8
E9
E10
E11
E12
B3
B4
B4
C4
C4
B1
B1
E5
E5
E5
E13
E14
E15A
E15B
E15C
E16
E18
E19
W1
E5
B3
E4
E4
E4
D1
D4
D4
E6
RP30
RP31
RP36
RP37
D1
D2
TB1
JRS232
JMACH1
JMACH2
E2
E2
E3
E3
A2
A3
B6
A2
F3
A4
Hardware Reference Summary
PMAC2A PC104 Hardware Reference Manual
Connectors and Indicators
J3 - Machine Connector (JMACH1 Port)
The primary machine interface connector is JMACH1, labeled J3 on the PMAC. It contains the pins for
four channels of machine I/O: analog outputs, incremental encoder inputs, amplifier fault and enable
signals and power-supply connections.
1. 50-pin female flat cable connector T&B Ansley P/N 609-5041
2. Standard flat cable stranded 50-wire T&B Ansley P/N 171-50
3. Phoenix varioface module type FLKM 50 (male pins) P/N 22 81 08 9
J4 - Machine Connector (JMACH2 Port)
This machine interface connector is labeled JMACH2 or J4 on the PMAC. It contains the pins for four
channels of machine I/O: end-of-travel input flags, home flag and pulse-and-direction output signals. In
addition, the B_WDO output allows monitoring the state of the Watchdog safety feature.
1. 34-pin female flat cable connector T&B Ansley P/N 609-3441
2. Standard flat cable stranded 34-wire T&B Ansley P/N 171-34
3. Phoenix varioface module type FLKM 34 (male pins) P/N 22 81 06 3
J8 - Serial Port (JRS232 Port)
This connector allows communicating with PMAC from a host computer through a RS-232 port. Delta
Tau provides the Accessory 3L cable that connects the PMAC to a DB-9 connector.
1. 10-pin female flat cable connector T&B Ansley P/N 609-1041
2. Standard flat cable stranded 10-wire T&B Ansley P/N 171-10
TB1 – Power Supply Terminal Block (JPWR Connector)
In almost in all cases the PMAC2A PC/104 will be powered from the PC/104 bus, when it is installed in a
host computer’s bus, or from the JMACH1 connector. This terminal block may be used as an alternative
power supply connector or to easily measure the voltages applied to the board.
1. 4-pin terminal block, 0.150 pitch
LED Indicators
D1: when this red LED is lit, it indicates that the watchdog timer has tripped and shut down the PMAC.
D2: when this green LED is lit, it indicates that power is applied to the +5V input.
Hardware Reference Summary
27
PMAC2A PC104 Hardware Reference Manual
28
Hardware Reference Summary
PMAC2A PC104 Hardware Reference Manual
E-POINT JUMPER DESCRIPTIONS
E0: Forced Reset Control
E Point and
Physical Layout
Location
Description
E0
B3
Factory use only; the board will not operate
with E0 installed.
Default
No jumper
E1: Servo and Phase Clock Direction Control
E Point and
Physical Layout
Location
Description
B4
Remove jumper for PMAC to use its
internally generated servo and phase clock
signals and to output these signals on the J8
serial port connector.
Jump pins 1 and 2 for PMAC to expect to
receive its servo and phase clock signals on
the J8 serial port connector.
E1
Default
No jumper installed
Note:
If the E1 jumper is ON and the servo and phase clocks are not brought in on the J8
serial port, the watchdog timer will trip immediately.
E2: CPU Frequency Select
E Point and
Physical Layout
Location
Description
B4
Remove jumper for 40 MHz operation (E4
OFF also) or for 80 MHz operation (E4
ON).
Jump pin 1 to 2 for 60 MHz operation (E4
OFF).
E2
Default
No jumper installed
E3: Normal/Re-Initializing Power-Up/Reset
E Point and Physical
Layout
E3
E-Point Jumper Descriptions
Location
Description
C4
Jump pin 1 to 2 to re-initialize on powerup/reset, loading factory default settings.
Remove jumper for normal power-up/reset,
loading user-saved settings.
Default
No jumper installed
29
PMAC2A PC104 Hardware Reference Manual
E4: CPU Frequency Select
E Point and
Physical Layout
E4
Location
Description
Default
C4
Remove jumper for 40 MHz operation (E2
OFF also) or for 60 MHz operation (E4 ON).
Jump pin 1 to 2 for 80 MHz operation (E2
OFF).
No jumper installed
(standard or Option 5EF)
Jumper installed (Option
5CF)
E8: Phase Clock Lines Output Enable
E Point and
Physical Layout
Location
Description
B1
Jump pin 1 to 2 to enable the PHASE clock
line on the J8 connector, allowing
synchronization with another PMAC.
Remove jumper to disable the PHASE clock
line on the J8 connector.
E8
Default
No Jumper
E9: Servo Clock Lines Output Enable
E Point and
Physical Layout
E9
Location
Description
Default
B1
Jump pin 1 to 2 to enable the SERVO clock
line on the J8 connector, allowing
synchronization with another PMAC.
No Jumper
Remove jumper to disable the SERVO clock
line on the J8 connector.
E10 – E12: Power-Up State Jumpers
E Point and
Physical Layout
Location
Description
Default
E10
E5
Remove jumper E10;
Jump E11;
Jump E12;
To read flash IC on power-up/reset
Other combinations are for factory use only;
the board will not operate in any other
configuration.
No E10 jumper installed;
Jump E11 and E12
E12
30
E-Point Jumper Descriptions
PMAC2A PC104 Hardware Reference Manual
E13: Power-Up/Reset Load Source
E Point and
Physical Layout
Location
Description
E13
E5
Jump pin 1 to 2 to reload firmware through
serial or bus port.
Remove jumper for normal operation.
Default
No jumper
E14: Watchdog Disable Jumper
E Point and
Physical Layout
Location
Description
E14
B3
Jump pin 1 to 2 to disable Watchdog timer
(for test purposes only).
Remove jumper to enable Watchdog timer.
Default
No jumper
E15A, B, C: Flash Memory Bank Select
E Point and
Physical Layout
Location
Description
E15A
E4
Remove all 3 jumpers to select flash memory
bank with factory-installed firmware.
Use other configuration to select one of the 7
other flash memory banks.
Default
No jumpers installed
E15C
E16: ADC Inputs Enable
E Point and
Physical Layout
Location
Description
D1
Jump pin 1 to 2 to enable the Option-12
ADC inputs.
Remove jumper to disable the ADC inputs,
which might be necessary for reading
current feedback signals from digital
amplifiers.
E16
E-Point Jumper Descriptions
Default
No jumper
31
PMAC2A PC104 Hardware Reference Manual
E18 – E19: PC/104 Bus Address
E Point and Physical
Layout
Location
Description
Default
D4
Jumpers E18 and E19 select the PC/104 bus
address for communications according to
the following table:
No E18 jumper installed;
Jumper E19 installed
E18
E19
E18
E19
Address
(Hex)
Address
(Dec)
OFF
OFF
$200
512
OFF
ON
$210
528
ON
OFF
$220
544
ON
ON
$230
560
Note:
Jumper E18 must be removed and jumper E19 must be installed for using either
the Ethernet or USB optional methods of communication.
E20-E23: ENCODER SINGLE ENDED/DIFFERENTIAL SELECT
(Note: v107 and above only)
E Point and
Physical Layout
E20
E21
E22
Location
Description
Default
Jump pin 2 to 3 to obtain differential 1-2 Jumper installed
encoder input mode. This will bias
encoder negative inputs to VCC = 5V
Jump pin 1 to 2 to obtain non-differential
encoder input mode. This will bias
encoder negative inputs to 1/2 VCC =
2.5V
E23
32
E-Point Jumper Descriptions
PMAC2A PC104 Hardware Reference Manual
CONNECTOR PINOUTS
TB1 (JPWR): Power Supply
(4-Pin Terminal Block)
Top View
Pin#
Symbol
Function
Description
Notes
1
GND
Common
Digital Common
2
+5V
Input
Logic Voltage
Supplies all PMAC digital circuits
3
+12V
Input
DAC Supply Voltage
Ref to Digital GND
4
-12V
Input
DAC Supply Voltage
Ref to Digital GND
This terminal block can be used to provide the input for the power supply for the circuits on the PMAC board
when it is not in a bus configuration. When the PMAC is in a bus configuration, these supplies automatically
come through the bus connector from the bus power supply; in this case, this terminal block should not be used.
J4 (JRS232) Serial Port Connector
(10-PIN CONNECTOR)
Front View
Pin#
Symbol
Function
Description
1
2
3
4
5
6
7
8
9
10
PHASE
DTR
TXD/
CTS
RXD/
RTS
DSR
SERVO
GND
+5V
Output
Bidirect
Input
Input
Output
Output
Bidirect
Output
Common
Output
Phasing Clock
Data Terminal Ready
Receive Data
Clear to Send
Send Data
Request to Send
Data Set Ready
Servo Clock
Digital Common
+5Vdc Supply
Connector Pinouts
Notes
Tied to "DSR"
Host transmit data
Host ready bit
Host receive data
PMAC ready bit
Tied to "DTR"
Power supply out
33
PMAC2A PC104 Hardware Reference Manual
J3 (JMACH1): Machine Port Connector
(50-Pin Header)
Top View
34
Pin#
Symbol
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
+5V
+5V
GND
GND
CHA1
CHA2
CHA1/
CHA2/
CHB1
CHB2
CHB1/
CHB2/
CHC1
CHC2
CHC1/
CHC2/
CHA3
CHA4
CHA3/
CHA4/
CHB3
CHB4
CHB3/
CHB4/
CHC3
CHC4
CHC3/
CHC4/
DAC1
DAC2
DAC1/
DAC2/
AENA1/
AENA2/
FAULT1/
FAULT2/
DAC3
DAC4
DAC3/
Output
Output
Common
Common
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Output
Description
+5V Power
+5V Power
Digital Common
Digital Common
Encoder A Channel Positive
Encoder A Channel Positive
Encoder A Channel Negative
Encoder A Channel Negative
Encoder B Channel Positive
Encoder B Channel Positive
Encoder B Channel Negative
Encoder B Channel Negative
Encoder C Channel Positive
Encoder C Channel Positive
Encoder C Channel Negative
Encoder C Channel Negative
Encoder A Channel Positive
Encoder A Channel Positive
Encoder A Channel Negative
Encoder A Channel Negative
Encoder B Channel Positive
Encoder B Channel Positive
Encoder B Channel Negative
Encoder B Channel Negative
Encoder C Channel Positive
Encoder C Channel Positive
Encoder C Channel Negative
Encoder C Channel Negative
Analog Output Positive 1
Analog Output Positive 2
Analog Output Negative 1
Analog Output Negative 2
Amplifier-Enable 1
Amplifier -Enable 2
Amplifier -Fault 1
Amplifier -Fault 2
Analog Output Positive 3
Analog Output Positive 4
Analog Output Negative 3
Notes
For encoders, 1
For encoders, 1
For encoders, 1
For encoders, 1
2
2
2,3
2,3
2
2
2,3
2,3
2
2
2,3
2,3
2
2
2,3
2,3
2
2
2,3
2,3
2
2
2,3
2,3
4
4
4,5
4,5
6
6
4
4
4,5
Connector Pinouts
PMAC2A PC104 Hardware Reference Manual
J3 JMACH1 (50-Pin Header)
(Continued)
Top View
Pin#
Symbol
Function
Description
Notes
40
DAC4/
Output
Analog Output Negative 4
4,5
41
AENA3/
Output
Amplifier -Enable 3
42
AENA4/
Output
Amplifier -Enable 4
43
FAULT3/
Input
Amplifier -Fault 3
6
44
FAULT4/
Input
Amplifier -Fault 4
6
45
ADCIN_1
Input
Analog Input 1
Option-12 required
46
ADCIN_2
Input
Analog Input 2
Option-12 required
47
FLT_FLG_V
Input
Amplifier Fault pull-up V+
48
GND
Common
Digital Common
49
+12V
Input
DAC Supply Voltage
7
50
-12V
Input
DAC Supply Voltage
7
The J3 connector is used to connect PMAC to the first 4 channels (Channels 1, 2, 3, and 4) of servo amps
and encoders.
Note 1: In standalone applications, these lines can be used as +5V power supply inputs to power PMAC’s
digital circuitry.
Note 2: Referenced to digital common (GND). Maximum of ±12V permitted between this signal and its
complement.
Note 3: Leave this input floating if not used (i.e. digital single-ended encoders).
Note 4: ±10V, 10 mA max, referenced to common ground (GND).
Note 5: Leave floating if not used. Do not tie to GND.
Note 6: Functional polarity controlled by variable Ix25. Must be conducting to 0V (usually GND) to
produce a 0 in PMAC software. Automatic fault function can be disabled with Ix25.
Note 7: Can be used to provide input power when the PC/104 bus connector is not being used. When the
bus configuratio is used, these supply voltages automatically come through the bus connector
from the PC power supply.
Connector Pinouts
35
PMAC2A PC104 Hardware Reference Manual
J4 (JMACH2): Machine Port CPU
Connector
(34-Pin Header)
Pin#
Symbol
Function
Description
Front View
Notes
1
FLG_1_2_V
Input
Flags 1-2 Pull-Up
2
FLG_3_4_V
Input
Flags 3-4 Pull-Up
3
GND
Common
Digital Common
4
GND
Common
Digital Common
5
HOME1
Input
Home-Flag 1
10
6
HOME2
Input
Home-Flag 2
10
7
PLIM1
Input
Positive End Limit 1
8,9
8
PLIM2
Input
Positive End Limit 2
8,9
9
MLIM1
Input
Negative End Limit 1
8,9
10
MLIM2
Input
Negative End Limit 2
8,9
11
USER1
Input
User Flag 1
12
USER2
Input
User Flag 2
13
PUL_1
Output
Pulse Output 1
14
PUL_2
Output
Pulse Output 2
15
DIR_1
Output
Direction Output 1
16
DIR_2
Output
Direction Output 2
17
EQU1
Output
Encoder Comp-Equal 1
18
EQU2
Output
Encoder Comp-Equal 2
19
HOME3
Input
Home-Flag 3
10
20
HOME4
Input
Home-Flag 4
10
21
PLIM3
Input
Positive End Limit 3
8,9
22
PLIM4
Input
Positive End Limit 4
8,9
23
MLIM3
Input
Negative End Limit 3
8,9
24
MLIM4
Input
Negative End Limit 4
8,9
25
USER1
Input
User Flag 3
26
USER2
Input
User Flag 4
27
PUL_3
Output
Pulse Output 3
28
PUL_4
Output
Pulse Output 4
29
DIR_3
Output
Direction Output 3
30
DIR_4
Output
Direction Output 4
31
EQU3
Output
Encoder Comp-Equal 3
32
EQU4
Output
Encoder Comp-Equal 4
33
B_WDO
Output
Watchdog Out
Indicator/driver
34
No Connect
Note 8: Pins marked PLIMn should be connected to switches at the positive end of travel. Pins marked MLIMn
should be connected to switches at the negative end of travel.
Note 9: Must be conducting to 0V (usually GND) for PMAC to consider itself not into this limit. Automatic limit
function can be disabled with Ix25.
Note 10: Functional polarity for homing or other trigger use of HOMEn controlled by Encoder/Flag Variable I9n2.
HMFLn selected for trigger by Encoder/Flag Variable I9n3. Must be conducting to 0V (usually GND) to
produce a 0 in PMAC software.
36
Connector Pinouts
PMAC2A PC104 Hardware Reference Manual
Connector Pinouts
37
PMAC2A PC104 Hardware Reference Manual
SCHEMATICS
38
Connector Pinouts
PMAC2A PC104 Hardware Reference Manual
BA08_A
BA09_A
BA08_A
BA09_A
BA10_A
BA11_A
BA10_A
BA11_A
BX/Y_A
BX/Y_A
R1
19.6608Mhz
10
C87
.1UF
19.6608Mhz
BH2
BH3
+5V
OR
BH4
BH5
BH6
BH7
A6
A7
C15
10UF
16V
(TANT)
VR1
LM1117MPX-3.3
MC33269ST-3.3
3
IN
OUT
GND
+3P3V
+
(SOT-223)
GND
X/Y
EXTAL
C16
10UF
16V
(TANT)
1
C88
RP3
.1UF
10
1
+5V
RP4
GND
+3P3V
+5V
RP7
10
1
10
1
10
3.3KSIP10C
GND
+12V
-12V
T/RRESET
-5V
+5V
2
3
4
5
6
7
8
9
SC02
BHACKBHREQDESRD0
STD0
SCK0
BB-
1
19
B0
B1
B2
B3
B4
B5
B6
B7
VCC
GND
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
U34
A0
A1
A2
A3
A4
A5
A6
A7
T/R
OE
2
3
4
5
6
7
8
9
BRTSTMS_U1
BGT/RBSTD1
BSRD1
BSCK1
BSC12
BTXD
12
RXD
13
BRTS-
11
CTS-
10
TXD
RXD
RXD
RTS
RTS
CTS
CTS
RXEN
10KSIP10C
RXD
CTSSER
PHA
BTA
IRQB-
20
10
C43
8
9
18
TXEN
BSC11
HEADER 10
(BOX)
SERVO
SERVO
PHA
SER
1OE
1A
2OE
2A
3OE
3A
4OE
4A
VSS
VDD
1Y
2Y
3Y
4Y
8
11
1
RP5A
3
1KSIP6I
M4
.1UF
HOLE
SER
+5V
C20
.1UF
9
BTA
8
GND
74ACT14
(SO14)
5
GND
CLK
MHR13FAJ19.6608
(4 PIN SMT)
CPUCLK
U2
4
2
2
3
4
5
6
7
8
9
MODA/IRQAMODB/IRQBMODC/IRQCBOOTENSC01
BTXD
BSC11
C22
GND
1
2 E13
1
.1UF
+5V
RP2
1
GND
JUMP `E0'
TO LOAD `isp' PART
E0
E0
4
RESET-
1KSIP6I
D3
RESET-
U4D
3
9
8
WDO-
WDO-
MMBD301LT1
(SO14)
74ACT14
1
2
3
4
5
6
7
8
+ C34
1UF
35V
tant
R3
100K
E14
RESET
Q3 3
2N7002
SOT23
(SOT23)
2
Q1
MMBT3906LT1
(SOT23)
6
1
2 E12
+3P3V
GUARD BAND
NC7SZ08M5
(SOT23-5)
1
2 E11
EXTAL
3
GND
3
2 E10
2
3
SOT23
2N7002
(SOT23)
RP5B
RESET
6
(SO14)
74ACT14
1
1
Q2
U3
N.C.
IN
N.C.
MODE
N.C.
TOL
N.C.
GND
N.C.
VCC
N.C.
NMI
N.C.
RST
N.C.
RST
PWDO-
16
15
14
13
12
11
10
9
U4E
11
WDO
D2
LED
GRN
PWR
U4F
C2
DS1231S
(SOL16)
10
WDO
(SO14)
74ACT14
13
.1UF
12
D1
LED
RED
WD
(SO14)
74ACT14
E14
1
D4
R4
1K
3
10
R5
1K
MMBD301LT1
3.3KSIP10C
GND
GND
TRST1
+3P3V
GND
BRCLK
GUARD BAND
CPUCLK
BSCANRESETTDI_U6
A0
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
RDWRTMS_U6
D5
+ C96
1SMC5.0AT3
22UF
35V
VCC
+12V
D6
+ C97
1SMC18AT3
22UF
35V
D7
C98
BD00_A
PA16
PA17
PA18
PA19
PA20
PA21
-12V
+
1SMC18AT3
FLASHCS-
TP1
GND
22UF
35V
TDO_U6
BD00_A
PA16
PA17
PA18
PA19
PA20
PA21
WDTC
FLASHCS-
N.C.
N.C.
S5
S4
SA11
SA10
SA9
SA8
SA7
SA6
SA5
N.C.
GND
GOE1
SA4
SA3
SA2
SA1
SA0
IOWIORLBENOEL
N.C.
N.C.
VCCIO
GND
I/O38
HRW
HDSHA2
HA1
HA0
INRDGOE0
SYSCLK
VCC
GND
Y2
N.C.
TCK
VMECSDPRCSCS0CS1CS4CS00IOCSVCCIO
GND
DSW05
DSW04
SA11
SA10
SA09
SA08
SA07
SA06
SA05
2 E19
1
2 E18
1
+5V
RP50
GND
+5V
3.3KSIP10C
1
1
1
SA04
SA03
SA02
SA01
SA00
SIOWSIORLBENOEL
1
GND
E1
2
CARD0
INRDXIN_0
XIN_1
2
2
40/60
E_51
XIN_2
XIN_3
E2
E3
E4
2
TBD_0
TBD_1
XIN_4
XIN_5
TBD_2
TBD_3
XIN_6
XIN_7
CS_00CS_0-
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CS_1CS_4DP_RCSVM_ECS-
BHR/W
BHDSBHA2
BHA1
BHA0
INRD-
PWDORESETC36
SYSCLK
TCK_U6
VM_ECSDP_RCSCS_0CS_1CS_4CS_00IOCS-
.1UF
U36
OE1
A0
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCC
A12
A13
GND
A14
A15
OE2
T/R1
B0
B1
GND
B2
B3
VCC
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BD01_A
BD02_A
BD03_A
BD04_A
BD05_A
BD06_A
BD07_A
CS00CS0CS1CS4DPRCSVMECSBWDO_ABRST_A-
BD01_A
BD02_A
BD03_A
BD04_A
BD05_A
BD06_A
BD07_A
CS00CS0CS1CS4DPRCSVMECSBWDO_ABRST_A-
C37
PI74FCT16245ATA
(TSSOP48)
.1UF
GND
IOCS-
ISPLSI2064E-100LT100-PC104
GND
C44
.1UF
C45
.1UF
C46
.1UF
GND
Connector Pinouts
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
U6
VCC10
GND
S6
S7
S8
S9
S10
S11
BRCLK
N.C.
CPUCLK
VCC
GND
BSCANRESETTDI
A0
A3
A4
A5
A6
A7
A8
VCCIO
GND
N.C.
N.C.
A9
A10
A11
A12
A13
A14
A15
RDWRTMS
GND
TDO
DB0
PA16
PA17
PA18
PA19
PA20
PA21
WDTC
PROMCSN.C.
N.C.
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
9
8
7
6
5
4
3
2
TDI_U1
TDO_U1
TCK_U1
RESETTRSTTDO_U6
TDI_U6
BSCAN-
GND
GND
+5V
+12V
-12V
Q4
2N7002
(SOT23)
2
+5V
RP1
3
SOT23
1
10
CE4
SER
74ACT14
(SO14)
+5V
3
2
1
2
9
8
7
6
5
4
3
2
M3
11
U35D
WAIT-
WAIT-
4
2
1
VCC
4
2
N.C.
E10
E11
E12
E13
+3P3V
GUARD BAND
Y1
5
1
HOLE
HOLE
10
PHA
U35E
12
74ACT14
(SO14)
74ACT14
(SO14)
(SO14)
74ACT14
1
5
RP5C
1KSIP6I
1
.1UF
GND
+5V
.1UF
PHA
U4C
3
74ACT14
(SO14)
C35
+5V
C33
GND
M1
CE3
4
74ACT14
(SO14)
+5V
2
1
GND
M2
3
U35F
6
GND
C21
.01UF
HOLE
2
74ACT14
(SO14)
U4B
1
C1
.1UF
TCK_U6
.1UF
PHASE
SERVO
C23
GND
R2
INIT-
TMS_U6
CE2
2
4
6
8
U35B
1
13
5
GND
.01UF
6
7
8
.1UF
E9
6
U35C
CARD0
RP8
U35A
14
3
74HC126C
(SO14)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
WDTC
1
2
3
4
CE1
E8
220SIP4X2
U8
1
2
4
5
10
9
13
12
7
PHASE
PHASE
KEY
(jisp)
J9
HSIP8NO5
8
7
6
5
GND
A
C
GND
GND
B
D
GND
1
3
5
7
.1UF
2
GND
3.3KSIP10C
TMS
GND
TCK
U9
1
2
3
4
+5V
.1UF
+3P3V
+3.3V
TDO
TDI
BSCAN-
J8 (JRS232)
PHASE
1
DTR
2
TXD3
CTS
4
RXD5
RTS
6
DSR
7
SERVO
8
GND
9
+5V
10
14
PC/104/HEADER/D20
J9
J8
.1UF
15
C19
10K
PC/104/HEADER/D20
J2D
0 1
MEMCS161 2
IOCS162 3
IRQ10
3 4
IRQ11
4 5
IRQ12
5 6
IRQ15
6 7
IRQ14
7 8
DACK08 9
DRQ0
9 10
DACK510 11
DRQ5
11 12
DACK612 13
DRQ6
13 14
DACK714 15
DRQ7
15 16
+5V
16 17
MASTER17 18
GND
18 19
GND
19 20
C2-
TXD
6
.1UF
GND
GND
C1-
.1UF
C41
5
SN75240PW
U4A
(KEY)
C42
7
VC2+
C1+
LTC1384CS
(SOL18)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
X/Y
WRRD-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
3.3KSIP10C
74LCX245
(TSSOP20)
GND
PC/104/HEADER_B32
J2C
GND
0 1
SBHE1 2
LA23
2 3
LA22
3 4
LA21
4 5
LA20
5 6
LA19
6 7
LA18
7 8
LA17
8 9
MEMR9 10
MEMW10 11
SD08
11 12
SD09
12 13
SD10
13 14
SD11
14 15
SD12
15 16
SD13
16 17
SD14
17 18
SD15
18 19
(KEY)
(KEY)
19 20
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
X/Y
WRRD-
10KSIP10C
2
3
4
5
6
7
8
9
2
+
+3P3V
GUARD BAND
GND
GND
BRXD
BCTSSER_A
PHA_A
TAMODD/IRQD-
4
+V
1
GND
GND
RP6
.1UF
2
A8
A9
A10
A11
IDT74FCT164245TPA
(TSSOP48)
GUARD BAND
NOTE2:
GND
INSTALL
`VR2,C17,C18'
FOR `DSP56309PW80'
AND `DSP56311GC150'
DO NOT INSTALL `F2'
3
1
LBENBH0
BH1
U7
.1UF
C40
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NOTE2:
.1UF
C39
17
*
+
2
SD06
SD07
BA06_A
BA07_A
OE1
A0
A1
GND
A2
A3
VCCA
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCCA
A12
A13
GND
A14
A15
OE2
C18
10UF
16V
(TANT)
2
SD04
SD05
U33
T/R1
B0
B1
GND
B2
B3
VCCB
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCCB
B12
B13
GND
B14
B15
T/R2
(SOT-223)
VSS
SD02
SD03
BA06_A
BA07_A
+3P3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
+
C38
INSTALL `F2' ONLY
FOR `DSP56303PW80'
DO NOT INSTALL
`VR2,C17,C18'
FOR `DSP56303PW80'
VCC
NOTE1:
GND
OEL
SD00
SD01
PC/104/HEADER_A32
J1B
GND
32
GND
31
OSC
30
+5V
29
BALE
28
TC
27
DACK226
IRQ3
25
IRQ4
24
IRQ5
23
IRQ6
22
IRQ7
21
SYSCLK
20
REFRESH19
DRQ1
18
DACK117
DRQ3
16
DACK315
SIOR14
SIOW13
SMEMR12
SMEMW11
(KEY)
(KEY)
10
+12V
9
ENDXFR8
-12V
7
DRQ2
6
-5V
5
IRQ9
4
+5V
3
RESTDRV
2
GND
1
+5V
VCCQL
2
10UF
16V
(TANT)
1
+5V
GND
SA00
SA01
SA02
SA03
SA04
SA05
SA06
SA07
SA08
SA09
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
AEN
IOCHRDY
SD00
SD01
SD02
SD03
SD04
SD05
SD06
SD07
IOCHCHK-
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VR2
LM1117MPX-1.8
MC33269ST-1.8
3
IN
OUT
1
C17
J1A
GND
OR
GND
+5V
16
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
ABOVE AGREEMENT.
39
C47
.1UF
SHEET2
670-0SH2
|Link
|670-0SH2.sch
Delta Tau Data Systems, Inc.
Title
PMAC-PC104, DSP56311 CPU & PC104 I/O SECTION
Size
D
Document Number
Date:
Monday, July 02, 2001
Rev
B
603670-320
Sheet
1
of
2
PMAC2A PC104 Hardware Reference Manual
BD00_A
BD02_A
BD04_A
BD06_A
BD08_A
BD10_A
BD12_A
BD14_A
BA00_A
BA02_A
BA04_A
BA06_A
BA08_A
BA10_A
BA12_A
BX/Y_A
(JEXP_A)
J11
BD00_A
BD02_A
BD04_A
BD06_A
BD08_A
BD10_A
BD12_A
BD14_A
BD16_A
BD18_A
BD20_A
BD22_A
BA00_A
BA02_A
BA04_A
BA06_A
BA08_A
BA10_A
BA12_A
BX/Y_A
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PWM~A~T1
PWM_B_T1
PWM_B_B1
PWM_B_T2
PWM_B_B2
PWM_B_T3
PWM_B_B3
PWM_B_T4
PWM_B_B4
ADC_A1
ADC_A2
ADC_A3
ADC_A4
ADC_B1
ADC_B2
ADC_B3
ADC_B4
ADC_STR
FAULT~1
FAULT~2
FAULT~3
FAULT~4
BA07_A
BA09_A
BA11_A
WAIT-
1 RP12A
2
100KSIP8I
1 RP13A
2
4
LF347M
6
5
U15B
5 RP14C
7
RP14D
47KSIP8I
C101
-12V
C109
470PF
.1UF
9
5 RP12C
6
100KSIP8I
5 RP13C
6
5
ENC_A3
13
OUT-C
EN-B,D
(SO14)
11
ENC_A4
3 RP17B
4
OUT-D
GND
DAC1+
ST34C86CF16
(SO16)
220SIP8I
3
47PF
LF347M
6
5
U16B
(SO14)
8
47KSIP8I
-12V
9
C111
470PF
2
1 RP19A
2
7 RP16D
6
47KSIP8I
3
13
12
U16D
24K
OUT-A
4
DAC2ENC_B2
5
ENC_B3
13
8
DAC2+
ENC_B4
220SIP8I
ST34C86CF16
(SO16)
5 RP18C
3
5 RP20C
7
U17B
6
9
47KSIP8I
100KSIP8I
5 RP19C
4
RP20D
47KSIP8I
C105
6
U25
VCC
1 RP23A
8
1 RP22A
2
ENC_C1
DAC3-
3
OUT-A
220SIP8I
(SO14)
4
3 RP22B
2
47KSIP8I
R15
13
12
U17D
24K
EN-A,C
IN-C
3 RP23B
14
4
ENC_C2
5
ENC_C3
13
12
ENC_C4
OUT-D
GND
4
3
7
C107
-12V
C115
470PF
.1UF
9
10
RP21D
47KSIP8I
4
47KSIP8I
6
47KSIP8I
(SO14)
5 RP23C
8
U18C
5 RP22C
6
DAC4-
7 RP22D
6
47KSIP8I
R17
24K
12
U18D
8
R20
D10
D11
.1UF
D12
D13
D14
D15
D16
D17
C68
D18
D19
.1UF
D20
D21
D22
D23
A0
A1
+3P3V
C69
A2
A3
.1UF
A4
A5
40
WRRD-
GND
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
A0
A1
A2
A3
A4
A5
WRRD-
IDT74FCT164245TPA
(TSSOP48)
U13
48
OE1
T/R1
47
B0
A0
46
A1
B1
45
GND
GND
44
A2
B2
43
A3
B3
42
VCCA
VCCB
41
A4
B4
40
A5
B5
39
GND
GND
38
A6
B6
37
A7
B7
36
A8
B8
35
A9
B9
34
GND
GND
33
A10
B10
32
A11
B11
31
VCCA
VCCB
30
A12
B12
29
A13
B13
28
GND
GND
27
A14
B14
26
A15
B15
25
OE2
T/R2
IDT74FCT164245TPA
(TSSOP48)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(SO8)
3
WDO
U14B
(SO8)
5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
HOME1+
PLIM1+
MLIM1+
USER1+
PUL_1+
DIR_1+
EQU_1+
HOME3+
PLIM3+
MLIM3+
USER3+
PUL_3+
DIR_3+
EQU_3+
B_WDO
FLAG_C1
FLAG_D1
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
FLAG_A2
FLAG_B2
HOME2+
PLIM2+
MLIM2+
USER2+
PUL_2+
DIR_2+
EQU_2+
HOME4+
PLIM4+
MLIM4+
USER4+
PUL_4+
DIR_4+
EQU_4+
FLAG_C2
FLAG_D2
FLAG_A3
FLAG_B3
FLAG_C3
FLAG_D3
FLAG_A4
FLAG_B4
FLAG_C4
FLAG_D4
BD00_A
BD01_A
CHC2-
6
CHC2+
14
CHC3+
15
CHC3-
9
CHC4-
10
CHC4+
6
AENA_2
WDO1
AENA_4
6
U21
OE1
A0
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCC
A12
A13
GND
A14
A15
OE2
T/R1
B0
B1
GND
B2
B3
VCC
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
5
AENA2-
3
AENA3-
5
AENA4-
DS75452N
U27B
(DIP8)
7 (SOCKET)
.1UF
+5V
+5V
GND
RP45
10
3.3KSIP10C
R24
.1UF
1
C121
100PF
C122
100PF
1
2
3
4
5
6
7
8
9
10
11
12
R25
20.0K/1%
1
3
5
7
2RP25
4
6
810KSIP8I
HOME1+
PLIM1+
MLIM1+
USER1+
1
3
5
7
2RP26
4
6
810KSIP8I
HOME2+
PLIM2+
MLIM2+
USER2+
1
3
5
7
2RP28
4
6
810KSIP8I
HOME3+
PLIM3+
MLIM3+
USER3+
1
3
5
7
2RP29
4
6
810KSIP8I
HOME4+
PLIM4+
MLIM4+
USER4+
3
LM6132AIM
R26
2
4.99K/1%
+
1
U19A
(SO8)
R27
20.0K/1%
100PF
U20
DGND
CH_B1+
CH_B1CH_B0+
CH_B0CH_A1+
CH_A1CH_A0+
CH_A0REF_IN
REF_OUT
AGND
+VD
SDO_A
SDO_B
BUSY
CLOCK
CSRD
CONVST
A0
M0
M1
+VA
24
23
22
21
20
19
18
17
16
15
14
13
FLAG_T1
FLAG_U1
FLAG_V1
FLAG_W1
FLAG_T2
FLAG_U2
FLAG_V2
FLAG_W2
RP46
2
3
4
5
6
7
8
9
FLAG_T3
FLAG_U3
FLAG_V3
FLAG_W3
FLAG_T4
FLAG_U4
FLAG_V4
FLAG_W4
ADC_A1
ADC_A2
10
3.3KSIP10C
ADC_CLK
ADC_CSADC_STR
+5V
ADS7861E
(SSOP24)
C125
4.99K/1%
C123
2
3
4
5
6
7
8
9
3.3KSIP10C
C124
ADCIN_1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AENA1-
DS75452N
U27A
(DIP8)
2 (SOCKET)
AENA_3
3
DS75452N
U26B
(DIP8)
7 (SOCKET)
WDO-
8
4.99K/1%
+5V
10
1
20.0K/1%
RP27
.1UF
74ACA6245
(dgg)
GND
C126
.1UF
.1UF
+
C127
10UF/10V
GND
FLT_FLG_V
GND
+5V
RP43
RP44
4.7KSIP10C
3.3KSIP10C
+5V
+5V
C67
FAULT_1
FAULT_2
FAULT_3
FAULT_4
EQU_1+
EQU_2+
EQU_3+
EQU_4+
.1UF
+5V
18
17
16
15
14
13
12
11
+5V
C66
GND
+5V
.1UF
BD14_A
BD15_A
+5V
C71
.1UF
BD22_A
BD23_A
BA00_A
BA01_A
+5V
C70
.1UF
FLT_FLG_V
(JMACH1)
J3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
CHA1+
CHA1CHB1+
CHB1CHC1+
CHC1CHA3+
CHA3CHB3+
CHB3CHC3+
CHC3DAC1+
DAC1AENA1FALT1DAC3+
DAC3AENA3FALT3ADCIN_1
BD16_A
BD17_A
BWR_ABRD_A-
7
AENA_1
R23
C73
BD06_A
BD07_A
BD08_A
BD09_A
BA04_A
BA05_A
CHC1-
+
7
U19B
(SO8)
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FLAG_A1
FLAG_B1
Flag_3_4_V
(JMACH2)
J4
DS75451M
(SOCKET)
BA02_A
BA03_A
CHC1+
1
10
U14A
DS75451M
(SOCKET)
6
BD18_A
BD19_A
2
(DIP8)
2 (SOCKET)
1
WDO
BD20_A
BD21_A
1
10
+5V
.1UF
1
BD12_A
BD13_A
16
1
C63
GND
D0
A0
BD10_A
BD11_A
6
4
Flag_1_2_V
GND
D1
BD04_A
BD05_A
RP24
10
1
D3
D2
BD02_A
BD03_A
GND
.1UF
U26A
+12V
+5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
HEADER 25X2
C75
.1UF
.1UF
WDO
PWM_A_T1
PWM_A_B1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PWM_A_T2
PWM_A_B2
PWM_A_T3
PWM_A_B3
PWM_A_T4
PWM_A_B4
PWM_C_T1
PWM_C_B1
PWM_C_T2
PWM_C_B2
PWM_C_T3
PWM_C_B3
PWM_C_T4
PWM_C_B4
WDO
GND
GND
Connector Pinouts
+5V
20
10
C85
GND
CHA2+
CHA2CHB2+
CHB2CHC2+
CHC2CHA4+
CHA4CHB4+
CHB4CHC4+
CHC4DAC2+
DAC2AENA2FALT2DAC4+
DAC4AENA4FALT4ADCIN_2
-12V
C74
U22
OE1
A0
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCC
A12
A13
GND
A14
A15
OE2
74ACA6245
(dgg)
T/R1
B0
B1
GND
B2
B3
VCC
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
U32
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
A3
A4
A5
A6
A7
A8
VCC
GND
G1
G2
2
3
4
5
6
7
8
9
FAULT~1
FAULT~2
FAULT~3
FAULT~4
1
3
5
7
2RP42
4
6
810KSIP8I
1
19
74AC541
(SOL20)
.1UF
FALT1FALT2FALT3FALT4EQU_1
EQU_2
EQU_3
EQU_4
SERVO
PHASE
SCLK
1 E16
ADC_CS-
2
JUMP E16 TO ENABLE ATD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PWM~A~T1
PWM~A~B1
GND
PWM~A~T2
PWM~A~B2
+5V
+5V
PWM~A~T3
PWM~A~B3
PWM~A~T4
PWM~A~B4
DIR_1+
PUL_1+
RP30
DIR_3+
PUL_3+
DIR_4+
PUL_4+
RP32
2.2KSIP10C
SIP SOCKET
DIR_2+
PUL_2+
1
6
5
4
3
2
RP33
1KSIP10C
CHA1CHB1CHC1-
CHA1+
CHB1+
CHC1+
1
2.2KSIP6C
RP31
GND
1
2.2KSIP6C
6
5
4
3
2
RP39
1KSIP10C
CHA3CHB3CHC3-
CHA3+
CHB3+
CHC3+
CHA4CHB4CHC4-
CHA4+
CHB4+
CHC4+
2.2KSIP6C
6
5
4
3
2
RP37
CHA2CHB2CHC2-
CHA2+
CHB2+
CHC2+
1
6
5
4
3
2
Delta Tau Data Systems, Inc.
Title
PMAC-PC104, MACHINE I/O & "JEXP" SECTION
2.2KSIP6C
GND
GND
RP38
2.2KSIP10C
SIP SOCKET
RP36
10
C65
+3P3V
.1UF
.1UF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
+5V
1
D6
D7
D8
D9
D4
D5
T/R1
B0
B1
GND
B2
B3
VCCB
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCCB
B12
B13
GND
B14
B15
T/R2
SSM-125-L-DV-LC
8
2
3
4
5
6
7
8
9
D4
D5
OE1
A0
A1
GND
A2
A3
VCCA
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCCA
A12
A13
GND
A14
A15
OE2
CHB4+
BRST_AGND
-12V
2
3
4
5
6
7
8
9
.1UF
D2
D3
U12
CHB4-
10
2
3
4
5
6
7
8
9
D2
D3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
9
GND
+12V
VMECSCS4BWDO_A-
HEADER 25X2(FEM)
CLS125LDDV
10
C64
+3P3V
D4
HEADER 17X2
IOCSD0
D1
Flag_3_4_V
3.3KSIP10C
7
IOCSD0
D1
CHB3-
1
`W1'= 1 TO 2 FOR 28F320J3A
`W1'= 2 TO 3 FOR 28F320J5A
+3P3V
C72
D5
C62
GND
Flag_1_2_V
D6
2
C61
.1UF
CHB3+
15
2
3
4
5
6
7
8
9
C60
.1UF
CHB2+
14
100PF
10
W1
+5V
1
3
+5V
6
BX/Y_A
CS1CS00-
guard band
R21
R22
D7
E28F320J3A
(TSOP56)
2
CHB2-
4.99K/1%
2
3
4
5
6
7
8
9
W1
SOLDER
JUMPER
1
CHB1-
7
1
LM6132AIM
10
+3P3V
A7
A6
A5
A4
A3
A2
A1
1
DAC4+
WRRDPRDY
1
A7
A6
RESETA11
A10
A9
A8
CHB1+
2
+5V
GND
BD01_A
BD03_A
BD05_A
BD07_A
BD09_A
BD11_A
BD13_A
BD15_A
BD17_A
BD19_A
BD21_A
BD23_A
BA01_A
BA03_A
BA05_A
VMECSCS4BWDO_ABRD_APHASE
BRST_A-
220SIP8I
2
3
4
5
6
7
8
9
RESETA11
A10
A9
A8
A15
A14
A13
A12
16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
+5V
7 RP23D
14
(SO14)
2
3
4
5
6
7
8
9
A15
A14
A13
A12
8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
8
5
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A24_WP
WEOESTS
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ12
DQ4
VCCQ
GND
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A00
BYTEA23
CE2
CHA4+
J5
BD00_A
BD02_A
BD04_A
BD06_A
BD08_A
BD10_A
BD12_A
BD14_A
BD16_A
BD18_A
BD20_A
BD22_A
BA00_A
BA02_A
BA04_A
BX/Y_A
CS1CS00BWR_ASERVO
19.6608Mhz
GND
2
3
4
5
6
7
8
9
FLASHCSPA21
PA20
PA19
PA18
PA17
PA16
U10
10
(JEXPA)
+5V
GND
47KSIP8I
LF347M
13
C120
A22
CE1A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RPA11
A10
A09
A08
GND
A07
A06
A05
A04
A03
A02
A01
CHA4-
.1UF
20.0K/1%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CHA3-
9
C78
GND
ADCIN_2
FLASHCSPA21
PA20
PA19
PA18
PA17
PA16
CHA3+
15
220SIP8I
(SO14)
8
3.3K
U18B
7
11
R32
CHA2+
14
DS75452N
C80
+
2
5
RP21B
47KSIP8I
5 RP21C
-
1 E15C
47PF
LF347M
6
+
47KSIP8I
2
-
1 RP21A
+
100KSIP8I
IN-D
ST34C86CF16
(SO16)
200.0K
1%
LF347M
-
+
1
U18A
(SO14)
C114
8
+3p3V
IN-B
EN-B,D
11
220PF
LF347M
2
7 RP19D
IN-B
IN-D
C119
47KSIP8I
8
IN-C
OUT-B
DAC3+
220SIP8I
(SO14)
OUT-C
R16
7 RP18D
IN-A
IN-A
4
47KSIP8I
LF347M
8
C113
470PF
.1UF
3
PWM~A~B4
6
C79
U17C
10
7
(SO14)
4
47KSIP8I
6
CHA2-
C77
4
5
47PF
RP20B
47KSIP8I
11
3 RP19B
6
LF347M
+
47KSIP8I
2
C112
-
2
1 RP20A
+
+
1
U17A
(SO14)
-
3
4
CHA1-
7
.1UF
200.0K
1%
LF347M
+
LF347M
+12V
3.3K
IN-D
GND
-
SCLK_DIR
3 RP18B
CHA1+
1
220PF
C106
R31
IN-D
OUT-D
R14
PWM~A~T4
2
IN-B
C118
.1UF
1 E15B
IN-C
OUT-B
EN-B,D
11
.1UF
47KSIP8I
-12V
3.3K
OUT-C
IN-B
12
7 RP17D
14
IN-A
EN-A,C
8
(SO14)
IN-A
IN-C
47KSIP8I
LF347M
R13
+12V
1 RP18A
100KSIP8I
6
220SIP8I
(SO14)
5 RP16C
C104
PWM~A~T3
5 RP17C
8
U16C
10
RP15D
47KSIP8I
C103
.1UF
6
47KSIP8I
ENC_B1
200.0K
1%
LF347M
7
RP15B
47KSIP8I
5 RP15C
7
2
.1UF
8
7 RP13D
C110
4
8
2
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
ABOVE AGREEMENT.
16
C76
VCC
4
47KSIP8I
11
7 RP12D
100KSIP8I
100KSIP8I
R30
IN-D
U24
+
PWM~A~B2
PWM~A~B3
2
IN-D
4
47KSIP8I
LF347M
13
14
12 U15D
-
1 RP15A
+
LF347M
+
1
U16A
(SO14)
2
GUARD BANDING REQ'D
1 E15A
IN-B
IN-B
220PF
3
3.3K
"E15" FLASH BANK SELECT
IN-C
OUT-B
C117
.1UF
47KSIP8I
-
GND
3 RP16B
24K
+
PRDY
3.3K
R37
ENC_A2
12
2
-
3.3K
R36
(SO14)
R11
3.3KSIP10C
WAIT-
DAC1-
R12
ADC_A1
ADC_A2
ADC_A3
ADC_A4
ADC_B1
ADC_B2
ADC_B3
ADC_B4
R35
2
220SIP8I
47KSIP8I
+12V
PWM~A~T2
IN-A
IN-A
EN-A,C
IN-C
1 RP17A
8
U15C
1 RP16A
C102
WAIT-
200.0K
1%
LF347M
10
7
4
47KSIP8I
6
47KSIP8I
(SO14)
8
100KSIP8I
3 RP13B
47PF
4
4
C108
RP14B
47KSIP8I
11
3 RP12B
2
3
1 RP14A
47KSIP8I
+
PWM~A~B1
OUT-A
4
-
2
+
10
LF347M
+
1
U15A
(SO14)
3
+5V
2
3
4
5
6
7
8
9
3
220PF
R10
SSM-125-L-DV-LC
RP10
VCC
ENC_A1
.1UF
47KSIP8I
-
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
+
J6
HEADER 25X2(FEM)
CLS125LDDV
1
U23
C116
+12V
-
DPRCS-
BA01_A
BA03_A
BA05_A
BA07_A
BA09_A
BA11_A
BA13_A
C100
(JEXPB)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
BD01_A
BD03_A
BD05_A
BD07_A
BD09_A
BD11_A
BD13_A
BD15_A
HEADER 20X2(FEM)
CLS120LDDV
SSM-120-L-DV-LC
PWM_A_T1
PWM_A_B1
PWM_A_T2
PWM_A_B2
PWM_A_T3
PWM_A_B3
PWM_A_T4
PWM_A_B4
PWM_C_T1
PWM_C_B1
PWM_C_T2
PWM_C_B2
PWM_C_T3
PWM_C_B3
PWM_C_T4
PWM_C_B4
ADC_CLK
AENA_1
AENA_2
AENA_3
AENA_4
BA06_A
BA08_A
BA10_A
DPRCS-
BD01_A
BD03_A
BD05_A
BD07_A
BD09_A
BD11_A
BD13_A
BD15_A
BD17_A
BD19_A
BD21_A
BD23_A
BA01_A
BA03_A
BA05_A
BA07_A
BA09_A
BA11_A
BA13_A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
670-0SH2.sch
Size
D
Document Number
Date:
Monday, July 02, 2001
Rev
B
603670-320
Sheet
2
of
2