Download Dataram DTM64332A memory module
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DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM Identification DTM64332A 256Mx72 2GB 2Rx8 PC3L-10600R-9-10-B0 Performance range Clock / Module Speed / CL-tRCD -tRP 667 MHz / PC3-10600 / 9-9-9 533 MHz / PC3-8500 / 8-8-8 533 MHz / PC3-8500 / 7-7-7 400 MHz / PC3-6400 / 6-6-6 Features Description 240-pin JEDEC-compliant DIMM, 133.35 mm wide by 30 mm high DTM64332A is a registered 256Mx72 memory module, which conforms to JEDEC's DDR3L, PC3L-10600 standard. The assembly is DualRank. Each Rank is comprised of nine 128Mx8 DDR3 Samsung SDRAMs. One 2K-bit EEPROM is used for Serial Presence Detect and a combination register/PLL, with Address and Command Parity, is also used. Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I/O signals in a Fly-by topology. A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C. Operating Voltage: VDD = VDDQ = +1.35V (1.283V to 1.45V) Backward-compatible to VDD = VDDQ = +1.5V ±0.075V On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM Data Transfer Rate: 10.6 Gigabytes/sec Data Bursts: 8 and burst chop 4 mode ZQ Calibration for Output Driver and On-Die Termination (ODT) Programmable ODT / Dynamic ODT during Writes Programmable CAS Latency: 6, 7, 8, and 9 Bi-Directional Differential Data Strobe signals SDRAM Addressing (Row/Col/Bank): 14/10/3 Fully RoHS Compliant Pin Configuration Front Side Pin Description Back Side Name Function 1 VREFDQ 31 DQ25 61 A2 91 DQ41 121 VSS 151 VSS 181 A1 211 VSS CB[7:0] Data Check Bits 2 VSS 32 VSS 62 VDD 92 VSS 122 DQ4 152 DM3 182 VDD 212 DM5 DQ[63:0] Data Bits 3 4 5 6 33 /DQS3 34 DQS3 35 VSS 36 DQ26 63 64 65 66 CK1* /CK1* VDD VDD 93 94 95 96 /DQS5 DQS5 VSS DQ42 123 DQ5 124 VSS 125 DM0 126 /TDQS9 153 154 155 156 183 184 185 186 213 214 215 216 DQS[8:0], /DQS[8:0] DM[8:0] /TDQS[17:9] CK[1:0], /CK[1:0] Differential Data Strobes Data Mask Termination Data Strobes Differential Clock Inputs 7 DQS0 37 DQ27 8 VSS 38 VSS 9 DQ2 39 CB0 67 68 69 VREFCA PAR_IN VDD 97 98 99 DQ43 VSS DQ48 127 VSS 128 DQ6 129 DQ7 157 VSS 158 CB4 159 CB5 187 /Event 188 A0 189 VDD 217 VSS 218 DQ52 219 DQ53 CKE[1:0] /CAS /RAS Clock Enables Column Address Strobe Row Address Strobe 10 DQ3 40 CB1 70 A10/AP 100 DQ49 130 VSS 160 VSS 190 BA1 220 VSS /S[3:0] Chip Selects 11 VSS 12 DQ8 41 VSS 42 /DQS8 71 72 BA0 VDD 101 VSS 102 /DQS6 131 DQ12 132 DQ13 161 DM8 191 VDD 162 /TTDQS17 192 /RAS 221 DM6 222 /TDQS15 /WE A[15:0] Write Enable Address Inputs 13 DQ9 43 DQS8 73 /WE 103 DQS6 133 VSS 163 VSS 14 VSS 15 /DQS1 16 DQS1 17 VSS 44 VSS 45 CB2 46 CB3 47 VSS 74 75 76 77 /CAS VDD /S1 ODT1 104 105 106 107 134 DM1 164 135 /TDQS10 165 136 VSS 166 137 DQ14 167 78 79 80 VDD 108 DQ56 /S2, NC* 109 DQ57 VSS 110 VSS 21 DQ16 51 VDD 81 DQ32 22 DQ17 23 VSS 24 /DQS2 25 DQS2 26 VSS 27 DQ18 82 83 84 85 86 87 DQ33 VSS /DQS4 DQS4 VSS DQ34 88 89 90 DQ35 VSS DQ40 118 SCL 119 SA2 120 VTT DQ0 DQ1 VSS /DQS0 18 DQ10 48 VTT 19 DQ11 49 VTT 20 VSS 50 CKE0 52 BA2 53 /ERR_OUT 54 VDD 55 A11 56 A7 57 VDD 28 DQ19 58 A5 29 VSS 59 A4 30 DQ24 60 VDD VSS DQ50 DQ51 VSS /TDQS12 VSS DQ30 DQ31 VDD CK0 /CK0 VDD 193 /S0 CB6 194 CB7 195 VSS 196 NC (TEST) 197 VDD ODT0 A13 VDD /TDQS14 VSS DQ46 DQ47 223 VSS BA[2:0] Bank Addresses 224 225 226 227 ODT[1:0] SA[2:0] SCL SDA On Die Termination Inputs SPD Address SPD Clock Input SPD Data Input/Output DQ54 DQ55 VSS DQ60 138 DQ15 139 VSS 140 DQ20 168 /RESET 169 CKE1 170 VDD 198 /S3, NC* 199 VSS 200 DQ36 228 DQ61 229 VSS 230 DM7 VSS VDD VDDSPD Ground Power SPD EEPROM Power 111 /DQS7 141 DQ21 171 A15 201 DQ37 231 /TDQS16 VREFDQ Reference Voltage for DQ 112 113 114 115 116 117 142 VSS 172 143 DM2 173 144 /TDQS11 174 145 VSS 175 146 DQ22 176 147 DQ23 177 202 203 204 205 206 207 232 233 234 235 236 237 VREFCA VTT /Event NC Reference Voltage for CA Termination Voltage Temperature Sensing No Connection DQS7 VSS DQ58 DQ59 VSS SA0 148 VSS 149 DQ28 150 DQ29 A14 VDD A12/ /BC A9 VDD A8 178 A6 179 VDD 180 A3 VSS DM4 /TQDS13 VSS DQ38 DQ39 208 VSS 209 DQ44 210 DQ45 VSS DQ62 DQ63 VSS VDDSPD SA1 238 SDA 239 VSS 240 VTT * Not used Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 Page 1 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM Front view 133.35 [5.250] 9.50 [0.374] 30.00 [1.181] 17.30 [0.681] 5.00 [0.197] 5.175 [0.204] 47.00 [1.850] 71.00 [2.795] 2.50 [0.098] 123.00 [4.843] Back view Side view 4.00Max [0.157] Max 4.00 Min [0.157] Min 1.27 ±.10 [0.0500 ±0.0040] Notes Tolerances on all dimensions except where otherwise indicated are ±.13 (.005). All dimensions are expressed: millimeters [inches] Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 Page 2 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM /RS1 /RS0 DQSR0 /DQSR0 DMR0 /TDQSR9 I/O[7:0] I/O[7:0] RANK 1 DQR[39:32] I/O[7:0] DQR[47:40] /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS I/O[7:0] RANK 1 /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS I/O[7:0] I/O[7:0] I/O[7:0] DQR[55:48] I/O[7:0] /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS I/O[7:0] DM TDQS /CS DQSR6 /DQSR6 DMR6 /TDQSR15 I/O[7:0] DQR[63:56] I/O[7:0] I/O[7:0] /DQS DQS DM TDQS /CS /DQS DQS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS I/O[7:0] NU /TDQS DQSR7 /DQSR7 DMR7 /TDQSR16 DQSR3 /DQSR3 DMR3 /TDQSR12 DQR[31:24] RANK 0 DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS I/O[7:0] DQSR2 /DQSR2 DMR2 /TDQSR11 DQR[23:16] I/O[7:0] DQSR5 /DQSR5 DMR5 /TDQSR14 DQSR1 /DQSR1 DMR1 /TDQSR10 DQR[15:8] DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS RANK 0 DM TDQS /CS DQR[7:0] /DQS DQS DM TDQS /CS NU /TDQS DQSR4 /DQSR4 DMR4 /TDQSR13 I/O[7:0] CBR[7:0] I/O[7:0] /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS DQSR8 /DQSR8 DMR8 /TDQSR17 I/O[7:0] V DD TO SDRAMS All 22 OHMS All 15 OHMS DQR[63:0] DQ[63:0] CB[7:0] CBR[7:0] /RS0 /RS1 /S0 /S1 BA[2:0] BA[2:0]R A[15:0]R A[15:0] DQSR[8:0] /RAS /RASR /DQS[8:0] /DQSR[8:0] /CAS /WE /CASR /WER DMR[8:0] CKE0 /TDQSR[17:9] CKE1 ODT0 DM[8:0] REG / PLL DQS[8:0] /TDQS[17:9] ODT1 All 39 OHMS BA[2:0]R ODT1R CK0 120 OHMS /CK0 L,R(CLK)[1:0] /L,R(CLK)[1:0] LCLK[1:0] RCLK[1:0] /RCLK[1:0] DECOUPLING V DDSPD V DD V REF_DQ V SS VREF_CA V TT Serial PD All Devices All SDRAMs All Devices All SDRAMs All SDRAMs /RESET A[15:0]R /RASR SDRAMS /CASR /WER VTT /EVENT All 240 OHMS All 39 OHMS CKE[1:0]R ODT[1:0]R RS[1:0] All 39 OHMS 100 nF /LCLK[1:0] CKE0R CKE1R ODT0R /ERR_OUT PAR_IN GLOBAL SDRAM CONNECTS VDD All 39 OHMS 100 nF SCL ZQ VTT VSS Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 TEMPERATURE MONITOR/ SERIAL PD SA0 SA1 SDA SA2 Page 3 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM Absolute Maximum Ratings (Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.) PARAMETER Symbol Minimum Maximum Unit Temperature, non-Operating TSTORAGE -55 100 C TA 0 70 C Ambient Temperature, Operating TCASE 0 95 C VDD -0.4 1.975 V VIN,VOUT -0.4 1.975 V DRAM Case Temperature, Operating Voltage on VDD relative to VSS Voltage on Any Pin relative to VSS Notes: DRAM Operating Case Temperature above 85C requires 2X refresh. Recommended DC Operating Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Power Supply Voltage I/O Reference Voltage I/O Reference Voltage Symbol Operation Voltage VDD VREFDQ VREFCA Minimum Typical Maximum 1.35V 1.283 1.35 1.4500 1.5V 1.425 1.5 1.575 0.49 VDD 0.50 VDD 0.51 VDD V 1 0.49 VDD 0.50 VDD 0.51 VDD V 1 1.35V 1.5V 1.35V 1.5V Unit Note V Notes: 1) For Reference VDD/2 ± 15 mV. The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may not exceed ±1% of its DC value. For Reference: VREF = VDD/2 ± 15 mV. DC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) Symbol Operation Voltage Minimum Maximum Unit Logical High (Logic 1) VIH(DC) 1.35V VREF + 0.09 VDD V 1.5V VREF + 0.1 VDD Logical Low (Logic 0) VIL(DC) 1.35V VSS VREF - 0.09 1.5V VSS VREF - 0.1 PARAMETER V AC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Logical Low (Logic 0) Symbol Operation Voltage Minimum Maximum Unit VIH(AC) 1.35V VREF + 0.160 - V 1.5V VREF + 0.175 - 1.35V - VREF - 0.160 1.5V - VREF - 0.175 VIL(AC) Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 V Page 4 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM Differential Input Logic Levels (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Differential Input Logic High Differential Input Logic Low Differential Input Cross Point Voltage relative to VDD/2 Symbol VIH.DIFF Minimum +0.200 Maximum DC:VDD AC:VDD+0.4 Unit V VIL.DIFF DC:VSS AC:VSS-0.4 -0.200 V VIX - 0.150 + 0.150 V Capacitance (TA = 25 C, f = 100 MHz) PARAMETER Pin Symbol Minimum Maximum Unit CCK 1.5 2.5 pF pF Input Capacitance, Clock CK0, /CK0 Input Capacitance, Address BA[2:0], A[15:0], /RAS, /CAS, /WE CI 1.5 2.5 Input Capacitance Control /S[1:0], CKE[1:0], ODT[1:0] CI 1.5 2.5 Input/Output Capacitance DQ[63:0], CB[7:0] DQS[8:0], /DQS[8:0], DM[8:0], TDQS[17:9] CIO 3 5 pF DC Characteristics (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Input Leakage Current Symbol Minimum Maximum Unit Note IIL -18 +18 μA 1,2 IOL -10 +10 μA 2,3 (Any input 0 V < VIN < VDD) Output Leakage Current (0V < VOUT < VDDQ) Notes: 1) All other pins not under test = 0 V 2) Values are shown per pin 3) DQ, DQS, DQS and ODT are disabled Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 Page 5 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM IDD Specifications and Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Operating One Bank ActivePrecharge Current Operating One Bank Active-ReadPrecharge Current Precharge PowerDown Current Precharge PowerDown Current Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Write Current Operating Burst Read Current Burst Refresh Current Self Refresh Current Operating Bank Interleave Read Current Symbol IDD0 IDD1 IDD2P IDD2P IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5 IDD6 IDD7 Test Condition Operating current : One bank ACTIVATE-to-PRECHARGE Operating current : One bank ACTIVATE-to-READ-toPRECHARGE Precharge power down current: (Slow exit) Precharge power down current: (Fast exit) Precharge quiet standby current Precharge standby current Active power-down current Active standby current Burst write operating current Burst read operating current Refresh current Self-refresh temperature current: MAX TC = 85°C All bank interleaved read current Max Value Unit 1.35V 1.5V 1340 1385 mA 1430 1475 mA 790 790 mA 880 970 mA 1020 1110 mA 1130 1130 mA 1060 1060 mA 1480 1570 mA 1800 1890 mA 1745 1835 mA 1885 1930 mA 780 780 mA 2420 2510 mA * One module rank in this operation the rest in IDD2P slow exit. ** All module ranks in this operation. Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 Page 6 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data tAA 13.125 20 ns CAS-to-CAS Command Delay tCCD 4 - tCK tCH(avg) 0.47 0.53 tCK tCK 1.5 1.875 ns tCL(avg) 0.47 0.53 tCK tDH 65 - ps Clock High Level Width Clock Cycle Time Clock Low Level Width Data Input Hold Time after DQS Strobe tDIPW 400 - ps DQS Output Access Time from Clock tDQSCK -255 +255 ps Write DQS High Level Width tDQSH 0.45 0.55 tCK(avg) Write DQS Low Level Width tDQSL 0.45 0.55 tCK(avg) DQS-Out Edge to Data-Out Edge Skew tDQSQ - 125 ps Data Input Setup Time Before DQS Strobe tDS 30 - ps DQS Falling Edge from Clock, Hold Time tDSH 0.2 - tCK(avg) DQS Falling Edge to Clock, Setup Time tDSS 0.2 - tCK(avg) Clock Half Period tHP minimum of tCH or tCL - ns Address and Command Hold Time after Clock tIH 140 - ps DQ Input Pulse Width tIS 65 - ps Load Mode Command Cycle Time tMRD 4 - tCK DQ-to-DQS Hold tQH 0.38 - tCK(avg) Active-to-Precharge Time tRAS 36 9*tREFI ns Active-to-Active / Auto Refresh Time tRC 49.125 - ns RAS-to-CAS Delay tRCD 13.125 - ns - 7.8 μs Address and Command Setup Time before Clock o o tREFI o o Average Periodic Refresh Interval 0 C < TCASE < 95 C tREFI - 3.9 μs Auto Refresh Row Cycle Time tRFC 110 - ns Row Precharge Time tRP 13.125 - ns Read DQS Preamble Time tRPRE 0.9 Note-1 tCK(avg) Read DQS Postamble Time tRPST 0.3 Note-2 tCK(avg) Row Active to Row Active Delay tRRD Max(4nCK, 6ns) - ns Internal Read to Precharge Command Delay tRTP Max(4nCK, 7.5ns) - ns Average Periodic Refresh Interval 0 C < TCASE < 85 C Write DQS Preamble Setup Time tWPRE 0.9 - tCK(avg) Write DQS Postamble Time tWPST 0.3 - tCK(avg) Write Recovery Time tWR 15 - ns Internal Write to Read Command Delay tWTR Max(4nCK, 7.5ns) - ns Notes: 1. 2. The maximum preamble is bound by tLZDQS(min) The maximum postamble is bound by tHZDQS(max) Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 Page 7 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte # 0 Function. Value Hex Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage. Bit 3 ~ Bit 0. SPD Bytes Used 176 Bit 6 ~ Bit 4. SPD Bytes Total 256 Bit 7. CRC Coverage Bytes 0-116 SPD Revision. Rev. 1.0 0x92 2 Key Byte / DRAM Device Type. 0x0B 3 Key Byte / Module Type. 1 DDR3 SDRAM 0x01 Bit 3 ~ Bit 0. Module Type Bit 7 ~ Bit 4. Reserved - 4 6 SDRAM Density and Banks. Bit 3 ~ Bit 0. Total SDRAM capacity, in megabits Bit 6 ~ Bit 4. Bank Address Bits Bit 7. Reserved SDRAM Addressing. Bit 2 ~ Bit 0. Column Address Bits Bit 5 ~ Bit 3. Row Address Bits Bit 7, 6. Reserved Module Nominal Voltage, VDD. 7 Module Organization. 5 RDIMM 0 0x02 1Gb 8 banks 0 0x11 10 14 0 1.35 V operable. 8-Bits 2-Rank 0 10 Module Memory Bus Width. Bit 2 ~ Bit 0. Primary bus width, in bits Bit 4, Bit 3. Bus width extension, in bits Bit 7 ~ Bit 5. Reserved Fine Timebase (FTB) Dividend / Divisor. Bit 3 ~ Bit 0. Fine Timebase (FTB) Divisor Bit 7 ~ Bit 4. Fine Timebase (FTB) Dividend Medium Timebase (MTB) Dividend. 11 Medium Timebase (MTB) Divisor. 12 SDRAM Minimum Cycle Time (tCKmin). 2 5 1 (MTB = 0.125ns) 8 (MTB = 0.125ns) 1.5ns 13 Reserved. UNUSED 14 CAS Latencies Supported, Least Significant Byte. 9 0x02 0x09 Bit 2 ~ Bit 0. SDRAM Device Width Bit 5 ~ Bit 3. Number of Ranks Bit 7, 6. Reserved 8 0x10 Bit 0. CL = 4 Bit 1. CL = 5 Bit 2. CL = 6 Bit 3. CL = 7 Bit 4. CL = 8 Bit 5. CL = 9 Bit 6. CL = 10 Bit 7. CL = 11 Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 0x0B 64-Bits 8-Bits 0 0x52 0x01 0x08 0x0C 0x00 0x3C X X X X Page 8 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM 15 CAS Latencies Supported, Most Significant Byte. 0x00 Bit 0. CL = 12 Bit 1. CL = 13 Bit 2. CL =14 Bit 3. CL = 15 Bit 4. CL = 16 Bit 5. CL = 17 Bit 6. CL = 18 Bit 7. Reserved. 16 Minimum CAS Latency Time (tAAmin). 17 Minimum Write Recovery Time (tWRmin). 18 Minimum RAS# to CAS# Delay Time (tRCDmin). 19 Minimum Row Active to Row Active Delay Time (tRRDmin). 20 Minimum Row Precharge Delay Time (tRPmin). 21 Upper Nibbles for tRAS and tRC. Bit 3 ~ Bit 0. tRAS Most Significant Nibble Bit 7 ~ Bit 4. tRC Most Significant Nibble Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte. Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte. Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte. Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte. Minimum Internal Write to Read Command Delay Time (tWTRmin). Minimum Internal Read to Precharge Command Delay Time (tRTPmin). Upper Nibble for tFAW. Bit 3 ~ Bit 0. tFAW Most Significant Nibble Bit 7 ~ Bit 4. Reserved Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte. SDRAM Optional Features. Bit 0. RZQ / 6 Bit 1. RZQ / 7 Bit 6 ~ Bit 2. Reserved Bit 7. DLL-Off Mode Support SDRAM Drivers Supported. Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh (ASR) On-die Thermal Sensor (ODTS) Readout Reserved Reserved Reserved Partial Array Self Refresh (PASR) Module Thermal Sensor. Bit 6 ~ Bit 0. Thermal Sensor Accuracy - 22 23 24 25 26 27 28 29 30 31 32 Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 13.125ns 0x69 15.0ns 0x78 13.125ns 0x69 6.0ns 0x30 13.125ns 0x69 0x11 1 1 36.0ns 0x20 49.125ns 0x89 110.0ns 0x70 110.0ns 0x03 7.5ns 0x3C 7.5ns 0x3C 0x00 0 0 30.0ns 0xF0 0x83 X X 0x05 X X 0x80 0 Page 9 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM 33 3459 60 Bit 7. Thermal Sensor SDRAM Device Type. Bit 6 ~ Bit 0. Non-Standard Device Description Bit 7. SDRAM Device Type Reserved 67 Module Nominal Height. Bit 4 ~ Bit 0. Module Nominal Height max, in mm Bit 7 ~ Bit5. Reserved Module Maximum Thickness. Bit 3 ~ Bit 0. Front, in mm (baseline thickness = 1 mm) Bit 7 ~ Bit 4. Back, in mm (baseline thickness = 1 mm) Reference Raw Card Used. Bit 4 ~ Bit 0. Reference Raw Card Bit 6, Bit 5. Reference Raw Card Revision Bit 7. Reserved (Registered) DIMM Module Attributes. Bit 1 ~ Bit 0. # of Registers used on RDIMM Bit 3 ~ Bit 2. # of Rows of DRAMs on RDIMM Bit 7 ~ Bit 4. Reserved RDIMM Thermal Heat Spreader Solution. Bit 6 ~ Bit 0. Heat Spreader Thermal Characteristics Bit 7. Heat Spreader Solution Register Manufacturer ID Code, Least Significant Byte (Optional). Register Manufacturer ID Code, Most Significant Byte (Optional). Register Revision Number (Optional). 68 Register Type. 69 Bit[2-0] Support Device Bit[7-3] Reserved [SSTE32882]: RC1 (MS Nibble) / RC0 (LS Nibble) 61 62 63 64 65 66 70 With TS 0x00 0 Std Mono UNUSED 0x00 0x0F 29<h<=30 0 0x11 1<th<=2 1<th<=2 0x01 R/C B Rev.0 0 0x05 1 Register 1 Row 0 0x00 0 No HS UNUSED 0x00 UNUSED 0x00 0xFF 0x00 SSTE32882 0 UNUSED 0x00 72 [SSTE32882]: RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address. Bit 1, Bit 0. RC2/DA3,4 Value.RESERVED Bit 3, Bit 2. RC2/DBA0,1 Value RESERVED Bit 5, Bit 4. RC3/DA4,3 value, Command/Address A Outputs Moderate Bit 7, Bit 6. RC3/DBA0,1 value, Command/Address B Outputs Moderate [SSTE32882]: RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock. Bit 1, Bit 0. RC4/DA3,4 Control Signals, A Outputs.Light Bit 3, Bit 2. RC4/DBA0,1 Control Signals, B Outputs Light Bit 5, Bit 4. RC5/DA4,3 value, Y1/Y1# and Y3/Y3# Clock Light Outputs Bit 7, Bit 6. RC5/DBA0,1 value, Y0/Y0# and Y2/Y2# Clock Light Outputs [SSTE32882]: RC7 (MS Nibble) / RC6 (LS Nibble). UNUSED 0x00 73 [SSTE32882]: RC9 (MS Nibble) / RC8 (LS Nibble). UNUSED 0x00 74 [SSTE32882]: RC11 (MS Nibble) / RC10 (LS Nibble). UNUSED 0x00 75 [SSTE32882]: RC13 (MS Nibble) / RC12 (LS Nibble). UNUSED 0x00 71 Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 0x50 0x00 Page 10 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM 76 77112 113 114116 117 118 119 120, 121 122125 126 127 128131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146, 147 148 149 150175 176255 [SSTE32882]: RC15 (MS Nibble) / RC14 (LS Nibble). UNUSED 0x00 Module-Specific Section UNUSED 0x00 Module-Specific Section. Module-Specific Section UNUSED UNUSED 0x00 0x00 Module Manufacturer ID Code, Least Significant Byte Module Manufacturer ID Code, Most Significant Byte Module Manufacturing Location Module Manufacturing Date UNUSED Module Serial Number Cyclical Redundancy Code (CRC). Cyclical Redundancy Code (CRC). Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Revision Code 0x01 0x91 0x00 0x20 0x20 CRC CRC 0xE4 0x44 0x20 D A T A R A M 0x44 0x41 0x54 0x41 0x52 0x41 0x4D 0x20 0x36 0x34 0x33 0x33 0x32 0x20 0x20 6 4 3 3 2 DRAM Manufacturer ID Code, Least Significant Byte DRAM Manufacturer ID Code, Most Significant Byte Manufacturer’s Specific Data UNUSED UNUSED UNUSED 0x00 0x00 0x00 Open for customer use UNUSED 0x00 Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 Page 11 DTM64332A 2GB - 240-Pin 2Rx8 Registered ECC LV DDR3 DIMM DATARAM CORPORATION, USA Corporate Headquarters, P.O.Box 7528, Princeton, NJ 08543-7528; Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com All rights reserved. The information contained in this document has been carefully checked and is believed to be reliable. However, Dataram assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Dataram. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Dataram. Document 06582, Revision A, 21-May-10, Dataram Corporation © 2010 Page 12