Download Transcend 256MB SDRAM 144Pin SO-DIMM PC100 Unbuffer Non-ECC Memory

144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
Placement
Description
The TS32MSS64V8L2 is a 32M bit x 64 Synchronous
Dynamic
RAM
high-density
memory
module.
The
TS32MSS64V8L2 consists of 16 pcs of CMOS 16Mx8bits
Synchronous DRAMs in 54pins sTSOP packages and a
B
2048 bits serial EEPROM on a 144-pin printed circuit
D
board. The TS32MSS64V8L2 is a Dual In-Line Memory
A
Module and is intended for mounting into 144-pin edge
connector sockets.
Synchronous design allows precise cycle control with the
F
E
use of system clock. I/O transactions are possible on every
clock
cycle.
Range
of
operation
frequencies,
programmable latencies allow the same device to be useful
G
for a variety of high bandwidth, high performance memory
H
system applications.
K
I
J
Features
•
Performance Range: PC100 CL2
•
Burst Mode Operation.
•
Auto and Self Refresh.
•
Serial Presence Detect (SPD) with serial
PCB : 09-1100
EEPROM
•
LVTTL compatible inputs and outputs.
•
Single 3.3V ± 0.3V power supply.
•
MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
•
All inputs are sampled at the positive going edge
of the system clock.
Transcend information Inc
C
1
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
Pin Identification
Dimensions
Side
Millimeters
Inches
Symbol
Function
A
67.60 ± 0.200
2.661 ± 0.008
A0~A11
Address inputs
B
32.80
1.291
BA0, BA1
Select Bank
C
23.20
0.913
DQ0~DQ63
Data inputs/outputs
D
4.60
0.181
E
3.30
0.130
CLK0, CLK1
Clock Input
F
2.50
0.098
CKE0, CKE1
Clock Enable Input
G
4.00
0.157
/CS0, /CS1
Chip Select Input
H
6.00
0.236
/RAS
Row address strobe
I
20.00
0.787
/CAS
Column address strobe
J
31.75 ± 0.200
1.250 ± 0.008
/WE
Write Enable
K
1.00 ± 0.100
0.039 ± 0.004
DQM0~7
DQM
Vcc
Power Supply
Vss
Ground
SDA
Serial Address / Data I/O
SCL
Serial Clock
NC
No Connection
Transcend information Inc
2
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
Pinouts
Pin
Pin
Pin Pin
No
Name
No Name
01
Vss
49
DQ13
03
DQ0
51
DQ14
05
DQ1
53
DQ15
07
DQ2
55
Vss
09
DQ3
57
*CB0
11
Vcc
59
*CB1
13
DQ4
61
CLK0
15
DQ5
63
Vcc
17
DQ6
65
/RAS
19
DQ7
67
/WE
21
Vss
69
/CS0
23
DQM0
71
*/CS1
25
DQM1
73
NC
27
Vcc
75
Vss
29
A0
77
*CB2
31
A1
79
*CB3
33
A2
81
Vcc
35
Vss
83
DQ16
37
DQ8
85
DQ17
39
DQ9
87
DQ18
41
DQ10
89
DQ19
43
DQ11
91
Vss
45
Vcc
93
DQ20
47
DQ12
95
DQ21
* Please refer Block Diagram
Transcend information Inc
Pin
No
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Pin
Name
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
DQM2
DQM3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
Pin
No
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQM4
DQM5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
3
Pin
No
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Pin
Name
DQ45
DQ46
DQ47
Vss
*CB4
*CB5
CKE0
Vcc
/CAS
*CKE1
*A12
*A13
*CLK1
Vss
*CB6
*CB7
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
Pin
No
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Pin
Name
DQ54
DQ55
Vcc
A7
BA0
Vss
*BA1
*A11
Vcc
DQM6
DQM7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
Block Diagram
CLK
DQM4
CLK
DQM5
A0~A11,BA0~1
A0~A11,BA0~1
DQ0~7
DQ0~7
/RAS
/RAS
/RAS
/RAS
/CAS
/WE
16Mx8
SDRAM
A0~A11,BA0~1
/CAS
16Mx8
/WE
SDRAM
/CAS
16Mx8
/WE
SDRAM
/CS
/CS
/CS
CKE
CKE
CKE
CKE
DQM
/CS
CLK
DQM2
CLK
DQM3
CLK
DQM6
CLK
DQM7
A0~A11,BA0~1
A0~A11,BA0~1
DQ0~7
DQ0~7
DQ0~7
DQ0~7
/RAS
/RAS
/RAS
/WE
/CS
/CAS
/WE
16Mx8
SDRAM
DQM
CKE
CKE
CLK
DQM1
DQM0
A0~A11,BA0~1
/WE
CKE
CLK
DQM4
A0~A11,BA0~1
/CAS
/WE
CKE
CLK
DQM5
A0~A11,BA0~1
A0~A11,BA0~1
DQ0~7
DQ0~7
DQ0~7
DQ0~7
/RAS
/RAS
/RAS
/RAS
/CAS
/WE
16Mx8
SDRAM
/CS
CLK
DQM2
SDA
16Mx8
SDRAM
/CS
DQM
CKE
/CAS
/WE
CKE
CLK
16Mx8
/CAS
SDRAM
/WE
/CS
DQM3
/CAS
/WE
16Mx8
SDRAM
/CS
CKE
CLK
DQM6
SDA SCL
A0
A1
A2
24C02
16Mx8
SDRAM
/CS
/CS
/CS
CLK
/RAS
16Mx8
SDRAM
/CAS
DQM
16Mx8
SDRAM
/CAS
A0~A11,BA0~1
CKE
CLK
DQM
A0~A11,BA0~1
CLK1
CLK
DQ0~7
16Mx8
SDRAM
16Mx8
SDRAM
CKE
A0~A11,BA0~1
/CAS
CKE1
CKE
DQ0~7
/WE
/CS1
/CS
CLK
/CAS
/WE
/CS
/CS
CKE
DQM1
DQM0
/WE
DQM
CKE
16Mx8
SDRAM
/CAS
DQM
/CS
/WE
16Mx8
SDRAM
DQM
/WE
/CAS
/RAS
/RAS
/RAS
16Mx8
SDRAM
/CAS
DQM
CLK0
/RAS
DQM
CKE0
DQ0~7
DQM
/CS0
A0~A11,BA0~1
DQ0~7
DQM
/WE
A0~A11,BA0~1
DQ0~7
DQM
/CAS
A0~A11,BA0~1
DQM
/RAS
A0~A11,BA0~1
DQ0~7
DQM
DQ0~DQ63
DQM
A0~A11
BA0~BA1
DQM7
SCL
This technical information is based on industry standard data and tests believed to be reliable. However , Transcend makes no warranties,
either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the
right to make changes in specifications at any time without prior notice
Transcend information Inc
4
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Mean time between failure
Temperature Humidity Burning
Temperature Cycling Test
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
Value
-1.0~4.6
-1.0~4.6
-55~+150
16
50
50
85°C/85%, Static Stress
0°C ~ 125°C Cycling
IOS
MTBF
THB
TC
Unit
V
V
°C
W
mA
year
°C-%
°C
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70 °C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
Input low voltage
VIL
-0.3
0
0.8
V
Output high voltage
VOH
2.4
V
Output low voltage
VOL
0.4
V
Input leakage current
ILI
-10
10
uA
Note
1
2
IOH = -2mA
IOL = 2mA
3
Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is < 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is < 3ns.
3. Any input 0V ≤ Vin ≤ VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-state output.
CAPACITANCE (VDD = 3.3V, TA = 23℃, f = 1MHz, VREF = 1.4V ± 200mV)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A11, BA0~BA1)
CIN1
60
90
pF
Input capacitance (/RAS, /CAS, /WE)
CIN2
60
90
pF
Input capacitance (CKE0,CKE1)
CIN3
35
55
pF
Input capacitance (CLK0~CLK1)
CIN4
25
35
pF
Input capacitance (/CS0,/CS1)
CIN5
25
35
pF
Input capacitance (DQM0~DQM7)
CIN6
15
25
pF
Data input/output capacitance (DQ0~DQ63)
COUT
10
25
pF
Transcend information Inc
5
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Operating Current
Burst Length =1
ICC1
(One Bank Active)
tRC≥tRC(min)
IOL=0mA
ICC2P
CKE≤VIL(max), tCC=15ns
Precharge Standby Current
ICC2PS CKE & CLK≤VIL(max), tCC=∞
in power-down mode
ICC2N
CKE≥VIH(min), /CS≥VIH(min), tCC=15ns
Value
Unit
Note
1,120
mA
1
16
240
mA
Input signals are changed one time during 30ns
Precharge Standby Current
in non power-down mode
ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
mA
16
112
Input signals are stable
Active Standby Current
in power-down mode
ICC3P
CKE≤VIL(max), tCC=10ns
80
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
80
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
480
ICC3N
Active Standby Current
in non power-down mode
(One Bank Active)
Input signals are changed one time during 30ns
ICC3NS
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
mA
mA
320
Input signals are stable
IOL= 0 mA
Page Burst
tccD = 2CLKs
1,240
Icc5
tRC ≥ tRC(min)
3,200
ICC6
CKE≤0.2V
Operating Current
(Burst Mode)
ICC4
Refresh current
Self Refresh Current
24
mA
1
mA
2
mA
Note: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading cap.
Transcend information Inc
6
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf=1/1
1.4
See Fig. 2
Unit
V
V
ns
V
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Row active time
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
Value
Unit
Note
20
20
20
50
100
ns
ns
ns
ns
us
1
1
1
1
@Operation
tRC(min)
70
ns
Row cycle time
Last data in to new col. address delay
tCDL(min)
1
CLK
Last data in to row precharge
tRDL(min)
1
CLK
Last data in to burst stop
tBDL(min)
1
CLK
Col. address to col. address delay
tCCD(min)
1
CLK
Number of valid output data
1
ea
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc
7
1
2
2
2
3
4
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
Value
Min
Max
CLK cycle time
tCC
10
Unit
Note
1000
ns
1
6
ns
1, 2
CLK to valid output delay
tSAC
Output data hold time
tOH
3
ns
CLK high pulse width
tCH
3
ns
2
3
CLK low pulse width
tCL
3
ns
3
Input setup time
tSS
2
ns
3
Input hold time
tSH
1
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output in Hi-Z
tSHZ
6
Note: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc
8
ns
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Refresh
Auto Refresh
Entry
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Clock Suspend or
Active Power Down
CKEn-1 CKEn
/CAS
/WE
DQM
BA0,1
A10/AP
A11, A0~A9
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
H
X
L
H
H
L
X
H
X
Entry
H
L
Entry
/RAS
H
Bank Selection
Both Banks
Exit
/CS
L
H
H
L
Precharge Power
Down Mode
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
V
1,2
3
3
3
3
Row Address
L
Column
Address
(A0~A9)
H
L
Column
Address
(A0~A9)
H
X
V
X
Note
L
H
4
4, 5
4
4, 5
6
X
X
X
X
X
X
Exit
DQM
No Operation Command
L
H
X
H
H
X
H
X
X
X
L
H
H
H
X
V
X
X
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note:
1. OP Code : Operand Code
A0~A12, BA0~BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatic precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc
9
7
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
Serial Presence Detect Specification
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
Serial Presence Detect
Function Described
Standard Specification
# of Bytes Written into Serial Memory
128bytes
Total # of Bytes of S.P.D Memory
256bytes
Fundamental Memory Type
SDRAM
# of Row Addresses on this Assembly
A0~A11
# of Column Addresses on this Assembly
A0~A9
# of Module Banks on this Assembly
2 banks
Data Width of this Assembly
64bits
Data Width Continuation
0
Voltage Interface Standard of this Assembly
LVTTL3.3V
SDRAM Cycle Time (highest CAS latency)
10ns
SDRAM Access from Clock (highest CL)
6ns
DIMM configuration type (non-parity, ECC)
DIMM
Refresh Rate Type
15.625us/Self Refresh
Primary SDRAM Width
X8
Error Checking SDRAM Width
0
Min Clock Delay Back to Back Random Address
1 clock
Burst Lengths Supported
1,2,4,8 & Full page
Number of banks on each SDRAM device
4 bank
CAS # Latency
2&3
CS # Latency
0 clock
Write Latency
0 clock
SDRAM Module Attributes
Non Buffer
SDRAM Device Attributes : General
Prec All, Auto Prec, R/W Burst
SDRAM Cycle Time (2nd highest CL)
10ns
SDRAM Access from Clock (2nd highest CL)
6ns
SDRAM Cycle Time (3rd highest CL)
SDRAM Access from Clock (3rd highest CL)
Minimum Row Precharge Time
20ns
Minimum Row Active to Row Activate
20ns
Minimum RAS to CAS Delay
20ns
Minimum RAS Pulse Width
50ns
Density of Each Bank on Module
128MB
Command/Address Setup Time
2ns
Command/Address Hold Time
1ns
Data Signal Setup Time
2ns
Data Signal Hold Time
1ns
Superset Information
SPD Data Revision Code
Intel SPD SPEC V1.2
Checksum for Bytes 0-62
17
Manufacturers JEDEC ID Code per JEP-108E
Transcend
Manufacturing Location
T
73-90
Manufacturers Part Number
91-92
93-94
95-98
Revision Code
Manufacturing Date
Assembly Serial Number
Transcend information Inc
10
Vendor Part
80
08
04
0C
0A
02
40
00
01
A0
60
00
80
08
00
01
8F
04
06
01
01
00
0E
A0
60
00
00
14
14
14
32
20
20
10
20
10
00
12
17
7F, 4F
54
TS32MSS64V8L2
54 53 33 32 4D 53
53 36 34 56 38 4C
32 20 20 20 20 20
0
By Manufacturer
By Manufacturer
0
Variable
Variable
144PIN PC100 Unbuffered SO-DIMM
256MB With 16M X 8 CL2
TS32MSS64V8L2
99-125
126
127
128~255
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend information Inc
11
100MHz
CL=2&3 Clock=0,1
Open
0
64
C6
FF