Download Transcend 256MB SDRAM 144Pin Micro-DIMM PC133 Unbuffer Non-ECC Memory

144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
Description
Placement
The TS32MMS64V6F is a 32M x 64bits Synchronous
Dynamic
RAM
high-density
for
PC-133.
The
TS32MMS64V6F consists of 8pcs CMOS 32Mx8 bits
C
Synchronous DRAMs in SOC packages and a 2048 bits
serial EEPROM on a 144-pin printed circuit board. The
B A
TS32MMS64V6F is a Dual In-Line Memory Module and
is intended for mounting into 144-pin edge connector
D
sockets.
Synchronous design allows precise cycle control with
H
the use of system clock. I/O transactions are possible
G
on every clock cycle. Range of operation frequencies,
F
programmable latencies allow the same device to be
E
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• Performance Range: PC-133
PCB: 09-1900
• Conformed to JEDEC Standard Spec.
• Burst Mode Operation.
• Auto and Self Refresh.
• CKE Power Down Mode.
• DQM Byte Masking (Read/Write)
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
Transcend information Inc.
1
I
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
Dimensions
Pin Identification
Side
Millimeters
Inches
A
38.00 ± 0.20
1.496 ± 0.008
B
35.50
1.398
C
0.875
0.034
D
1.00
0.039
E
30.00 ± 0.20
1.181 ± 0.008
F
17.00
G
Symbol
Function
A0~A12, BA0, BA1 Address input
DQ0~DQ63
Data Input / Output.
CLK0, CLK2
Clock Input.
0.669
CKE0
Clock Enable Input.
13.00
0.512
/CS0, /CS2
Chip Select Input.
H
5.00
0.197
I
0.80 ± 0.08
0.031 ± 0.003
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data (DQ) Mask
SA0~SA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Volt Power Supply
Vss
Ground
NC
No Connection
(Refer Placement)
Transcend information Inc.
2
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
Pinouts:
Pin
No
01
03
05
07
09
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
Pin
Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQM0
DQM1
Vcc
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ12
Pin
No
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
Pin
Name
DQ13
DQ14
DQ15
Vss
*CB0
*CB1
CLK0
Vcc
/RAS
/WE
/CS0
*/CS1
NC
Vss
*CB2
*CB3
Vcc
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
Pin
No
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Pin
Name
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
DQM2
DQM3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
Pin
No
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
*Please refer Block Diagram
Transcend information Inc.
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQM4
DQM5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
Pin
No
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Pin
Name
DQ45
DQ46
DQ47
Vss
*CB4
*CB5
CKE0
Vcc
/CAS
*CKE1
*A12
*A13
*CLK1
Vss
*CB6
*CB7
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
Pin
No
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Pin
Name
DQ54
DQ55
Vcc
A7
BA0
Vss
*BA1
*A11
Vcc
DQM6
DQM7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
Block Diagram
A0~A12,
BA0,BA1
DQ0~DQ63
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/RAS
/RAS
/RAS
/RAS
/CAS
/CAS
/WE
/WE
/WE
/WE
/WE
/CS0
/CS
/CS
/CS
/CS
CKE0
CKE
32Mx8
SDRAM
32Mx8
DQM3
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
CKE
CLK
DQM2
CKE
CLK
DQM1
DQM
DQM0
CLK
CLK
/CAS SDRAM
CLK
/CAS
DQM
/CAS
32Mx8
SDRAM
DQM
32Mx8
SDRAM
DQM
10
CKE
/CAS
32Mx8
SDRAM
/RAS
/CAS
/CAS
CLK
CLK
/RAS
32Mx8
SDRAM
32Mx8
SDRAM
/RAS
/WE
/CS
/CS
/CS
/CS
CKE
DQM4
CKE
DQM5
SCL
DQM6
Serial EEPROM
SCL SDA
A0
A1
DQM
/WE
DQM
/WE
DQM
/WE
CKE
32Mx8
/CAS SDRAM
CKE
DQM
/RAS
CLK
/CS2
CLK0
CLK2
DQM7
SDA
A2
SA0 SA1 SA2
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties,
either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the
right to make changes in specifications at any time without prior notice.
Transcend information Inc.
4
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Symbol
VIN, VOUT
Value
-1.0~4.6
Unit
V
Voltage on VDD supply to Vss
VDD, VDDQ
-1.0~4.6
V
TSTG
-55~+150
°C
Power dissipation
PD
8
W
Short circuit current
IOS
50
mA
MTBF
50
Year
THB
85°C/85%,Static Stress
°C-%
Storage temperature
Mean time between failure
Temperature Humidity Burning
Temperature Cycling Test
TC
0°C ~ 125°C Cycling
°C
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, T A = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
V
IOH=-2mA
Output low voltage
VOL
0.4
V
IOL=2mA
Input leakage current
ILI
-10
10
uA
3
Note:
1. VIH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD=3.3V,TA = 23°C, f = 1MHz,VREF=1.4V+ 200mV)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A12, BA0~ BA1)
CIN1
30
40
pF
Input capacitance (/RAS, /CAS, /WE)
CIN2
30
40
pF
Input capacitance (CKE0)
CIN3
30
40
pF
Input capacitance (CLK0, CLK2)
CIN4
25
30
pF
Input capacitance (/CS0, /CS2)
CIN5
16
25
pF
Input capacitance (DQM0~DQM7)
CIN6
8
10
pF
COUT1
6
8
pF
Data input/output capacitance (DQ0~DQ63)
Transcend information Inc.
5
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
CAS Latency
Operating Current
(One Bank Active)
ICC1
Precharge Standby Current ICC2P
in power-down mode
ICC2PS
ICC2N
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC2NS
Value (Typ)
Unit
Note
Burst Length =1
tRC≥tRC(min)
IOL=0mA
720
mA
1
CKE≤VIL(max), tCC=10ns
16
CKE & CLK≤VIL(max), tCC=∞
16
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
160
Input signals are changed one time during 30ns
mA
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
80
Input signals are stable
ICC3P
CKE≤VIL(max), tCC=10ns
48
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
48
ICC3N
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
mA
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
200
Input signals are stable
Operating Current
(Bust Mode)
ICC4
IOL= 0 mA
Page Burst
tccD = 2CLKs
Refresh Current
ICC5
tRC≥tRC(min)
Self Refresh Current
ICC6
CKE≤0.2V
Note:
3
mA
1
1600
mA
2
24
L
12
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL=VDDQ/VSSQ)
6
880
C
1. Measured with outputs open.
Transcend information Inc.
mA
240
Input signals are changed one time during 30ns
ICC3NS
mA
mA
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
Value
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, I OH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Symbol
Value
Unit
Note
Row active to row active delay
tRRD(min)
15
ns
1
/RAS to /CAS delay
tRCD(min)
20
ns
1
Row precharge time
tRP(min)
20
ns
1
tRAS(min)
45
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
65
ns
1
Last data in to new col. Address delay
tCDL(min)
1
CLK
2
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to Active delay
tDAL
2CLK+tRP
-
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
1
ea
4
Row active time
Number of valid output data
Note:
CAS latency=2
1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc.
7
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
Min
Max
Unit
Note
7.5
1000
ns
1
5.4
ns
1, 2
CLK cycle time
CAS latency=2
tCC
CLK to valid
output delay
CAS latency=2
tSAC
Output data
hold time
CAS latency=2
tOH
2.7
ns
2
CLK high pulse width
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output
in Hi-Z
Note:
CAS latency=2
5.4
tSHZ
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc.
8
ns
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn
Register
Mode Register Set
Refresh
Auto Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
Read &
Column
Address
Write &
Column
Address
Burst Stop
Precharge
/RAS
/CAS
/WE
DQM
BA0,1
Auto Precharge Enable
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Entry
Exit
Precharge Power
Down Mode
H
X
L
H
L
L
X
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
H
H
L
Entry
V
1,2
3
3
3
3
Row Address
L
Column
Address
(A0~A9)
H
L
Column
Address
(A0~A9)
H
X
V
X
L
L
H
4
4, 5
4
4, 5
6
X
X
X
X
X
H
X
H
H
X
X
H
L
X
H
X
H
X
H
V
X
X
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
1. OP Code: Operand Code
A0~A12, BA0~BA1: Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc.
Note
X
Exit
DQM
No Operation Command
A10/AP A11, A12, A0~A9
H
Auto Precharge Disable
Clock Suspend or
Active Power Down
Note:
/CS
9
7
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function Described
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
Standard Specification
128bytes
256bytes
SDRAM
13
10
1 bank
64bits
0
LVTTL3.3V
7.5ns
5.4ns
None
7.8us/Self Refresh
X8
64bit
1 clock
1,2,4,8 & Full page
4 bank
2,3
0 clock
0 clock
Non Buffer
Prec All, Auto Prec,
R/W Burst
10ns
6ns
20ns
16ns
20ns
45ns
256MB
1.5ns
0.8ns
1.5ns
0.8ns
JEDEC2
C2
Transcend
T
SDRAM Device Attributes: General
nd
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
SDRAM Cycle Time (2 highest CL)
nd
SDRAM Access from Clock (2 highest CL)
rd
SDRAM Cycle Time (3 highest CL)
rd
SDRAM Access from Clock (3 highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID Code per JEP-108E
Manufacturing Location
73-90
Manufacturers Part Number
Transcend information Inc.
TS32MMS64V6F
10
Vendor Part
80
08
04
0D
0A
01
40
00
01
75
54
00
82
08
00
01
8F
04
06
01
01
00
0E
54
53
20
53
36
20
A0
60
00
00
14
0F
14
2D
40
15
08
15
08
00
02
C2
7F, 4F
54
33 32 4D 4D
34 56 36 46
20 20 20 20
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
TS32MMS64V6F
91-92
93-94
95-98
99-125
126
127
128~
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend information Inc.
11
By Manufactory
By Manufactory
CL=2,3 Clock 0~3
Open
0
Variable
Variable
0
64
F6
FF