Download Transcend 256MB SDRAM PC133 Unbuffer Non-ECC Memory
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168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D Placement Description The TS32MLS64V6D is a 32M bit x 64 Synchronous Dynamic RAM high-density for PC-133. The TS32MLS64V6D consists of 16pcs CMOS 16Mx8 bits Synchronous DRAMs in TSOP-II 400mil packages and a 2048 bits serial EEPROM on a 168-pin printed circuit board. The TS32MLS64V6D is a Dual In-Line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operation frequencies, A programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Features B D • RoHs Compliant Product • Performance Range: PC-133. E • Conformed to JEDEC Standard Spec. C • Burst Mode Operation. • Auto and Self Refresh. I E • CKE Power Down Mode. H • DQM Byte Masking (Read/Write) • Serial Presence Detect (SPD) with serial EEPROM G F • LVTTL compatible inputs and outputs. • Single 3.3V ± 0.3V power supply. • MRS cycle with address key programs. Latency (Access from column address) PCB: 09-7149 Burst Length (1,2,4,8 & Full Page) Data Sequence (Sequential & Interleave) • All inputs are sampled at the positive going edge of system clock. Transcend Information Inc. 1 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D Dimensions Side Pin Identification Millimeters Inches A 133.35±0.40 5.250±0.016 B 65.67000 2.585000 C 23.49000 0.925000 D 8.89000 0.350000 E 3.00000 0.118000 F 29.21±0.200 G Symbol Function A0~A11, BA0, BA1 Address input DQ0~DQ63 Data Input / Output. CLK0~CLK3 Clock Input. 1.150±0.00800 CKE0, CKE1 Clock Enable Input. 19.8000 0.788000 /CS0~/CS3 Chip Select Input. H 15.80 0.622 I 1.27±0.10 0.050±0.004 /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DQM0~DQM7 Data (DQ) Mask SA0~SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add/Data input/output Vcc +3.3 Voltage Power Supply Vss Ground NC No Connection (Refer Placement) Transcend Information Inc. 2 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D Pinouts: Pin No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 *CB0 *CB1 Vss NC NC Vcc /WE DQM0 DQM1 /CS0 NC Vss A0 A2 A4 A6 A8 A10/AP BA1 Vcc Vcc CLK0 Pin No 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin Name Vss NC /CS2 DQM2 DQM3 NC Vcc NC NC *CB2 *CB3 Vss DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC *Vref *CKE1 Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss *CLK2 NC NC SDA SCL Vcc Pin No 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 *Please refer Block Diagram Transcend Information Inc. 3 Pin Name Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 *CB4 *CB5 Vss NC NC Vcc /CAS DQM4 DQM5 */CS1 /RAS Vss A1 A3 A5 A7 A9 BA0 A11 Vcc *CLK1 *A12 Pin No 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin Name Vss CKE0 */CS3 DQM6 DQM7 *A13 Vcc NC NC *CB6 *CB7 Vss DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC *Vref *REGE Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss *CLK3 NC SA0 SA1 SA2 Vcc 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D Block Diagram CKE1 /CS1 /CS0 CKE0 DQM0 DQM4 DQM DQ3 DQ1 DQ2 DQ0 DQ7 DQ5 DQ6 DQ4 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 /CS CKE DQM I/O I/O I/O I/O I/O I/O I/O I/O U1 0 1 2 3 4 5 6 7 DQM /CS CKE DQ35 DQ34 DQ33 DQ32 DQ39 DQ38 DQ37 DQ36 U9 DQM1 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 /CS CKE DQM I/O I/O I/O I/O I/O I/O I/O I/O U2 0 1 2 3 4 5 6 7 DQM /CS CKE DQ42 DQ41 DQ43 DQ40 DQ44 DQ46 DQ47 DQ45 U10 DQM2 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 /CS CKE DQM I/O I/O I/O I/O I/O I/O I/O I/O U3 0 1 2 3 4 5 6 7 /CS CKE I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 I/O I/O I/O I/O I/O I/O I/O I/O U5 /CS CKE 0 1 2 3 4 5 6 7 DQM I/O I/O I/O I/O I/O I/O I/O I/O U6 DQM DQ51 DQ50 DQ49 DQ48 DQ53 DQ54 DQ55 DQ52 U11 DQM3 /CS CKE U13 0 1 2 3 4 5 6 7 /CS CKE U14 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 /CS CKE DQM I/O I/O I/O I/O I/O I/O I/O I/O U7 0 1 2 3 4 5 6 7 /CS CKE U15 DQM7 DQM DQ24 DQ25 DQ26 DQ27 DQ30 DQ31 DQ29 DQ28 DQM /CS CKE DQM6 DQM DQ19 DQ18 DQ17 DQ16 DQ23 DQ22 DQ21 DQ20 0 1 2 3 4 5 6 7 DQM5 DQM DQ8 DQ9 DQ10 DQ11 DQ15 DQ14 DQ13 DQ12 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 /CS CKE DQM I/O I/O I/O I/O I/O I/O I/O I/O U4 BA0 U1~U16 BA1 U1~U16 -RAS U1~U16 -CAS U1~U16 -WE CLK0 U1~U16 U1,U2,U5,U6 0 1 2 3 4 5 6 7 /CS CKE DQM DQ58 DQ59 DQ57 DQ56 DQ60 DQ61 DQ62 DQ63 U12 VDD I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 DQM /CS CKE I/O I/O I/O I/O I/O I/O I/O I/O U8 0 1 2 3 4 5 6 7 /CS CKE U16 U1~U16 EEPROM VSS SCL CLK2 WP SDA U3,U4,U7,U8 SA0 SA1 SA2 CLK1 U9,U10,U13,U14 CLK3 U11,U12,U15,U16 Note: 1.U1~U16 are 16Mx8 SDRAM. 2.DQ-to-I/O wiring may be changed per nibble. 3.Unless otherwise noted , resister values are 10 Ohms±5% This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. Transcend Information Inc. 4 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0~4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0~4.6 V TSTG -55~+150 °C Power dissipation PD 16 W Short circuit current IOS 50 mA Operating temperature TA 0~70 °C Storage temperature Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Supply voltage VDD 3.0 3.3 3.6 V Input high voltage VIH 2.0 3.0 VDDQ+0.3 V Input low voltage VIL -0.3 0 0.8 V Output high voltage VOH 2.4 V Output low voltage VOL 0.4 V Input leakage current ILI -10 10 uA Note 1 2 IOH=-2mA IOL=2mA 3 Note: 1. VIH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200mV) Parameter Symbol Min Max Unit CADD 45 85 pF CIN 45 85 pF CKE (CKE0 ~ CKE1) CCKE 25 45 pF Clock (CLK0 ~ CLK3) CCLK 15 21 pF /CS (/CS0 ~ /CS3) CC5 15 25 pF DQM (DQM0 ~ DQM7) CDQM 10 15 pF DQ (DQ0 ~ DQ63) COUT 13 18 pF Address (A0 ~A11, BA0 ~BA1) /RAS, /CAS, /WE Transcend Information Inc. 5 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating Current (One Bank Active) Symbol ICC1 Precharge Standby Current ICC2P in power-down mode ICC2PS Precharge Standby Current ICC2N in non power-down mode Test Condition Value Unit Note Burst Length =1 tRC≥tRC(min) IO=0mA CKE≤VIL(max), tCC=10ns 960 mA 1 32 mA CKE & CLK≤VIL(max), tCC=∞ 32 CKE≥VIH(min), /CS≥VIH(min), tCC=10ns 320 mA Input signals are changed one time during 20ns 160 ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞ Input signals are stable Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) ICC3P CKE≤VIL(max), tCC=10ns 80 ICC3PS CKE & CLK≤VIL(max), tCC=∞ 80 ICC3N CKE≥VIH(min), /CS≥VIH(min), tCC=10s 480 mA mA Input signals are changed one time during 20ns ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞ 400 Input signals are stable Operating Current (Bust Mode) ICC4 Refresh Current ICC5 Self Refresh Current ICC6 IOL= 0 mA Page Burst 4 Banks activated tccD = 2CLKs tRC≥tRC(min) CKE≤0.2V Note: 6 mA 1 1840 mA 2 C 32 L 12.8 1. Measured with outputs open. 2. Refresh period is 64ms 3. Unless otherwise noted, input swing level is CMOS (VIH/VIL=VDDQ/VSSQ) Transcend Information Inc. 1120 mA 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C) Parameter AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf=1/1 ns 1.4 V See Fig. 2 Vtt=1.4V 3.3V 50 Ohm 1200 Ohm Output VOH (DC)=2.4V, IOH=-2mA VOL (DC)=0.4V, I OL=2mA Output Z0=50 Ohm 50pF 50pF 870 Ohm (Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Value Unit Note Row active to row active delay tRRD(min) 15 ns 1 /RAS to /CAS delay tRCD(min) 20 ns 1 Row precharge time tRP(min) 20 ns 1 Row active time tRAS(min) 45 ns 1 tRAS(max) 100 us Row cycle time tRC(min) 65 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to Active precharge tDAL(min) 2 CLK + tRP - Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 2 ea 4 Number of valid output data CAS latency=3 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time, and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Transcend Information Inc. 7 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Refer to the individual component, not the whole module. Parameter Symbol Min Max Unit Note CLK cycle time tCC 7.5 1000 ns ns CLK to valid output delay tSAC 5.4 ns 1, 2 Output data hold time tOH 3.0 ns 2 CLK high pulse width tCH 2.5 ns 3 CLK low pulse width tCL 2.5 ns 3 Input setup time tSS 1.5 ns 3 Input hold time tSH 0.8 ns 3 CLK to output in Low-Z tSLZ 1 ns 2 CLK to output in Hi-Z tSHZ Note: 5.4 ns 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)= 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Transcend Information Inc. 8 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D SIMPLIFIED TRUTH TABLE /CS /RAS /CAS /WE DQM Register COMMAND Mode Register Set CKEn-1 CKEn H X L L L L X OP CODE 1,2 Refresh Auto Refresh Self Refresh H L L L H X X L H L H X H X H H X H X H H X L X Bank Active & Row Addr. L H L 3 3 3 3 X V Read & Column Address Auto Precharge Disable H X L H L H X V Write & Column Address Auto Precharge Disable Entry Exit BA0,1 Auto Precharge Enable A10/AP A11, A0~A9 Note Row Address L Column 4 H Address 4, 5 L Column 4 H Address 4, 5 (A0~A9) H X L H L L X V Auto Precharge Enable (A0~A9) Burst Stop Precharge Bank Selection Both Banks Clock Suspend or Active Power Down X X L L H L H H L L X X H L H X X X X L H L X V X V X V X X H L H X X X X L H H H H X X X L V V V H L X X H X H X H V X X L H X 6 X Entry Exit Precharge Power Down Mode H H Entry L H Exit DQM No Operation Command H H X X X V X X X 7 (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) Note: 1. OP Code: Operand Code A0~A11, BA0~BA1: Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatically precharge without row precharge command is meant by “Auto”. Auto/self refresh can be issued only at both banks precharge state. 4. BA0~BA1: Bank select address. If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected. If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected. If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Transcend Information Inc. 9 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D Serial Presence Detect Specification Serial Presence Detect Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function Described # of Bytes Written into Serial Memory Total # of Bytes of S.P.D Memory Fundamental Memory Type # of Row Addresses on this Assembly # of Column Addresses on this Assembly # of Module Rows on this Assembly Data Width of this Assembly Data Width of this Assembly Voltage Interface Standard of this Assembly SDRAM Cycle Time @CAS latency of 3 SDRAM Access Time from Clock @CAS latency of 3 DIMM configuration type (non-parity, ECC) Refresh Rate Type Primary SDRAM Width Error Checking SDRAM Width Min Clock Delay for Back to Back Random Address SDRAM Device Attributes: Burst Lengths Supported SDRAM Device Attributes: # of banks on SDRAM device SDRAM Device Attributes: CAS Latency SDRAM Device Attributes: CS Latency SDRAM Device Attributes: Write Latency 21 SDRAM Module Attributes 22 SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 73-90 SDRAM Cycle Time @CAS Latency of 2 SDRAM Access Time from Clock @CAS Latency of 2 SDRAM Cycle Time @CAS Latency of 1 SDRAM Access Time from Clock @CAS Latency of 1 Minimum Row Precharge Time (=t RP) Minimum Row Active to Row Activate (=t RRD) Minimum RAS to CAS Delay (=t RCD) Minimum Activate Precharge Time (=t RAS) Module Row Density Command and Address Signal input Setup Time Command and Address Signal input Hold Time Data Signal Setup Time Data Signal Hold Time Superset Information SPD Data Revision Code Checksum for Bytes 0-62 Manufacturers JEDEC ID Code per JEP-108E Manufacturing Location Manufacturers Part Number Standard Specification Vendor Part 128bytes 80 256bytes 08 SDRAM 04 12 0C 10 0A 2 rows 02 64bits 40 00 LVTTL3.3V 01 7.5ns 75 5.4ns 54 None 00 15.625us/Self Refresh 80 X8 08 None 00 tCCD=1CLK 01 1,2,4,8 & Full page 8F 4 bank 04 2,3 06 0 clock 01 0 clock 01 Non-buffered, non-registered 00 & redundant addressing +/- 10% voltage tolerance, Burst Read Signal bit Write 0E precharge all, auto precharge 10ns A0 6ns 60 00 00 20ns 14 15ns 0F 20ns 14 45ns 2D 2 rows of 128MB 20 1.5ns 15 0.8ns 08 1.5ns 15 0.8ns 08 00 JEDEC2 02 A0 Transcend 7F, 4F T 54 54 53 33 32 4D 4C TS32MLS64V6D 53 36 34 56 36 44 Transcend Information Inc. 10 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 TS32MLS64V6D 20 20 20 20 20 20 91-92 93-94 95-98 99-125 126 127 128~ Revision Code Manufacturing Date Assembly Serial Number Manufacturer Specific Data Intel Specification Frequency Intel Specification CAS# Latency/Clock Signal Support Unused Storage Locations Transcend Information Inc. 11 By Manufacturer By Manufacturer CL=2,3 Clock 0~3 Open 0 Variable Variable 0 64 F6 FF