Download Transcend 256MB SDRAM PC100 ECC Registered Memory

168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
Placement
Description
The TS32MLR72V8D is a 32M bit x 72 Synchronous
Dynamic RAM high-density memory registered DIMM
module. The TS32MLR72V8D consists of 18pcs of
CMOS 16Mx8bits Synchronous DRAMs in TSOP-II
400mil packages, 2pcs of drive ICs, 1pc of PLL and one
2048 bits serial EEPROM on a 168-pin printed circuit
board. The TS32MLR72V8D is a Dual In-Line Memory
Module and is intended for mounting into 168-pin edge
A
connector sockets.
Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible
on every clock cycle. Range of operation frequencies,
B
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
C
memory system applications.
D
E
Features
F
G
• Performance Range: PC-100
PCB: 09-7395
• Burst Mode Operation.
• Auto and Self Refresh.
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
Transcend information Inc
1
H
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
Dimensions
Side
Pin Identification
Millimeters
Symbol
Inches
A
133.35±0.400
5.250±0.016
B
65.67000
2.585000
C
23.49000
0.925000
D
8.89000
0.350000
E
15.78
F
Function
SA0~SA11
Address Input
SBA0, SBA1
Select Bank Address
SD0~SD63
Data Input / Output.
0.621
SCB0~SCB7
Check bit (data-in / data-out)
19.78
0.778
SCLK0
Clock Input.
G
40.50±0.200
1.594±0.008
H
1.27±0.100
0.050±0.004
SCKE0
Clock Enable Input.
/SCS0~/SCS3
Chip Select Input.
/SRAS
Row Address Strobe
/SCAS
Column Address Strobe
/SWE
Write Enable
(Refer Placement)
SDQM0~SDQM7 Data (DQ) Mask
Transcend information Inc
2
REGE
Register Enable
EA0~EA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
NC
No Connection
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
Pinouts:
Pin
Pin
Pin
Pin
No
Name
No
Name
01
Vss
43
Vss
02
SDQ0
44
NC
03
SDQ1
45
/SCS2
04
SDQ2
46
SDQM2
05
SDQ3
47
SDQM3
06
Vcc
48
NC
07
SDQ4
49
Vcc
08
SDQ5
50
NC
09
SDQ6
51
NC
10
SDQ7
52
*SCB2
11
SDQ8
53
*SCB3
12
Vss
54
Vss
13
SDQ9
55
SDQ16
14
SDQ10
56
SDQ17
15
SDQ11
57
SDQ18
16
SDQ12
58
SDQ19
17
SDQ13
59
Vcc
18
Vcc
60
SDQ20
19
SDQ14
61
NC
20
SDQ15
62
*Vref
21
*SCB0
63
*SCKE1
22
*SCB1
64
Vss
23
Vss
65
SDQ21
24
NC
66
SDQ22
25
NC
67
SDQ23
26
Vcc
68
Vss
27
/SWE
69
SDQ24
28
SDQM0
70
SDQ25
29
SDQM1
71
SDQ26
30
/SCS0
72
SDQ27
31
NC
73
Vcc
32
Vss
74
SDQ28
33
SA0
75
SDQ29
34
SA2
76
SDQ30
35
SA4
77
SDQ31
36
SA6
78
Vss
37
SA8
79
*SCLK2
38
SA10/AP
80
NC
39
SBA1
81
NC
40
Vcc
82
SDA
41
Vcc
83
SCL
42
SCLK0
84
Vcc
* Please refer Block Diagram
Transcend information Inc
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
3
Pin
Name
Vss
SDQ32
SDQ33
SDQ34
SDQ35
Vcc
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
Vss
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
Vcc
SDQ46
SDQ47
*SCB4
*SCB5
Vss
NC
NC
Vcc
/SCAS
SDQM4
SDQM5
*/SCS1
/SRAS
Vss
SA1
SA3
SA5
SA7
SA9
SBA0
SA11
Vcc
*SCLK1
*SA12
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
SCKE0
*/SCS3
SDQM6
SDQM7
*SA13
Vcc
NC
NC
*SCB6
*SCB7
Vss
SDQ48
SDQ49
SDQ50
SDQ51
Vcc
SDQ52
NC
*Vref
*REGE
Vss
SDQ53
SDQ54
SDQ55
Vss
SDQ56
SDQ57
SDQ58
SDQ59
Vcc
SDQ60
SDQ61
SDQ62
SDQ63
Vss
*SCLK3
NC
EA0
EA1
EA2
Vcc
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
Block Diagram
/RCS0~3
/CS0
/CS0
PCK3
/CS2
PCK3
/CS2
PCK1
/CS0
PCK1
CLK
/CS
DQM
CLK
/CS
DQM
CLK
DQM5
/CS
DQM4
DQM
DQM3
CLK
DQM2
/CS
DQM1
DQM
DQM0
CLK
RDQM0~7
/CS
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
DQM
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
CLK
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
/CS
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
DQM
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
/CS0
PCK2
SCB0~SCB7
PCK3
/CS2
/CS2
PCK2
/CS1
PCK1
/CS1
PCK6
/CS3
PCK6
CLK
/CS
DQM
CLK
DQM1
/CS
DQM2
DQM
DQM1
CLK
DQM0
/CS
DQM7
DQM
DQM6
PCK0
CLK
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
/CS
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
DQM
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
CLK
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
/CS
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
DQM
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
CLK
REGE
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
/CS
/SCS0~/SCS3
REGISTER
SDQM0~SDQM7
RA0~RA11,RBA0,RBA1
/RRAS
/RCAS
/RWE
RCKE0
DQM
SD0~SD63
SA0~SA11,SBA0,SBA1
/SRAS
/SCAS
/SWE
SCKE0
/CS0
PCK5
PCK2
SCB0~SCB7
/CS3
/CS1
PCK4
SCLK0
/CS1
PCK6
PLL
/CS3
PCK5
PCK0
PCK1
PCK2
PCK3
PCK4
PCK5
PCK6
PCK4
/CS3
PCK4
CLK
/CS
DQM
CLK
/CS
DQM
CLK
DQM5
/CS
DQM7
DQM
DQM6
CLK
DQM5
/CS
DQM4
DQM
DQM3
CLK
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
/CS
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
DQM
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
CLK
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
/CS
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
DQM
DQ0~DQ7
A0~A11,BA0,BA1
/RAS
16Mx8
/CAS
SDRAM
/WE
CKE
/CS1
PCK5
EEPROM
SCL
SCL
A0
SDA
A1
SDA
A2
EA0 EA1 EA2
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make
changes in specifications at any time without prior notice.
Transcend information Inc
4
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply to Vss
Storage temperature
Power dissipation
Short circuit current
Mean time between failure
Temperature Humidity Burning
Temperature Cycling Test
Note:
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
MTBF
THB
TC
Value
-1.0~4.6
-1.0~4.6
-55~+150
18
50
50
85°C/85%,
0°C ~ 125°C
Unit
V
V
°C
W
mA
year
°C-%
°C
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
V
IOH=-2mA
Output low voltage
VOL
0.4
V
IOL=2mA
Input leakage current (Inputs)
IIL
-2
2
uA
3
Input leakage current (I/O pins)
IOL
-3
3
uA
3,4
Note: 1. VIH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V±200mV)
Parameter
Input capacitance (SA0~SA11, SBA0~ SBA1)
Input capacitance (/SRAS, /SCAS, /SWE)
Input capacitance (SCKE0)
Input capacitance (SCLK0)
Input capacitance (/SCS0~/SCS3)
Input capacitance (SDQM0~SDQM7)
Data input/output capacitance (SD0~SD63)
Data input/output capacitance (SCB0~SCB7)
Transcend information Inc
Symbol
Min
Max
Unit
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
COUT1
-
19
19
33
12
12
12
19
19
pF
pF
pF
pF
pF
pF
pF
pF
5
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating Current
(One Bank Active)
Symbol
ICC1
Precharge Standby Current ICC2P
in power-down mode
ICC2PS
Precharge Standby Current ICC2N
in non power-down mode
Test Condition
CAS Latency
Burst Length =1
tRC≥tRC(min)
IOL=0mA
CKE≤VIL(max), tCC=15ns
Value
Unit
Note
1,550
mA
1
386
mA
3
CKE & CLK≤VIL(max), tCC=∞
38
CKE≥VIH(min), /CS≥VIH(min), tCC=15ns
710
mA
3
Input signals are changed one time during 30ns
ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
182
Input signals are stable
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3P
CKE≤VIL(max), tCC=15ns
440
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
92
ICC3N
CKE≥VIH(min), /CS≥VIH(min), tCC=15ns
890
mA
3
mA
Input signals are changed one time during 30ns
ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
3
452
Input signals are stable
Operating Current
(Bust Mode)
ICC4
Refresh Current
ICC5
IOL= 0 mA
Page Burst
tccD = 2CLKs
tRC≥tRC(min)
3
1670
2
2,480
mA
1
mA
2
Self Refresh Current
ICC6
CKE≤0.2V
386
mA
3
1. Module IDD was calculated on the basis of component IDD and can be differently measured according
Note:
to DQ loading capacitor.
Transcend information Inc
6
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
/RAS to /CAS delay
Row precharge time
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
Row active time
Row cycle time
Last data in to new col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Number of valid
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
CAS latency=3
Value
Unit
Note
20
20
20
50
100
70
ns
ns
ns
ns
us
ns
1
1
1
1
1
1
1
1
2
CLK
CLK
CLK
CLK
2
2
2
3
ea
4
CAS latency=2
output data
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write in Reg. DIMM (1CLK earlier than unbuffered DIMM)
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc
7
1
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
Value
Min
CLK cycle time
CAS latency=3
CAS latency=2
CLK to valid
output delay
CAS latency=3
Output data
hold time
CAS latency=3
10
tCC
Unit
Note
ns
1
ns
1, 2
ns
1, 2
Max
1000
-
tSAC
CAS latency=2
tOH
CAS latency=2
-
6
-
-
3
-
-
-
CLK high pulse width
tCH
3
-
ns
3
CLK low pulse width
tCL
3
-
ns
3
Input setup time
tSS
2
-
ns
3
Input hold time
tSH
1
-
ns
3
CLK to output in Low-Z
tSLZ
1
-
ns
2
-
6
ns
1
-
-
CLK to output
in Hi-Z
Note:
CAS latency=3
tSHZ
CAS latency=2
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc
8
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Refresh
Auto Refresh
Entry
Self
Refresh Exit
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Clock Suspend or
Active Power Down
H
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
H
X
L
H
H
L
X
X
V
X
H
X
Entry
H
L
Entry
L
H
H
L
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
SA0~SA9,
SA11
Note
1,2
3
3
3
3
Row Address
L
H
L
H
Column
Address
(SA0~SA9)
Column
Address
(SA0~SA9)
4
4, 5
4
4, 5
6
L
H
X
X
X
X
X
X
Exit
SDQM
No Operation Command
Note:
SCKEn /SCS /SRAS /SCAS /SWE SDQM SBA0,1 SA10/AP
Bank Selection
Both Banks
Exit
Precharge Power
Down Mode
SCKEn-1
L
H
H
X
H
X
X
H
X
X
X
L
H
H
H
V
X
X
X
7
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
1. OP Code : Operand Code
SA0~SA11, SBA0~SBA1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. SBA0~SBA1: Bank select address.
If both SBA0 and SBA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both SBA0 is “Low” and SBA1 is “High” at read, write, row active and precharge, bank B is selected.
If both SBA0 is “High” and SBA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both SBA0 and SBA1 are “High” at read, write, row active and precharge, bank D is selected.
If SA10/AP is “High” at row precharge, SBA0 and SBA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. SDQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write SDQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read SDQM latency is 2)
Transcend information Inc
9
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
Function Described
Standard Specification
Vendor Part
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Number of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
Number of Row Addresses on this Assembly
Number of Column Addresses on this Assembly
Number of Module Rows on this Assembly
Data Width of this Assembly
Data Width of this Assembly
Voltage Interface Standard of this Assembly
SDRAM Cycle Time @CAS latency of 3
SDRAM Access Time from Clock @CAS latency of 3
DIMM configuration type
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay for Back to Back Random Address
SDRAM Device Attributes : Burst Lengths Supported
SDRAM Device Attributes : # of banks on SDRAM device
SDRAM Device Attributes : CAS Latency
SDRAM Device Attributes : CS Latency
SDRAM Device Attributes : Write Latency
128bytes
256bytes
SDRAM
12
10
2 rows
72bits
LVTTL
10ns
6ns
ECC
15.625us/Self Refresh
X4
X4
tCCD=1CLK
1,2,4,8 & Full page
4 bank
3
0 clock
0 clock
80
08
04
0C
0A
02
48
00
01
A0
60
02
80
04
04
01
8F
04
04
01
01
21
SDRAM Module Attributes
Non-buffered, non-registered
& redundant addressing
16
22
SDRAM Device Attributes : General
23
24
25
26
27
28
29
30
31
32
33
34
SDRAM Cycle Time @CAS Latency of 2
SDRAM Access Time from Clock @CAS Latency of 2
SDRAM Cycle Time @CAS Latency of 1
SDRAM Access Time from Clock @CAS Latency of 1
Minimum Row Precharge Time (=t RP)
Minimum Row Active to Row Activate (=t RRD)
Minimum RAS to CAS Delay (=t RCD)
Minimum Activate Precharge Time (=t RAS)
Module Row Density
Command and Address Signal input Setup Time
Command and Address Signal input Hold Time
Data Signal Setup Time
Transcend information Inc
10
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto
precharge
20ns
20ns
20ns
50ns
1 row of 128MB
2.0ns
1.0ns
2.0ns
0E
00
00
00
00
14
14
14
32
20
20
10
20
168 PIN PC100 Registered DIMM
256MB With 16M X 8 CL3
TS32MLR72V8D
35
36-61
62
63
64-71
72
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID Dode per JEP-108E
Manufacturing Location
1.0ns
Ver 1.2
Transcend
T
10
00
12
35
7F, 4F
54
54 53 33 32 4D 4C
73-90 Manufacturers Part Number
TS32MLR72V8D
52 37 32 56 38 44
20 20 20 20 20 20
91-92
93-94
95-98
99-125
126
127
128~
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend information Inc
11
By Manufacturer
By Manufacturer
100MHz
CL= 3 Clock 0
Open
0
Variable
Variable
0
64
84
FF