Download Transcend 1GB DDR266 ECC Registered Memory
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184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 Description Placement The TS128MDR72V6L5 is a Low Profile 128M x 72bits Double Data Rate SDRAM high-density for PC-266. The TS128MDR72V6L5 consists of 36pcs CMOS 64Mx4 bits Double Data Rate SDRAMs in 66 pin TSOP-II 400mil packages, 2pcs drive ICs for input control signal, 1pcs PLL, and a 2048 bits serial EEPROM on a 184-pin printed circuit board. The TS128MDR72V6L5 is a Dual In-Line Memory Module and is intended for mounting into 184-pin edge A connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, B programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. C D Features • Power supply: VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V • Max clock Freq: 133MHZ. • Burst Mode Operation. • Auto and Self Refresh. • I H G All inputs except data & DM are sampled at the F positive going edge of the system clock (ck). • • Data I/O transactions on both edge of data strobe. • Serial Presence Detect (SPD) with serial EEPROM • SSTL-2 compatible inputs and outputs. • MRS cycle with address key programs. E Edge aligned data output, center aligned data input. PCB: 09-1380 CAS Latency (Access from column address): 2.5 Burst Length (2,4,8) Data Sequence (Sequential & Interleave) Transcend Information Inc. 1 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 Dimensions Side Pin Identification Millimeters Inches Symbol Function A 133.35±0.20 5.250±0.008 SA0~SA12, SBA0, SBA1 Address input B 72.39 2.850 SDQ0~SDQ63 Data Input / Output. C 6.35 0.250000 SCB0~SCB7 Check bit D 2.20 0.0870 E 30.48±0.20 1.20±0.00800 SDQS0~SDQS8, Data strobe input/output F 19.80 0.779 G 4.00 0.157 H 12.00 0.472 I 1.27±0.10 0.050±0.004 SDM0~SDM8 CK0, /CK0 Clock Input. SCKE0, SCKE1 Clock Enable Input. /SCS0, /SCS1 Chip Select Input. /SRAS Row Address Strobe /SCAS Column Address Strobe /SWE Write Enable VDD +2.5 Voltage power supply VDDQ +2.5 Voltage Power Supply for DQS VREF Power Supply for Reference VDDSPD +2.5 Voltage Serial EEPROM Power Supply EA0~EA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add/Data input/output Transcend Information Inc. 2 VDDID VDD Identification Flag VSS Ground /RESET Reset enable NC No Connection 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 Pinouts: Pin No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin Name VREF SDQ0 VSS SDQ1 SDQS0 SDQ2 VDD SDQ3 NC /RESET VSS SDQ8 SDQ9 SDQS1 VDDQ *CK1 */CK1 VSS SDQ10 SDQ11 SCKE0 VDDQ SDQ16 SDQ17 SDQS2 VSS SA9 SDQ18 SA7 VDDQ SDQ19 SA5 SDQ24 VSS SDQ25 SDQS3 SA4 VDD SDQ26 SDQ27 SA2 VSS SA1 SCB0 SCB1 VDD Pin No 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Pin Name SDQS8 SA0 SCB2 VSS SCB3 SBA1 SDQ32 VDDQ SDQ33 SDQS4 SDQ34 VSS SBA0 SDQ35 SDQ40 VDDQ /SWE SDQ41 /SCAS VSS SDQS5 SDQ42 SDQ43 VDD */SCS2 SDQ48 SDQ49 VSS */CK2 *CK2 VDDQ SDQS6 SDQ50 SDQ51 VSS VDDID SDQ56 SDQ57 VDD SDQS7 SDQ58 SDQ59 VSS NC SDA SCL Pin No 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 * Please refer Block Diagram Transcend Information Inc. 3 Pin Name VSS SDQ4 SDQ5 VDDQ SDM0 SDQ6 SDQ7 VSS NC NC NC VDDQ SDQ12 SDQ13 SDM1 VDD SDQ14 SDQ15 SCKE1 VDDQ NC SDQ20 SA12 VSS SDQ21 SA11 SDM2 VDD SDQ22 SA8 SDQ23 VSS SA6 SDQ28 SDQ29 VDDQ SDM3 SA3 SDQ30 VSS SDQ31 SCB4 SCB5 VDDQ CK0 /CK0 Pin No 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin Name VSS SDM8 SA10 SCB6 VDDQ SCB7 VSS SDQ36 SDQ37 VDD SDM4 SDQ38 SDQ39 VSS SDQ44 /SRAS SDQ45 VDDQ /SCS0 /SCS1 SDM5 VSS SDQ46 SDQ47 NC VDDQ SDQ52 SDQ53 NC VDD SDM6 SDQ54 SDQ55 VDDQ NC SDQ60 SDQ61 VSS SDM7 SDQ62 SDQ63 VDDQ EA0 EA1 EA2 VDDSPD 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 Block Diagram /CAS /CAS /CAS /WE /WE (64Mx4)x2 DDR SDRAM /CS0,/CS1 CKE0 CKE1 /CS0,/CS1 CKE0 CKE1 SDQS0 PCK1,/PCK1 SDQS1 PCK2,/PCK2 SDQS2 PCK3,/PCK3 SDQS3 PCK4,/PCK4 DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS /CAS /CAS /CAS /CAS /WE (64Mx4)x2 DDR SDRAM /WE (64Mx4)x2 DDR SDRAM /WE (64Mx4)x2 DDR SDRAM DQS CK,/CK /CS0,/CS1 CKE0 CKE1 /WE DDR SDRAM /WE /CS0,/CS1 CKE0 CKE1 SCB0~SCB3 SDQS8 PCK5,/PCK5 (64Mx4)x2 DDR SDRAM /CS0,/CS1 CKE0 CKE1 SDQS4 PCK6,/PCK6 /CS0,/CS1 CKE0 CKE1 SDQS5 PCK7,/PCK7 /CS0,/CS1 CKE0 CKE1 SDQS6 PCK8,/PCK8 /CS0,/CS1 CKE0 CKE1 SDQS7 PCK9,/PCK9 DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS (64Mx4)x2 /CAS /CAS /CAS /CAS /CAS DQS CK,/CK (64Mx4)x2 DDR SDRAM /WE (64Mx4)x2 DDR SDRAM /WE (64Mx4)x2 DDR SDRAM /WE (64Mx4)x2 DDR SDRAM /CS0,/CS1 CKE0 CKE1 /CS0,/CS1 CKE0 CKE1 /CS0,/CS1 CKE0 CKE1 /CS0,/CS1 CKE0 CKE1 SDQS0 PCK1,/PCK1 SDQS1 PCK2,/PCK2 SDQS2 PCK3,/PCK3 SDQS3 PCK4,/PCK4 DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS /CAS /CAS /CAS /CAS PCK10,/PCK10 /CS0,/CS1 CKE0 CKE1 SDQS5 PCK7,/PCK7 PLL CK0,/CK0 /WE /CS0,/CS1 CKE0 CKE1 SDQS6 PCK8,/PCK8 PCK10,/PCK10 PCK1,/PCK1 PCK2,/PCK2 PCK3,/PCK3 PCK4,/PCK4 PCK5,/PCK5 PCK6,/PCK6 PCK7,/PCK7 PCK8,/PCK8 PCK9,/PCK9 /WE /CS0,/CS1 CKE0 CKE1 DDR SDRAM SCB0~SCB3 SDQS8 PCK5,/PCK5 (64Mx4)x2 DDR SDRAM DQS CK,/CK /CS0,/CS1 CKE0 CKE1 SDQS4 PCK6,/PCK6 (64Mx4)x2 DDR SDRAM DQS CK,/CK (64Mx4)x2 DDR SDRAM DQS CK,/CK /WE DQS CK,/CK /WE (64Mx4)x2 DDR SDRAM /WE DQ0~DQ3 DQS CK,/CK REGISTER /CS0,/CS1 CKE0 CKE1 /WE /RESET /WE (64Mx4)x2 DDR SDRAM DQ0~DQ3 DQS CK,/CK /WE (64Mx4)x2 DDR SDRAM DQS CK,/CK /RCS0,/RCS1 RCKE0,RCKE1 /CAS (64Mx4)x2 DDR SDRAM DQS CK,/CK /SCS0,/SCS1 SCKE0,/SCKE1 /CAS DQS CK,/CK /RWE DQ0~DQ3 A0~A12, BA0,BA1 (64Mx4)x2 /RAS DQS CK,/CK /SWE DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQS CK,/CK /RRAS /RCAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQS CK,/CK /SCAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQS CK,/CK /SRAS DQ0~DQ3 A0~A12, BA0,BA1 /RAS DQS CK,/CK RA0~RA12,RBA0,RBA1 DQS CK,/CK SA0~SA12,SBA0,SBA1 DQS CK,/CK SDQ0~SDQ63 /CS0,/CS1 CKE0 CKE1 SDQS7 PCK9,/PCK9 Serial EEPROM SCL SCL A0 SDA A1 SDA A2 EA0 EA1 EA2 This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. Transcend Information Inc. 4 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply to Vss VDD, VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55~+150 °C Power dissipation PD 36 W Short circuit current IOS 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85°C/85%, Static Stress °C-% Temperature Cycling Test TC 0°C ~ 125°C Cycling °C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to Vss = 0V, T A = 0 to 70°C) Parameter Symbol Min Max Unit Note Supply voltage VDD 2.3 2.7 V I/O Supply voltage VDDQ 2.3 2.7 V I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination voltage VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH (DC) VREF+0.15 VDDQ+0.3 V 4 Input logic low voltage VIL (DC) -0.3 VREF-0.15 V 4 Input Voltage Level, CK and /CK inputs VIN (DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and /CK inputs VID (DC) 0.3 VDDQ+0.6 V 3 Input crossing point voltage, CK and /CK inputs VIX (DC) 1.15 1.35 V 5 Input leakage current II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current (Normal strength driver) IOH -16.8 mA VOUT= VTT + 0.84V Output Low Current (Normal strength driver) IOL 16.8 mA VOUT= VTT – 0.84V Output High Current (Half strength driver) IOH -9 mA VOUT= VTT + 0.45V Output High Current (Half strength driver) IOL 9 mA VOUT= VTT - 0.45V Note: 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled. TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of <=3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. Transcend Information Inc. 5 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T A = 0 to 70°C) Parameter Operating current - One bank Active-Precharge; tRC=tRCmin; tCK= tCK min DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle Operating current - One bank Active-Read-Precharge; Burst=4; tRC=tRC min; CL=2.5; tCK=tCK min; VIN=VREF fro DQ,DQS and DM Percharge power-down standby current; All banks idle; Power –down mode; CKE = <VIL (max); tCK= tCK min VIN = VREF for DQ, DQS and DM Precharge Floating standby current; CS# > =VIH (min); All banks idle; CKE > = VIH (min); tCK=133Mhz for DDR266 Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM Active power - down standby current; one bank active; power-down mode; CKE<= VIL (max); tCK = tCK min; VIN = VREF for DQ, DQS and DM Active standby current; CS# >= VIH (min); CKE>=VIH (min); One bank active; active - precharge; tRC=tRASmax; tCK = tCK min; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle Operating current - burst read; Burst length = 2; reads; continuous burst; One bank active; address and control inputs changing once per clock cycle; CL=2.5 at tCK = tCK min; 50% of data changing at every burst; lout = 0 mA Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=2.5 at tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst Auto refresh current; tRC = tRFC(min) Self refresh current; CKE <= 0.2V; Orerating current - Four bank operation; Four bank interleaving with BL=4 -Refer to the following page for detailed test condition Note: Symbol Max. Unit IDD0 3,180 mA IDD1 3,540 mA IDD2P 1,650 mA IDD2F 2,010 mA IDD3P 1,920 mA IDD3N 2,280 mA IDD4R 4,710 mA IDD4W 5,520 mA IDD5 IDD6 5,070 558 mA mA IDD7 8,040 mA Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Transcend Information Inc. 6 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF + 0.31 0.7 0.5*VDDQ - 0.2 Max Unit Note VREF - 0.31 VDDQ + 0.6 0.5*VDDQ + 0.2 V V V V 3 3 1 2 Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation the AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz. AC OPERATING TEST CONDITIONS (VDD=2.5, VDDQ=2.5, TA=0 to 70°C) Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels (VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.5*VDDQ 1.5 VREF+0.31/VREF-0.31 VREF VTT See Load Circuit Unit V V V V V Note VTT=0.5*VDDQ RT=50ohm Output ZO=50ohm VREF =0.5*VDDQ CLOAD=30pF Output Load circuit Input/Output CAPACITANCE (VDD = 2.5V, VDDQ = 2.5V,TA = 25°C, f = 1MHz) Parameter Input capacitance (SA0~SA12, SBA0~SBA1, /SRAS, /SCAS, /SWE) Input capacitance (SCKE0, SCKE1) Input capacitance (/SCS0, /SCS1) Input capacitance (CK0, /CK0) Input capacitance (SDM0~SDM8) Data and DQS input/output capacitance (SDQ0~SDQ63) Data input/output capacitance (SCB0~SCB7) Transcend Information Inc. 7 Symbol Min Max Unit CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 COUT2 6 5 5 8 12 12 12 8 7 7 10 14 14 14 pF pF pF pF pF pF pF 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 AC Timing Parameters & Specifications (These AC characteristics were tested on the Component) Parameter Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row active to Row active delay Row active to Row active delay Write recovery time Last data in to Read command Col. Address to Col. Address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK /CK Output data access time from CK /CK Data strobe edge to output data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control input setup time Address and Control input hold time Data-out high-impedance time from CK, /CK Data-out low-impedance time from CK, /CK Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to non-read command Exit self refresh to read command Refresh interval time Clock half period Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tHZ tLZ tMRD tDS tDH tDIPW tPDEX tXSNR tXSRD tREFI tHP Min 65 75 45 20 20 15 15 1 1 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 -0.75 -0.75 15 0.5 0.5 1.75 7.5 75 200 7.8 tCLmin or tCHmin Max 120K 12 0.55 0.55 0.75 0.75 0.5 1.1 0.6 1.25 1.1 0.75 0.75 Unit ns ns ns ns ns ns ns tCK tCK ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns tCK us ns Note 2 1 Data hold skew factor tQHS 0.75 ns DQS write postamble time tWPST 0.4 0.6 tCK 3 Note: 1. Maximum burst refresh of 8 2. The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The Maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are ≧45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. Transcend Information Inc. 8 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 SIMPLIFIED TRUTH TABLE COMMAND Extended Mode Register Set Mode Register Set Auto Refresh Entry Self Refresh Exit Register Register Refresh Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Burst Stop Precharge CKEn-1 CKEn /CS /RAS /CAS H X L L L L OP CODE 1,2 H X H L L L L L OP CODE L L L H X X 1,2 3 3 3 3 H L H L H H X H X H X H X L L H H V H X L H L H V H X L H L L H X L H H L Bank Selection All Banks H X Entry H L Active Power Down Exit Entry L H H L Precharge Power Down Mode L L H L H X X X L V V V X X X X H X X X L H H H H X X X L V V V H X X X L H H H DM L No Operation Command 5. 6. 7. 8. 9. L H L H Column Address (SA0~SA9, SA11) 4 Column Address (SA0~SA9, SA 11) 4 X V X L H 4 4, 6 7 X 5 X H H 4. V Row Address X Exit Note: 1. 2. 3. (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) SA0~SA9, SA11, /WE BA0, 1 SA10/AP Note SA12 H X X X 8 9 X 9 OP Code: Operand Code. A0 ~ A12 & BA0 ~ BA1: Program keys. (@EMRS/MRS) EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. BA0 ~ BA1: Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. During burst write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. Burst stop command is valid at every burst length. DM sampled at the rising and falling edges of the DQS and Data-in is masked at the both edges (Write DM latency is 0). This combination is not defined for any function, which means "No Operation (NOP)" in DDR SDRAM. Transcend Information Inc. 9 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 Serial Presence Detect Specification Serial Presence Detect Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function Described # of Bytes Written into Serial Memory Total # of Bytes of S.P.D Memory Fundamental Memory Type # of Row Addresses on this Assembly # of Column Addresses on this Assembly # of Module Rows on this Assembly Data Width of this Assembly Data Width of this Assembly VDDQ and Interface Standard of this Assembly DDR SDRAM Cycle Time at CAS Latency=2.5 DDR SDRAM Access Time from Clock at CL=2.5 DIMM configuration type (non-parity, Parity, ECC) Refresh Rate Type Primary DDR SDRAM Width Error Checking DDR SDRAM Width Min Clock Delay for Back to Back Random Column Address Burst Lengths Supported # of banks on each DDR SDRAM device CAS Latency supported CS Latency WE Latency 21 DDR SDRAM Module Attributes 22 DDR SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 DDR SDRAM Cycle Time CL=2.0 DDR SDRAM Access from Clock CL=2.0 DDR SDRAM Cycle Time CL=1.5 DDR SDRAM Access from Clock CL=1.5 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Activate delay (tRRD) Minimum RAS to CAS Delay (tRCD) Minimum active to Precharge time (tRAS) Module ROW density Command/Address Input Setup Time Command/Address Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information SPD Data Revision Code Checksum for Bytes 0-62 Manufacturers JEDEC ID Transcend Information Inc. 10 Standard Specification 128bytes 256bytes DDR SDRAM 13 11 2 bank 72bits 0 SSTL 2.5V 7.5ns 0.75ns ECC 7.8us/Self Refresh X4 X4 tCCD=1CLK Vendor Part 80 08 07 0D 0B 02 48 00 04 75 75 02 82 04 04 01 2,4,8 4 bank 2, 2.5 0 CLK 1 CLK Registered address & control inputs and on-card DLL +/-0.2V voltage tolerance 10ns 0.75ns 20ns 15ns 20ns 45ns 512MB 0.9ns 0.9ns 0.5ns 0.5ns Transcend 0E 04 0C 01 02 26 00 A0 75 00 00 50 3C 50 2D 80 90 90 50 50 00 00 11 7F, 4F 184Pin DDR266 1U Registered DIMM 1GB With 64Mx4 CL2.5 TS128MDR72V6L5 72 73-90 91-92 93-94 95-98 99-127 128~255 Manufacturing Location T Manufacturers Part Number TS128MDR72V6L5 Revision Code Manufacturing Date Assembly Serial Number Manufacturer Specific Data Unused Storage Locations Transcend Information Inc. By Manufacturer By Manufacturer Undefined 11 54 54 53 31 32 38 4D 44 52 37 32 56 36 4C 35 20 20 20 20 Variable Variable -