Download Transcend 512MB SDRAM PC133 Unbuffer Non-ECC Memory

168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
Description
The TS64MLS64V6F is a 64M bit x 64 Synchronous
Dynamic
RAM
high-density
for
PC-133.
Placement
The
TS64MLS64V6F consists of 16pcs CMOS 32Mx8 bits
Synchronous DRAMs in TSOP-II 400mil packages and a
2048 bits serial EEPROM on a 168-pin printed circuit
board. The TS64MLS64V6F is a Dual In-Line Memory
Module and is intended for mounting into 168-pin edge
connector sockets.
Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible on
every clock cycle. Range of operation frequencies,
programmable latencies allow the same device to be
A
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• RoHS compliant products.
• Performance Range: PC-133.
• Conformed to JEDEC Standard 4 clocks.
B
• Burst Mode Operation.
• Auto and Self Refresh.
D
• CKE Power Down Mode.
E
• DQM Byte Masking (Read/Write)
C
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
E
• Single 3.3V ± 0.3V power supply.
H
• MRS cycle with address key programs.
G
Latency (Access from column address)
F
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
PCB: 09-7309
Transcend information Inc.
1
I
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
Pin Identification
Dimensions
Symbol
Side
Millimeters
Function
Inches
A
133.35±0.40
5.250±0.016
B
65.67
2.585
C
23.49
0.925
D
8.89
0.350
E
3.00
0.118
F
29.21±0.20
1.150±0.008
G
19.80
0.788
H
15.80
0.622
I
1.27±0.10
0.050±0.004
(Refer Placement)
Transcend information Inc.
A0~A12, BA0, BA1 Address input
DQ0~DQ63
Data Input / Output.
CLK0~CLK3
Clock Input.
CKE0, CKE1
Clock Enable Input.
/CS0~/CS3
Chip Select Input.
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data (DQ) Mask
SA0~SA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
NC
No Connection
2
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
Pinouts:
Pin
Pin
Pin
No
Name
No
01
Vss
43
02
DQ0
44
03
DQ1
45
04
DQ2
46
05
DQ3
47
06
Vcc
48
07
DQ4
49
08
DQ5
50
09
DQ6
51
10
DQ7
52
11
DQ8
53
12
Vss
54
13
DQ9
55
14
DQ10
56
15
DQ11
57
16
DQ12
58
17
DQ13
59
18
Vcc
60
19
DQ14
61
20
DQ15
62
21
*CB0
63
22
*CB1
64
23
Vss
65
24
NC
66
25
NC
67
26
Vcc
68
27
/WE
69
28
DQM0
70
29
DQM1
71
30
/CS0
72
31
NC
73
32
Vss
74
33
A0
75
34
A2
76
35
A4
77
36
A6
78
37
A8
79
38
A10/AP
80
39
BA1
81
40
Vcc
82
41
Vcc
83
42
CLK0
84
* Please refer Block Diagram
Transcend information Inc.
Pin
Name
Vss
NC
/CS2
DQM2
DQM3
NC
Vcc
NC
NC
*CB2
*CB3
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
*Vref
*CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
*CLK2
NC
NC
SDA
SCL
Vcc
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
*CB4
*CB5
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
*/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
*CLK1
*A12
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
CKE0
*/CS3
DQM6
DQM7
*A13
Vcc
NC
NC
*CB6
*CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
*Vref
*REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
*CLK3
NC
SA0
SA1
SA2
Vcc
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
Block Diagram
CKE0
CKE
/WE
/CS
CKE
/RAS
/WE
/CS
CKE
32Mx8
SDRAM
/RAS
/CAS
/WE
/CS
CKE
32Mx8
SDRAM
CLK
/WE
/CS
/CAS
32Mx8
SDRAM
DQM
/CS0
/CAS
A0~A12,
BA0,BA1
DQ0~DQ7
CLK
/WE
32Mx8
SDRAM
CLK
/CAS
A0~A12,
BA0,BA1
DQ0~DQ7
DQM
/RAS
/CAS
CLK
/RAS
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
DQM
A0~A12,
BA0,BA1
DQ0~DQ7
DQM
A0~A12
BA0,BA1
DQ0~DQ63
DQM0
DQM1
DQM2
DQM3
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
32Mx8
/RAS
/RAS
/RAS
32Mx8
/CAS
SDRAM
/CAS
/CAS
SDRAM
DQM4
DQM5
DQM6
DQM7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
/RAS
/RAS
/RAS
/RAS
/CAS
32Mx8
SDRAM
/CAS
32Mx8
SDRAM
/CAS
CKE
CKE
DQM1
DQM2
DQM3
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
A0~A12,
BA0,BA1
DQ0~DQ7
DQM4
DQM5
SCL
Serial EEPROM
SCL
SDA
A0 A1 A2
CKE
DQM6
32Mx8
SDRAM
CLK
/WE
/CS
/WE
/CS
CKE
/RAS
/CAS
DQM
32Mx8
SDRAM
CLK
CKE
/RAS
/CAS
DQM
/WE
/CS
32Mx8
SDRAM
CLK
/RAS
/CAS
CLK1
CLK3
CKE
DQM0
DQM
/CS3
CKE
CLK
CKE1
DQM
/CS
CLK
/WE
/CS
DQM
/WE
/CS
CLK
/WE
/CS
DQM
/WE
/CS1
32Mx8
SDRAM
DQM
/CAS
32Mx8
SDRAM
/RAS
/CAS
/WE
/CS
CKE
CLK
CKE
CLK
/WE
/CS
32Mx8
SDRAM
CLK
CKE
CLK
/WE
/CS
DQM
/CLK
CLK
DQM
/CAS
32Mx8
SDRAM
DQM
CLK0
CLK2
CKE
DQM
/WE
/CS
/WE
/CS
CKE
32Mx8
SDRAM
DQM
/CS2
DQM7
SDA
SA0 SA1 SA2
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties,
either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the
right to make changes in specifications at any time without prior notice.
Transcend information Inc.
4
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0~4.6
V
Voltage on VDD supply to Vss
VDD, VDDQ
-1.0~4.6
V
TSTG
-55~+150
°C
PD
16
W
Storage temperature
Power dissipation
Short circuit current
IOS
50
mA
Operating Temperature
TA
0~70
°C
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
-
-
V
IOH=-2mA
Output low voltage
VOL
-
-
0.4
V
IOL=2mA
IIL
-10
-
10
uA
3
Input leakage current (Inputs)
Note
Input leakage current (I/O pins)
IIL
uA
Note: 1. VIH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
Transcend information Inc.
5
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ±200 mV)
Parameter
Input capacitance (A0~A12, BA0~ BA1)
Input capacitance (/RAS, /CAS, /WE)
Input capacitance (CKE0, CKE1)
Input capacitance (/CLK0~ /CLK3)
Input capacitance (/CS0~ /CS3)
Input capacitance (DQM0~DQM7)
Data input/output capacitance (DQ0~DQ63)
Symbol
Min
Max
Unit
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT1
80
80
50
40
25
15
10
100
100
60
45
35
20
15
pF
pF
pF
pF
pF
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to70°C)
Parameter
Symbol
Test Condition
CAS Latency
Operating Current
(One Bank Active)
ICC1
ICC2P
Precharge Standby Current
ICC2PS
in power-down mode
ICC2N
Value (Typ)
Unit
Note
960
mA
1
Burst Length =1
tRC≥tRC(min)
IOL=0mA
CKE≤VIL(max), tCC=10ns
32
CKE & CLK≤VIL(max), tCC=∞
32
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
320
mA
Input signals are changed one time during 20ns
Precharge Standby Current
in non power-down mode ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
mA
160
Input signals are stable
Active Standby Current
in power-down mode
ICC3P
CKE≤VIL(max), tCC=10ns
96
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
96
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
480
ICC3N
Active Standby Current
in non power-down mode
(One Bank Active)
Input signals are changed one time during 20ns
ICC3NS
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
mA
mA
400
Input signals are stable
Operating Current
(Bust Mode)
ICC4
IOL= 0 mA
Page Burst
tccD = 2CLKs
1,120
mA
Refresh Current
ICC5
tRC≥tRC(min)
1,840
mA
Self Refresh Current
ICC6
C
48
CKE≤0.2V
mA
L
Note:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL=VDDQ/VSSQ)
Transcend information Inc.
6
24
1
2
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
AC OPERATING TEST CONDITIONS (VDD = 3.3V ±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Symbol
Value
Unit
Note
Row active to row active delay
tRRD(min)
15
ns
1
/RAS to /CAS delay
tRCD(min)
20
ns
1
Row precharge time
tRP(min)
20
ns
1
tRAS(min)
45
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
65
ns
1
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to Active delay
tDAL
2CLK+tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
2
ea
4
Row active time
Number of valid output data
CAS latency=3
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc.
7
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
Min
CLK cycle time
CAS latency=3
CAS latency=2
CLK to valid
output delay
CAS latency=3
Output data
hold time
CAS latency=3
Max
7.5
tCC
1000
-
tSAC
CAS latency=2
5.4
Unit
Note
ns
1
ns
1, 2
ns
2
3
tOH
CAS latency=2
-
CLK high pulse width
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output
in Hi-Z
Note:
CAS latency=3
5.4
tSHZ
ns
CAS latency=2
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc.
8
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Refresh
Auto Refresh
Self
Entry
Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
Both Banks
Clock Suspend or Entry
Active
Power
Down
Exit
Precharge Power
Down Mode
CKEn-1 CKEn
/CS
/RAS
/CAS
/WE
DQM
A10/AP
H
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
L
H
L
X
V
X
V
X
V
X
L
H
X
X
X
X
X
H
X
X
X
H
L
L
H
H
H
H
X
X
X
L
V
V
V
Entry
V
X
A11,A12,
A0~A9
Note
1,2
3
3
3
3
Row Address
L
H
L
H
X
L
H
Column
Address
(A0~A9)
Column
Address
(A0~A9)
4
4, 5
4
4, 5
6
X
X
X
X
Exit
L
DQM
No Operation Command
BA0,1
H
X
H
H
X
H
X
X
X
L
H
H
H
X
V
X
X
X
7
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note:
1. OP Code : Operand Code
A0~A12, BA0~BA1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc.
9
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
22
SDRAM Device Attributes : General
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
Standard
Specification
128bytes
256bytes
SDRAM
13
10
2 bank
64bits
LVTTL3.3V
7.5ns
5.4ns
Non parity
7.8us/Self Refresh
X8
None
1 clock
1,2,4,8 & Full page
4 bank
2, 3
0 clock
0 clock
Non Buffer
Prec All, Auto Prec,
R/W Burst
10ns
6ns
20ns
15ns
20ns
45ns
1row of 256MB
1.5ns
0.8ns
1.5ns
0.8ns
JEDEC2
-
Function Described
nd
SDRAM Cycle Time (2 highest CL)
SDRAM Access from Clock (2nd highest CL)
SDRAM Cycle Time (3rd highest CL)
SDRAM Access from Clock (3rd highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Transcend information Inc.
10
Vendor Part
80
08
04
0D
0A
02
40
00
01
75
54
00
82
08
00
01
8F
04
06
01
01
00
0E
A0
60
00
00
14
0F
14
2D
40
15
08
15
08
00
02
C3
168PIN PC133 Unbuffered DIMM
512MB With 32Mx8 CL3
TS64MLS64V6F
64-71
72
Manufacturers JEDEC ID Code per JEP-108E
Manufacturing Location
73-90
Manufacturers Part Number
91-92
93-94
95-98
99-125
126
127
128~
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend information Inc.
Transcend
T
TS64MLS64V6F
11
By Manufactory
By Manufactory
CL=2, 3 Clock 0~3
Open
7F, 4F
54
54 53 36 34 4D 4C
53 36 34 56 36 46
20 20 20 20 20 20
0
Variable
Variable
0
64
F6
FF