Download Super Talent Technology 512MB DDR SC Kit
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512MB Unbuffered DIMM DDR SDRAM DDR SDRAM Unbuffered MODULE 184pin Unbuffered Module based on 32Mbx8 & 64Mbx8 64/72-bit Non-ECC/ECC Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 1 512MB Unbuffered DIMM DDR SDRAM 1.0 Feature • VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V for DDR333 • VDD: 2.6V ± 0.1V, VDDQ: 2.6V ± 0.2V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQ] x8) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM • PCB : Height 1,250 (mil) & single (512MB), double (512MB) sided • SSTL_2 Interface • 66pin TSOP II package 2.0 Ordering Information Part number Density Organization Component composition No. of rank Height 2 1 1.25” 1.25” x64 Non ECC D32PB12C25 D32PA512N 512MB 512MB 64x64 64x64 32mx8 TSOP II 64Mx8 TSOP II 512MB 512MB 64x72 64x72 32mx8 TSOP II 64Mx8 TSOP II x72 ECC 2 1 3.0 Operating Frequencies CC(DDR400@CL=3) Speed @CL2 Speed @CL2.5 Speed @CL3 CL-tRCD-tRP 166MHz 200Mhz 3-3-3 B3(DDR333@CL=2.5) 133MHz 166MHz 2.5-3-3 4.0 Absolute Maximum DC Rating Symbol Vin, Vout VDD, VDDQ Ios Pd TSTG Note: • • • Parameter Voltage on any pin relative to VSS Voltage on VDD & Vddq Short circuit current Power dissipation Storage Temperature supply relative to Vss Rating Units -0.5 ~ 3.6 -1.0 ~ 3.6 V V 50 1.5 * #of component 55 ~ + 150 mA w °C Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 2 512MB Unbuffered DIMM DDR SDRAM 5.0 DIMM Pin Configurations (Front side/Back side) Pin Front Pin Front Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 KEY 53 54 55 56 57 58 59 60 61 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD *CS2 DQ48 DQ49 VSS CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back Pin Back Pin Back VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 RAS DQ45 VDDQ CS0 CS1 DM5 VSS DQ46 DQ47 *CS3 VDDQ DQ52 DQ53 *A13 VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 KEY 145 146 147 148 149 150 151 152 153 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0 VSS DM8 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Note: * These pins are not use in this module 6.0 Dimm Pin Description Pin Name Function Pin Name Function A0 ~ A12 Address input (multiplex) DM0 ~ DM7 BA0 ~ BA1 Bank Select Address VDD DQ0~DQ63 Data input/output VDDQ DQS0~DQS7 CK0, CK0 ~ CK2, CK2 CKE0, CKE1 CS0, CS1 RAS CAS WE Data Strobe input/output VSS Data in mask Power Supply (2.5V for DDR333, 2.6V FOR DDR400) Power Supply for DQS (2.5V for DDR333, 2.6V for DDR400) Ground Clock input VREF Power Supply for reference Clock enable input Chip select input Row address strobe Column address strobe Write enable VDDSPD SDA SCL SA0~2 VDDID Serial EEPROM Power/Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in Eeprom VDD, VDDQ level detection Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 3 512MB Unbuffered DIMM DDR SDRAM 7.0 Functional Block Diagram: 7.1 512MB, 64x64 Module (populated as 1 rank of 64x8 SDRAMs) Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 4 512MB Unbuffered DIMM DDR SDRAM 7.2 512MB, 8x64 Module (populated as 2 rank of 32x8 SDRAMs) Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 5 512MB Unbuffered DIMM DDR SDRAM 7.3 512MB, 64mx72 Module (populated as 1 rank of 64x8 SDRAMs) Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 6 512MB Unbuffered DIMM DDR SDRAM 7.4 512MB, 64x72 Module (populated as 2 rank of 32x8 SDRAMs) Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 7 512MB Unbuffered DIMM DDR SDRAM 8.0 DC Operating Conditions Recommended operating conditions (Voltage referenced to Vss=0V, TA=0 to 70°C) Symbol VDD VDD VDDQ VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VI(Ratio) IIN IOZ IOH IOL IOH IOL Parameter Supply voltage (nominal Vdd 2.5V for DDR333) Supply voltage ( nominal VDD 2.6V for DDR400) Supply voltage (nominal Vdd 2.5V for DDR333) Supply voltage ( nominal VDD 2.6V for DDR400) I/O Reference voltage I/O Termination voltage (system) Input logic high voltage Input logic low voltage Input voltage level, CK and CK inputs Input differential voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ration Input leake current Output leakage current Output high current (Normal strengh driver); VOUT = VTT + 0.84V Output high current (Normal strengh driver); VOUT = VTT - 0.84V Output high current (Half strengh driver); VOUT = VTT + 0.45V Output high current (Half strengh driver); VOUT = VTT - 0.45V 9.0 AC Operating Conditions Symbol Parameter/Condition VIH(AC) VIL(AC) VID(AC) VIX(AC) CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 COUT2 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 COUT2 Max Unit 2.3 2.5 2.3 2.5 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.71 -2 -5 -16.8 16.8 -9 9 2.7 2.7 2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.4 2 5 V V V V V V V V V V µA µA mA mA mA mA Min Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input voltage level, CK and CK inputs Input crossing point voltage, CK and CK inputs Max Unit VREF+0.31 VDDQ+0.6 0.5*VDDQ-0.2 V V V V VREF+0.31 0.7 0.5*VDDQ-0.2 Note Note VDD=2.5V, VDDQ=2.5V, TA=25°C, f=1MHZ 10. Input/Output Capacitance Symbol Min D32PA512N Parameter/Condition Input capacitance (A0~A12, BA0~BA1, RAS, CAS, WE) Input capacitance (CKE0) Input capacitance (CS0) Input capacitance (CLK0, CLK1, CLK2) Input capacitance (DM0 ~ DM7, DM8 (for ECC)) Data & DQS input/output capacitance (DQ0 ~ DQ63) Data input/output capacitance (CB0 ~ CB7) Min Max 49 42 42 25 6 6 - 57 50 50 30 7 7 - Min Max 51 44 44 25 6 6 6 60 53 53 30 7 7 7 D32PB12C25 Parameter/Condition Input capacitance (A0~A12, BA0~BA1, RAS, CAS, WE) Input capacitance (CKE0) Input capacitance (CS0) Input capacitance (CLK0, CLK1, CLK2) Input capacitance (DM0 ~ DM7, DM8 (for ECC)) Data & DQS input/output capacitance (DQ0 ~ DQ63) Data input/output capacitance (CB0 ~ CB7) Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 8 Min Max 65 42 42 28 10 10 - 81 50 50 34 12 12 - Min Max 69 44 44 28 10 10 10 87 53 53 34 12 12 12 Unit pF pF pF pF pF pF PF Unit pF pF pF pF pF pF pF 512MB Unbuffered DIMM DDR SDRAM 11.0 AC Timing Parameters & Specifications Parameter Symbol Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Clock cycle time tRC tRFC tRAS tRCD tRP tRRD tWR tWTR CL=2.0 CL=2.5 CL=3.0 Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to output data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-setup time DQS-in high level width DQS-in low level width Address and Control input setup time (fast) Address and Control input hold time (fast) Address and Control input setup time (slow) Address and Control input hold time (slow) Data-out high impedance time from CK/CK Data-out low impedance time from CK/CK Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Exit self refresh to non-Read command Exit self refresh to Read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharged time tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tIS tIH tIS tIH tHZ tLZ tMRD tDS tDH tIPW tDIPW tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL CC (DDR400@CL=3.0) Min Max 55 70 40 70K 15 15 10 15 2 6 12 5 10 0.45 0.55 0.45 0.55 -0.55 +0.55 -0.65 +0.65 +0.4 0.9 1.1 0.4 0.6 0.72 1.28 0 0.25 0.2 0.2 0.35 0.35 0.6 0.6 0.7 0.7 -0.65 +0.65 -0.65 +0.65 10 0.4 0.4 2.2 1.75 75 200 7.8 THPtQHS TCLmin or tCHmin 0.5 0.4 0.6 15 (tWR/tCK )+ (tRP/tCK) Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 9 B3 (DDR333@CL=2.5) Min Max 60 72 42 70K 18 18 12 15 1 7.5 12 6 12 0.45 0.55 0.45 0.55 -0.6 +0.6 -0.7 +0.7 +0.45 0.9 1.1 0.4 0.6 0.75 1.25 0 0.25 0.2 0.2 0.35 0.35 0.75 0.75 0.8 0.8 -0.7 +0.7 -0.7 +0.7 12 0.45 0.45 2.2 1.75 75 200 7.8 THPtQHS TCLmin or tCHmin 0.55 0.4 0.6 18 (tWR/tCK )+ (tRP/tCK) Unit ns ns ns ns ns ns ns tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns tCK ns ns ns ns tCK tCK Note 512MB Unbuffered DIMM DDR SDRAM 12.0 Physical Dimensions: 64Mbx8 based component, 64x64 & 64x72 Modules , populated as 1 Rank. Note: All dimensions are typical unless otherwise state millimeters inches Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 10 512MB Unbuffered DIMM DDR SDRAM 32Mbx8 based component, 64x64 & 64x72 Modules, populated as 2 Ranks Note: All dimensions are typical unless otherwise state millimeters inches Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 11 512MB Unbuffered DIMM DDR SDRAM Revision History Revision 1.0 (Mar. 2006) -Initial Release Products and Specifications discussed herein are subject to change without notice © 2006 Super Talent Tech., Corporation. 12