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Chapter 2
Configuration and Installation
Timing Requirements and Communication Protocol
Communication Signals
This section describes the methods for communicating on the Serial Peripheral Interface (SPI)
bus and their timing requirements. The communication signals are SERDATIN, DAQD*/A,
SLOT0SEL*, SERDATOUT, and SERCLK. Furthermore, Slot 0 produces SS* according to
data acquisition board programming; therefore SS* timing relationships will also be discussed.
For information on the Slot 0 Slot-Select Register, consult Chapter 4, Register Descriptions.
The data acquisition board determines to which slot it will talk to by writing a slot-select number
to Slot 0. In the case of an SCXI-1001 chassis, this write also determines to which chassis the
data acquisition board will talk.
Use the following procedure for selecting a slot in a particular chassis. Figure 2-7 illustrates the
timing of this procedure with the example of selecting Slot 11 in Chassis 9. Notice that the
factory-default chassis address for the SCXI-1001 is address 0. For information on changing the
address of your chassis, consult the SCXI-1000/1001 User Manual. An SCXI-1000 chassis will
respond to any chassis number.
SLOT0SEL*
Tss_dis
SS*X
Chassis Y
SS*11
Chassis 9
Tclk_wait
Tss_en
SERCLK
Tslot0sel*_wait
SERDATIN
0
1
0 0
1
1 0
Chassis ID = 9
Tss _ dis
Tclk _ wait
Tslot0sel* _ wait
Tss _ en
SLOT0SEL* low to SS* disabled
SLOT0SEL* low to first rising edge on SERCLK
Last rising edge on SERCLK to SLOT0SEL* high
SLOT0SEL* high to SS* enabled
1
1
Slot 11
200 nsec maximum
75 nsec minimum
250 nsec minimum
450 nsec maximum
Figure 2-7. Slot-Select Timing Diagram
To write the 16-bit slot-select number to Slot 0, follow these steps:
1. Initial conditions:
SERDATIN = don't care.
DAQD*/A = 1.
SLOT0SEL* = 1.
SERCLK = 1.
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SCXI-1162 User Manual