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Chapter 15: PowerPC Specific Information
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15.8.1 System Reset
An RTEMS based application is initiated or re-initiated when the PowerPC processor is
reset. The PowerPC architecture defines a Reset Exception, but leaves the details of the
CPU state as implementation specific. Please refer to the User’s Manual for the CPU model
in question.
In general, at power-up the PowerPC begin execution at address 0xFFF00100 in supervisor
mode with all exceptions disabled. For soft resets, the CPU will vector to either 0xFFF00100
or 0x00000100 depending upon the setting of the Exception Prefix bit in the MSR. If during
a soft reset, a Machine Check Exception occurs, then the CPU may execute a hard reset.
15.8.2 Processor Initialization
If this PowerPC implementation supports on-chip caching and this is to be utilized, then
it should be enabled during the reset application initialization code. On-chip caching has
been observed to prevent some emulators from working properly, so it may be necessary to
run with caching disabled to use these emulators.
In addition to the requirements described in the Board Support Packages chapter of the
RTEMS C Applications User’s Manual for the reset code which is executed before the call
to rtems_initialize_executive, the PowrePC version has the following specific requirements:
• Must leave the PR bit of the Machine State Register (MSR) set to 0 so the PowerPC
remains in the supervisor state.
• Must set stack pointer (sp or r1) such that a minimum stack size of MINIMUM STACK SIZE bytes is provided for the RTEMS initialization sequence.
• Must disable all external interrupts (i.e. clear the EI (EE) bit of the machine state
register).
• Must enable traps so window overflow and underflow conditions can be properly
handled.
• Must initialize the PowerPC’s initial Exception Table with default handlers.