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D0..19
D20..31
Reserved
Queue Base Address
Local Memory base address of the Inbound and Outbound Queues (four contiguous and equal
size FIFOs). Queue base address must be aligned on a 1 MB boundary.
2.12.7 INBOUND FREE HEAD P OINTER REGISTER (PCI 0XC8)
D0..1
D2..19
D20..31
Reserved
Inbound Free Head Pointer
Local memory Offset for Inbound Free List FIFO. This register is initialized as (0*FIFO Size) and
maintained by the local CPU software.
Queue Base Address
2.12.8 INBOUND FREE HEAD TAIL REGISTER (PCI 0XCC)
D0..1
D2..19
D20..31
Reserved
Inbound Free Tail Pointer
Local Memory Offset for Inbound Free List FIFO. This register is initialized as (0*FIFO Size) by
the local CPU software. It is maintained by the MU hardware and is incremented modulo the FIFO
size.
Queue Base Address
2.12.9 INBOUND P OST HEAD P OINTER REGISTER (PCI 0XD0)
D0..1
D2..19
D20..31
Reserved
Inbound Post Head Pointer
Local Memory Offset for Inbound Post List FIFO. This register is initialized as (1*FIFO Size) by
the local CPU software. It is maintained by the MU hardware and is incremented modulo the FIFO
size.
Queue Base Address
2.12.10 INBOUND P OST TAIL P OINTER REGISTER (PCI 0XD4)
D0..1
D2..19
D20..31
Reserved
Inbound Post Tail Pointer
Local Memory Offset for Inbound Post List FIFO. This register is initialized as (1*FIFO Size) by
the local CPU software.
Queue Base Address
2.12.11 OUTBOUND FREE HEAD P OINTER REGISTER (PCI 0XD8)
D0..1
D2..19
D20..31
Reserved
Outbound Free Head Pointer
Local Memory Offset for Outbound Free List FIFO. This register is initialized as (3*FIFO Size) by
the local CPU software. It is maintained by the MU hardware and is incremented modulo the FIFO
size.
Queue Base Address
2.12.12 OUTBOUND FREE TAIL P OINTER REGISTER (PCI 0XDC)
D0..1
D2..19
Reserved
Outbound Free Tail Pointer
User Manual for the PMC-SIO4-RS232 Card, Revision: B
General Standards Corporation
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