Download Master Product Selector Guide

Master Product Selector Guide
ASIC
Fujitsu fully supports an “open” design flow that allows designers
to use the EDA tools of their choice from all mainstream EDA vendors. Three major third party EDA vendors supported are
Cadence, Synopsys, and Mentor Graphics. The official signoff
EDA simulation tools are Cadence Verilog, Synopsys VCS and
VSS, and Model-sim (Verilog/VHDL) from Mentor Graphics.
Other popular third party tools supported are as follows:
Synopsys
Design Compiler, Movie/Prime Time, Design Power/Power Compiler, and TestGen/Test Compiler
Cadence
NC-Verilog, Leapfrog, Design Planner, CTGen, PBOpt,
Wroute/SE, Hyper Extract and Dracula
Product
Drawn Geometry (µm)
CX61
0.35
DesignVerifyer from Chrysalis and WattWatcher from Sante.
Fujitsu’s packaging options span a wide range–from low-cost plastic QFPs and BGAs, to high pin-count FBGA and FCBGA–so
that the designers can choose the optimal package to fit their
unique design criteria.
Fujitsu recognizes that today’s designers need total solutions in
order to successfully implement their ASIC designs. In addition to
Fujitsu’s industry-leading silicon process and packaging technology, the company also offers a wide range of system-level design
support tools, including clock skew measurement, scan insertion,
and ATPG test support, as well as RAM and ROM compilers.
FMI’s U.S.-based multidisciplinary engineering support staff is
ready to assist customers.
Descriptions
Embedded array
68K to 2M gates, 144 to 672 signal I/Os, 81 ps gate delay, 0.17µW/gate/MHz
CX66
0.35
Embedded array and standard cells
CX71
0.25
Embedded array and standard cells
CX81
0.18
Embedded array and standard cells
91K to 1.1M gates, 126 to 312 signal I/Os, 93 ps gate delay, 0.15µW/gate/MHz
167K to 8M gates, 88 to 506 signal I/Os, 60 ps gate delay, 0.06µW/gate/MHz
540K to 22M gates, 126 to 1320 signal I/Os, 53 ps gate delay, 0.022µW/gate/MHz
4
Fujitsu Microelectronics, Inc.