Download IA-32 Intel® Architecture Software Developer`s Manual

VM EXITS
— Task switch. Details about the reason for the VM exit are encoded as shown in
Table 23-2.
Table 23-2. Exit Qualification for Task Switch
Bit Position(s)
Contents
15:0
Selector of task-state segment (TSS) to which the guest attempted to switch
29:16
Reserved (cleared to 0)
Source of task switch initiation:
0: CALL instruction
1: IRET instruction
2: JMP instruction
3: Task gate in IDT
31:30
Reserved (cleared to 0). These bits exist only on processors that support Intel
EM64T.
63:32
— For INVLPG, the exit qualification contains the linear-address operand of the
instruction.
•
On processors that support Intel EM64T, bits 63:32 are cleared if the logical
processor was not in 64-bit mode before the VM exit.
•
If the INVLPG source operand specifies an unusable segment, the linear address
specified in the exit qualification will match the linear address that the INVLPG
would have used if no VM exit occurred. Note that this address is not architecturally defined and may be implementation-specific.
— VMCLEAR, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXON. The exit
qualification receives the value of the instruction’s displacement field, which is signextended to 64 bits if necessary (32 bits on processors that do not support Intel
EM64T). If the instruction has no displacement (for example, has a register operand),
zero is stored into the exit qualification.
On processors that support Intel EM64T, an exception is made for RIP-relative
addressing (used only in 64-bit mode). Such addressing causes an instruction to use an
address that is the sum of the displacement field and the value of RIP that references
the following instruction. In this case, the exit qualification is loaded with the sum of
the displacement field and the appropriate RIP value.
In all cases, bits of this field beyond the instruction’s address size are undefined. For
example, suppose that the address-size field in the VMX-instruction information field
(see Section 20.9.4 and Section 23.2.4) reports an n-bit address size. Then bits 63:n
(bits 31:n on processors that do not support Intel EM64T) of the instruction
displacement are undefined.
23-6 Vol. 3B