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Download ECE5465/Intel arch reference/Intel 64 and 32 Arch Sw Dev Man V3B
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PERFORMANCE-MONITORING EVENTS Table A-10. Performance Monitoring Events Supported by Intel NetBurst Microarchitecture for Non-Retirement Counting (Contd.) Event Name Event Parameters Parameter Value Counter numbers per ESCR ESCR0: 8, 9 ESCR Event Select 0CH ESCR1: 10, 11 ESCR Event Mask CCCR Select Description ESCR[31:25] ESCR[24:9] Bit 15: ALL Count all μops operating on packed double-precision operands. 01H CCCR[15:13] Event Specific Notes If an instruction contains more than one packed DP μops, each packed DP μop that is specified by the event mask will be counted. scalar_SP_uop This event increments for each scalar single-precision μop, specified through the event mask for detection. ESCR restrictions MSR_FIRM_ESCR0 MSR_FIRM_ESCR1 Counter numbers per ESCR ESCR0: 8, 9 ESCR Event Select 0AH ESCR1: 10, 11 ESCR Event Mask CCCR Select ESCR[24:9] Bit 15: ALL Count all μops operating on scalar single-precision operands. 01H CCCR[15:13] Event Specific Notes If an instruction contains more than one scalar SP μops, each scalar SP μop that is specified by the event mask will be counted. scalar_DP_uop This event increments for each scalar double-precision μop, specified through the event mask for detection. ESCR restrictions MSR_FIRM_ESCR0 MSR_FIRM_ESCR1 A-188 Vol. 3 ESCR[31:25]
