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Download SMT310Q User Manual - Sundance Multiprocessor Technology Ltd.
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Version 2.1 Page 30 of 55 8.2 SMT310Q User Manual PCI-To-SMT310Q Interrupts CONTROL CPLD CONTROL REGISTER PCI Bridge LINT can be caused by any PCI interrupt e.g. Mailbox LINT IIOF0 TIMIIOF0 IIOF1 TIMIIOF1 IIOF2 TIMIIOF2 INTREG REGISTER LINT TIMIIOF0 IE TIMIIOF1 IE TIMIIOF2 IE Figure 10: PCI to SMT310Q Interrupts 8.3 Interrupt Registers The following registers are used to control PCI►DSP and DSP►PCI interrupts: • PCI bridge internal register • PCI Interrupt Configuration (BAR 0, 4C16) • PCI Interrupt Status (BAR 0, 4816) • Local Bus Interrupt Mask (BAR 0, 7716) • Local Bus Interrupt Status (BAR 0, 7616) • PCI Mailbox Write Interrupt Control (BAR 0, D016) • PCI Mailbox Read Interrupt Control (BAR 0, D216) • Local Bus Mailbox Write Interrupt Control (BAR 0, D416) • Local Bus Mailbox Read Interrupt Control (BAR 0, D616) • Mailbox Write Interrupt Status (BAR 0, D816) • Mailbox Read Interrupt Status (BAR 0, DA16)
