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EVB-USB3300-XLX User
Manual
The information contained herein is proprietary to SMSC, and shall be used solely in accordance with the agreement pursuant to which it is provided. Although the information is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to this document and to specifications and product descriptions at any
time without notice. Neither the provision of this information nor the sale of the described semiconductor devices conveys
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SMSC EVB-USB3300-XLX
Revision 0.4 (06-29-07)
EVB-USB3300-XLX User Manual
1 Introduction
The SMSC USB3300 USB Transceiver features a ULPI interface to support systems implementing a
USB Host, Device, or On-the-Go (OTG) system. SMSC supplies a complete family of PHY products
to meet the needs of many applications.
2 Overview
The EVB-USB3300-XLX is a Daughter Card designed to plug into a user's Xilinx ML401 development
system using a header connector. The card attaches to a USB link layer to create a USB Host, Device,
or On-the-Go (OTG) system. The digital interface meets the UTMI+ Low Pin Interface (ULPI)
specification. The ULPI specification can be downloaded from the SMSC web site at
http://www.smsc.com/main/catalog/usb3300.html. The EVB-USB3300-XLX includes the USB300 and
all associated external components. Figure 3 shows a schematic of the EVB.
2.1
3.3 Volt Power Supply
The EVB-USB3300-XLX requires a 3.3 volt supply capable of providing 80mA of current to be present
at the J2 header pins 16, 19, 22 and 25. For device only applications this is the only power the EVBUSB3300-XLX requires.
2.2
Crystal Oscillator
A 24 MHz crystal is connected to the internal oscillator of the USB3300. A PLL circuit in the USB3300
generates the 60MHz CLKOUT signal used by the link layer.
2.3
USB Connector
A standard Mini-AB connector is provided to attach a USB cable.
2.4
Supplying VBUS Power
In host or OTG applications the EVB-USB3300-XLX must provide 5 volts on VBUS. The EVB-USB3300XLX includes a 5 volt switch that can connect 5 volts to VBUS. The EVB-USB3300-XLX 5 volt supply
can come from either external power supplied at J5 or from header J1 pins 1, 4, 7 and 10. Jumper J6
must be installed to source +5V for the ML501 header. When using J5 to supply external power, J6
must be removed.
The 5 volt switch is controlled by the CPEN signal from the USB3300. The CPEN state is controlled
by ULPI registers in the USB3300 per the ULPI specification. The 5 volt switch has an undervoltage
lockout that turns the switch off if the VBUS voltage is low and the switch prevents reverse current
flow (backdrive) when in the off state. The switch does not provide protection from reverse currents
when in the on state. The user should take care to ensure the switch is off when VBUS is being sourced
by the USB cable.
In host mode, connector J7 should be installed to add capacitance to VBUS. The USB2.0 specification
requires this extra capacitance be present in host implementations.
Revision 0.4 (06-29-07)
SMSC EVB-USB3300-XLX
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EVB-USB3300-XLX User Manual
2.5
Digital I/O
The ULPI signals are routed to connector J1 for connection to the ML401. Each signal on J1 is
described in Table 2.1. All ULPI signals are 3.3V CMOS compatible.
Table 2.1 Signals on 3x13-Pin Header
J1 Pin
Signal Name
J1 Pin
Signal Name
J1 Pin
Signal Name
1
+5V
2
GND
3
Reset
4
+5V
5
GND
6
NXT
7
+5V
8
GND
9
CLKOUT
10
+5V
11
GND
12
DIR
13
NC
14
GND
15
STP
16
+3.3V
17
GND
18
DATA7
19
+3.3V
20
GND
21
DATA6
22
+3.3V
23
GND
24
DATA5
25
+3.3V
26
GND
27
DATA4
28
NC
29
GND
30
DATA3
31
RSVD1
32
GND
33
DATA2
34
RSVD2
35
GND
36
DATA1
37
RSVD3
38
GND
39
DATA0
SMSC EVB-USB3300-XLX
Revision 0.4 (06-29-07)
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EVB-USB3300-XLX User Manual
2.6
ULPI Signal Test Points
The headers J2, J3 and J4 provide easy access to the ULPI signals, and each pin has a silk screen
label as shown in Figure 1 .
Figure 1 ULPI Signal Test Points
2.7
Block Diagram
The EVB-USB3300-XLX block diagram shows how the jumpers are used on the board.
J5
5V DC
Input
VBUS Switch
500 mA current limit
w/ Fault Detection
U1
ONA
J7
5.6uF
FAULTAn
J7 Install for
Host mode
J6
Install to source +5V
from the FPGA
development system.
USB3300
VBUS
DM
J1
EXTVBUS
3x13
Header
DP
ID
5V
150uF
DM
DP
ID
GND
CPEN
VDD3.3
VDD3.3
ULPI Bus
USB OTG
Connector
ULPI Signals
24 MHz XTAL
Figure 2 EVB-USB3300-XLX Block Diagram
Revision 0.4 (06-29-07)
SMSC EVB-USB3300-XLX
4
SMSC EVB-USB3300-XLX
5
A
B
C
D
5
4
+3.3V
RSVD3
RSVD2
RSVD1
J4
J3
J2
+5V
HDR_1x5
HDR_1x5
HDR_1x5
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
5
1
2
4
5
7
8
10
11
13
14
16
17
19
20
22
23
25
26
28
29
31
32
34
35
37
38
J1
DATA5
DATA4
24
27
39
36
33
DATA0
DATA1
DATA2
DATA3
DATA6
30
STP
DATA7
21
DIR
18
CLKOUT
12
15
NXT
9
Reset
6
3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
DATA4
DATA3
RESET
NXT
CLKOUT
DIR
STP
NXT
DIR
STP
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
2
3
1
EXT_VBUS_DET
CLKOUT
Power_Jack
J5
4
C6
33pF
50V
C15
0.1uF
16V
C1
1.0uF
16V
24Mhz
Y1
J4
C16
4.7uF
6.3V
1M
1/10W
R4
HDR_1x2
1
J6
2
C17
0.1uF
16V
+5V
C18
4.7uF
6.3V
C2
33pF
50V
VDD1.8
VDD1.8
VDDA1.8
FB3
3
C21
0.01uF
16V
C19
10uF
6.3V
12.0K
1/10W
R5
EXT_VBUS_DET
1
MTG250P125D
MH
TEST_POINT
Black
MH2
1
TP2
1
2
31
30
6
16
25
32
8
7
5
3
4
9
MTG250P125D
MH
C20
0.1uF
16V
+3.3VA
GND
GND
VDDA3.3
VDDA3.3
VDDA3.3
VDD3.3
VDD3.3
RBIAS
DM
DP
ID
CPEN
VBUS
RESET
C5
1.0uF
16V
MH1
USB3300
EXT_VBUS_DETECT
CLKOUT
NXT
DIR
STP
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
XI
XO
U3
F-BEAD
500mA / 0.1DCR
+3.3V
15
26
29
10
14
11
12
13
17
18
19
20
21
22
23
24
28
27
1 = T&MT 5V Power Supply
0 = External 5V Power Supply
3
5
2
3
4
1
OUTA
GND
OUTB
MAX1823B
6
9
8
7
10
C8
10uF
6.3V
ONB FAULTB
INA
IN
INB
ONA FAULTA
U1
2
2
TP1
C9
0.01uF
16V
Reset
R1
C7
5.6uF
16V
100K
1/10W
TEST_POINT
Red
C10
0.1uF
16V
+3.3V
J7
2
HDR_1x2
ZERO
0.1W
+3.3V
FB4
F-BEAD
500mA / 0.1DCR
R6
C3
1.0uF
16V
Date:
Size
C
+
C4
150uF
<Voltage>
10V
P1
1
Wednesday, November 16, 2005
Document Number
SCH-7065AZ
C11
0.1uF
16V
VBUS
DD+
ID
GND
SHIELD1
SHIELD2
SHIELD3
SHIELD4
MINI-AB
FB2
F-BEAD
500mA / 0.1DCR
1
2
3
4
5
6
7
8
9
FB1
F-BEAD
500mA / 0.1DCR
Sheet
2
of
2
3930 East Ray Road
Suite 200
Phoenix, Arizona 85044
480-759-0200
C12
0.1uF
16V
Keep ferrite beads close
to mini AB connector
0 = OTG Device
1 = Host
J7
1
1
Rev
A
A
B
C
D
2.8
Circuit Diagrams utilizing SMSC Products Are Included As A Means Of Illustrating
Typical Semiconductor Applications: Consequently Complete Information
Sufficient For Construction Purposes Is Not Necessarily Given. The Information
Has Been Carefully Checked And Is Believed To Be Entirely Reliable. However, No
Responsibility Is Assumed For Inaccuracies. Furthermore, Such Information Does
Not Convey To The Purchaser Of The Semiconductor Devices Described Any
License Under The Patent Rights Of SMSC Or Others. SMSC Reserves The Right
To Make Changes At Any Time In Order To Improve Design And Supply The Best
Product Possible.
EVB-USB3300-XLX User Manual
Schematic Diagram
Figure 3 EVB-USB3300-XLX Schematic
Revision 0.4 (06-29-07)
EVB-USB3300-XLX User Manual
Revision 0.4 (06-29-07)
SMSC EVB-USB3300-XLX
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