Download sim system integration module reference manual

5.10 Bus Arbitration
MCU bus design provides for a single bus master at any one time. Either the MCU or
an external device can be master. Bus arbitration protocols determine when an external device can become bus master. Bus arbitration requests are recognized during
normal processing, during HALT assertion, and when the CPU has halted due to a
double bus fault.
The bus controller in the MCU manages bus arbitration signals so that the MCU has
the lowest priority. Systems that include several devices that can become bus master
require external circuitry to assign priorities to the devices, so that when two or more
external devices attempt to become bus master at the same time, the one having the
highest priority becomes bus master first.
External devices that need to obtain the bus must assert bus arbitration signals in the
following sequence:
• An external device asserts the bus request signal (BR).
• The MCU asserts the bus grant signal (BG) to indicate that the bus is available.
• An external device asserts the bus grant acknowledge (BGACK) signal to indicate
that it has assumed bus mastership.
BR may be issued any time during a bus cycle or between cycles. BG is asserted in
response to BR. To guarantee operand coherency, BG is only asserted at the end of
operand transfer. Additionally, BG is not asserted until the end of an indivisible readmodify-write operation (when RMC is negated), on CPU32-based MCUs. (CPU16based MCUs do not provide an RMC signal.)
If more than one external device can be bus master, required external arbitration must
begin when a requesting device receives BG. An external device must assert BGACK
when it assumes mastership and must maintain BGACK assertion as long as it is bus
master.
Two conditions must be met for an external device to assume bus mastership. The device must receive BG through the arbitration process, and BGACK must be inactive,
indicating that no other bus master is active. This technique allows processing of bus
requests during data transfer cycles.
BG is negated a few clock cycles after an external device asserts BGACK. However,
if bus requests are still pending after BG is negated, the MCU asserts BG again within
a few clock cycles. This additional BG assertion allows external arbitration circuitry to
select the next bus master before the current master has released the bus.
Figure 5-36 is a flow chart of bus arbitration for a single device.
SIM
REFERENCE MANUAL
EXTERNAL BUS INTERFACE
MOTOROLA
5-47