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S3CC410 (Preliminary Spec) CalmMAC2424 ESFTD – Double Shift by Barrel Shifter Format: ESFTD asr,asa Operation: SG ← SG | (asr<<asa) This instruction shifts the value of 24-bit asr values by the amount of 7-bit asa. If the value of asa is positive, left shift operation is performed, and if the value of asa is negative right shift operation is performed. The 24-bit shifted result is ORed with previous SG register value ,and then stored into SG register. Flags: C: set if last shifted out bit is 1. Reset if not. Unchanged when shift amount is 0. Z: set if SG result is zero. Reset if not. VS: Reset. N: MSB of SG result. Notes: – Examples: ESFTD A, B ESFTD SI,SA # of Words: 1 23-125
