1
Download CPU Design
Transcript
00-173 C06 pp3 250 10/25/00 CHAPTER 6 11:10 AM Page 250 CPU DESIGN Table 6.6 State generation for a Relatively Simple CPU State Function State FETCH1 T0 JMPZY1 FETCH2 T1 JMPZY2 FETCH3 T2 JMPZY3 NOP1 INOP ∧ T3 ILDAC ∧ T3 JMPZN1 ILDAC ∧ T4 ILDAC ∧ T5 JPNZY1 ILDAC ∧ T6 ILDAC ∧ T7 ISTAC ∧ T3 JPNZY3 LDAC1 LDAC2 LDAC3 LDAC4 LDAC5 STAC1 STAC2 STAC3 STAC4 STAC5 MVAC1 MOVR1 JUMP1 JUMP2 JUMP3 JMPZN2 JPNZY2 JPNZN1 JPNZN2 Function IJMPZ ∧ Z ∧ T3 IJMPZ ∧ Z ∧ T4 IJMPZ ∧ Z ∧ T5 IJMPZ ∧ Z′ ∧ T3 IJMPZ ∧ Z′ ∧ T4 IJPNZ ∧ Z ∧ T3 IJPNZ ∧ Z ∧ T4 IJPNZ ∧ Z ∧ T5 IJPNZ ∧ Z′ ∧ T3 IJPNZ ∧ Z′ ∧ T4 IADD ∧ T3 ISTAC ∧ T4 ISTAC ∧ T5 ADD1 ISTAC ∧ T6 ISTAC ∧ T7 IMVAC ∧ T3 INAC1 IMOVR ∧ T3 IJUMP ∧ T3 OR1 XOR1 IOR ∧ T3 IXOR ∧ T3 IJUMP ∧ T4 IJUMP ∧ T5 NOT1 INOT ∧ T3 SUB1 CLAC1 AND1 ISUB ∧ T3 IINAC ∧ T3 ICLAC ∧ T3 IAND ∧ T3 Finally, we generate the ALU control signals in the same manner. For example, ALUS1 ADD1 ∨ SUB1 ∨ INAC1 and ALUS4 SUB1 ∨ INAC1. The remaining control signals are left as exercises for the reader. 6.3.7 Design Verification To verify the design of this CPU, the designer should prepare a trace of the execution, as was done for the Very Simple CPU. For the JMPZ and JPNZ instructions, the trace should show the execution under all possible circumstances, in this case Z 0 and Z 1. This is left as an exercise for the reader. To perform the trace, students may use the RS-CPU simulator package. This package is a Java applet that can be run using any standard Web browser with Java enabled. Using this package, the reader can enter a program and step through the fetch, decode, and execution of the individual instructions. The package may be accessed at the textbook’s companion Web site, along with its instructions.
