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To accommodate these parameters, the sample counter is 16 bits
wide. The sample loop time is set to
about 2.5 ps. Terminal count is
reached after an interval of 10 ms, and
in the absence of transitions, this is
the overflow count. To save space for
the decoding algorithm, the sample
routine listing is not presented here.
However, the BAR. Z I P archive is
available on the Circuit Cellar BBS and
contains this and related modules. (If
you do decide to examine the sampling
routine, remember that it is set up to
run on a 25MHz DS80C320.)
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DECODING 39
In keeping with my goal of providing a simplified firmware presentation, I will demonstrate the essence of
Code 39’s decoding algorithm. This is
in fact an implementation of the logic
described in the Automatic Identification Manufacturers (AIM) Reference
Decode Algorithm for USS-39.
At this point, it would be useful to
make a couple of general observations.
This decode algorithm presents the
basic steps for deciphering a Code-39
symbol. The underlying logic is sound,
but incomplete. As the AIM specification points out, you would undoubtedly want to add secondary checks for
acceleration, intercharacter gap, and
absolute dimensions for any serious
application. You should also realize
that these secondary checks and
balances can generate as much code as
the algorithm. As a result, the logic of
the algorithm can become totally
obscured.
The other relevant issue falls
smack in the realm of advancing the
state of the art. It’s not unusual to
encounter bar-code labels that don’t
meet specifications. This may be due
to dimensional-tolerance problems,
poor print-contrast ratio, inadequate
quiet zone, and suchlike. If some
clever programmer comes up with a
superior algorithm which consistently
reads deficient labels (one that doesn’t
result in an increase of missed decodes, of course), this has an unsettling
effect on the status quo. These things
happen and illustrate the fact that
meeting the specification should be
just a starting point.
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#129
Semiconductor’s new 8051-compatible DSSOC320
With Its 2X clock speed [25MHz] end 3X cycle efficiency, an
instruction can execute in 160”s: a” 8051 equivalent speed
of 62.5MHz’!! Equally wnpress~ve is the T-l 28’s high-speed NVRAM
interface. Any of the 128K RAM may be programmed directly from a PC fde through the console:
eliminating EPROMs and associated tools. Program Development has “ever bee” faster or more
convenient, eve” with the finest EPROM emulator.The T-128 features PORT 0 btas and EA-select for
OS87C520 upgrade.
BASIC520
*Dallas
Semiconductor’s ffi8oc320
‘Modified BASG52 lntemreter IBASICNow Fast Enough for N.&v Appl&ians
*Stack BASIC Pmgrams and Autorun
tiLL ASM Routines for Maximum Speed
l 3W% more efficient than tie 8051
*Three 1 &bit Timer/Caunters
*13 klt&wupts [6 Ext, 7 lntl
*A second 1 E-bit Data Pointer
9384 Bytes of internal RAM
*Programmable Watchdog
l Brownout Protectron
*Power-Fall Reset/interrupt
.PowerOn Reset
*Fully supported by Franklin C51
*Three a-hi Parallel Ports
l
.l”sn-uC00” cycle 121 ns
‘a.25 MIPS
l 8051 equivalent 82.5 MHz
*Internal 16K ROM/l K SRAM
M
*Two Full-Duplex RS232 Serial Ports
*Decoded Device I/O Strobes
*SOPin Bus Connector
UPGRADE
l OS87C520 processor 133MHzl
Entire 128K Memory Map
populated with fasast NV?=tAM
[64K DATAt64K CODE)
‘All memory pmgrammed on-board
rPartmo”able as
ccGE,‘DATA/C3vERAHl
Gde !$ace IS W”te+=mtectable
Q.atwfheArt Data PTvtacbon
Camps Rsady to Run
with pwsr adqterhble amrmbly.
Ineludas utility dishetts with
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in OTV.
Issue #54 January 1995
113