Download Laboratory assignment 1

Contents
1 Quartus project, combinatorial logic and functional simulation
1.1 Switches and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 7-segment decoder with functional simulation . . . . . . . . . . . . . . .
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2 Synchronous process
2.1 4-bit counter and push button . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Edge detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction
This lab assignment contains two parts. In the first part you will implement a simple
design to connect the onboard toggle switches to the onboard LEDs, and a 7-segment
decoder to show the value of the first 4 toggle swithces on the 7-segment display. To
verify the correct behaviour of the 7-segment decoder you will simulate the design using
a test bench setup which has already been prepared for you.
For the second part, you will implement a 4-bit counter that will be used as input to
the 7-segment decoder. The counter will be synchronous to the onboard 50 MHz crystal,
and a push butten will be used to activate the counter. A push button will be used to
increment the counter. To verify the correct behaviour of the 4-bit counter you will again
use an already prepared test bench setup.
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1.1
Quartus project, combinatorial logic and functional
simulation
Switches and LEDs
The purpose of this first assignment is to learn how to connect simple input and output
devices to an FPGA chip and implement a circuit that uses these devices. We will use
the switches on the DE1-SoC[1, 2] board as inputs to the circuit and we will connect
the outputs to the light emitting diodes (LEDs). The DE1-SoC board provides 10 toggle
switches, called SW9-0, which can be used as inputs to a circuit, and 10 red LEDs, called
LEDR9-0, that can be used to display output values. Listing 1 shows a simple VHDL
description where you will need to insert the appropriate statement in order to connect
the switches to the LEDs. Since there are 10 switches and 10 LEDs it is convenient to
represent them as arrays in the entity description of the VHDL code.
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