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Peripheral Memory-Mapped Registers Table 8–8. C5402 Peripheral Memory-Mapped Registers (Continued) Address (Hex) Name Description 3E–3F ––– Reserved 40 DRR21 41 DRR11 42 DXR21 43 DXR11 44–47 ––– 48 SPSA1 49 SPSD1 4A–53 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ––– McBSP1 data receive register 2 McBSP1 data receive register 1 McBSP1 data transmit register 2 McBSP1 data transmit register 1 Reserved McBSP1 serial port sub-bank address register (See Table 8–11 on page 8-17.) McBSP1 serial port sub-bank data register (See Table 8–11 on page 8-17.) Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 54 DMPREC DMA channel priority and enable control register 55 DMSA DMA sub-bank address register (See Table 8–12 on page 8-18.) 56 DMSDI DMA sub-bank data register with sub-bank address auto-increment (See Table 8–12 on page 8-18.) 57 DMSDN DMA sub-bank data register (See Table 8–12 on page 8-18.) 58 CLKMD Clock mode register ––– Reserved 59–5F 8-12 On-Chip Peripherals SPRU131G
