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OPB IPIF/LogiCore v3 PCI Core Bridge (v1.00c)
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With FIFOs includes asynchronous FIFOs with burst transfer support and backup capability for retrying transfers
as needed.
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Synchronization circuits for signals that cross time-domain boundaries
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PCI and OPB clocks can be totally independent
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Responding to the PCI latency timer
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Completing posted write operations prior to initiating new operations
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Signal set required for integrating a PCI bus arbiter in the FPGA with the PLB/PCI bridge is available at the top-level of
the PLB/PCI bridge module. The signal set includes PCLK, RST_N, FRAME_I and IRDY_I.
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Supports PCI clock generated in FPGA
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Parameterized control of IO-buffer insertion of INTR_A and REQ_N IO-buffers
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Supports all PCI commands supported by the v3 core with the following exceptions:
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The interrupt acknowledge command will be supported in future releases of the core and will be only for OPB
masters to execute the command while being ignored when executed by a remote PCI agent.
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The special cycle command will be supported in future releases of the core.
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I/O read and I/O write commands are supported only for OPB master read and writes of PCI I/O space as
designated by its associated memory designator bits of the generics. All memory space on the OPB-side is
designated as memory space in the PCI sense, hence, I/O commands can not be used to access memory on the
OPB-side.
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Configuration read and writes are supported (including self-configuration transactions) only when upper word
address lines are utilized for IDSel lines. The configuration read and write commands are automatically executed
by writing to the configuration data port register. Data in the configuration address port register and the
configuration bus number/subordinate bus number register is used in execution of the configuration transaction per
PCI 2.2 specification.
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Memory read line command is not supported mainly because the OPB does not have direct support of this type of
line wrapping.
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Memory write invalidate is not supported where the v3 core is a target because the low utility of having memory on
the OPB side with a cached counterpart and memory controller on the PCI side of the bridge. The v3 core does not
support this command when it is an initiator.
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Programmable enabling of the bridge feature to inhibit one or any number of the four transfer types when an error is
detected.
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Supports up to 6 OPB devices with unique memory OPB memory space
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Supports up to 3 PCI devices with unique memory PCI memory space. The v3 core supports up to 3 PCI BAR.
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Each device has the following generics: OPB BAR, length, prefetchability, Big Endian to Little Endian translate, and
offset for mapping OPB address space to PCI address space.
Each device has the following generics: PCI BAR, length, prefetchability, memory designator, Little Endian to Big
Endian translate, and offset for mapping PCI address space to OPB address space
Registers include
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Interrupt and interrupt enable registers at different hierarchal levels
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Reset
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Prefetch override
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Bridge and v3 Core Transaction Status
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Inhibit Transfers on Error
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OPB Mst Address Definition
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OPB Mst Read and Write Addresses
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Address range decode for supported BAR, length, and prefetch operation
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OPB-side Interrupts include
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OPB Master Read SERR and PERR
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OPB Master Read Target Abort
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OPB Master Write SERR and PERR
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