Download HUNT ENGINEERING HERON

TABLE OF CONTENTS
INTRODUCTION.......................................................................................................... 6
PHYSICAL LOCATION OF ITEMS ON THE HERON-FPGA9............................ 8
GETTING STARTED ................................................................................................... 9
STANDARD INTELLECTUAL PROPERTY (IP) ............................................................................................. 9
MODULE FEATURES ............................................................................................... 10
USER PROGRAMMABLE FPGA WITH EMBEDDED POWER PC ................................................................ 10
SERIAL CONFIGURATION OF THE USER FPGA ....................................................................................... 10
USER FPGA BOOT ROM ..................................................................................................................... 10
CLOCKING OF THE FPGA ...................................................................................................................... 12
HERON FIFOS .................................................................................................................................... 13
DDR SDRAM ...................................................................................................................................... 14
FLASH MEMORY ................................................................................................................................. 14
DIGITAL I/O........................................................................................................................................... 15
MODULE AND CARRIER ID .................................................................................................................... 15
GENERAL PURPOSE LEDS ..................................................................................................................... 15
DONE LEDS .......................................................................................................................................... 15
USB ...................................................................................................................................................... 15
GETTING STARTED ON YOUR FPGA DESIGN ................................................. 17
WORKING THROUGH EXAMPLE 1........................................................................................................... 18
Preparing ISE .................................................................................................................................. 18
Copying the examples from the HUNT ENGINEERING CD........................................................... 19
Opening the Example1 Project........................................................................................................ 19
The Project's Functional Parameters .............................................................................................. 19
Setting up the Configuration Package............................................................................................. 20
User Timing Constraints.................................................................................................................. 21
Creating the Bitstream for Example1 .............................................................................................. 22
Simulating the Complete Design ..................................................................................................... 23
MAKING YOUR OWN FPGA DESIGN................................................................... 24
USER_AP INTERFACE ............................................................................................................................ 24
HARDWARE INTERFACE LAYER ............................................................................................................. 29
IMPORTANT!.......................................................................................................................................... 29
OTHER EXAMPLES ................................................................................................................................. 30
HOW TO MAKE A NEW DESIGN ............................................................................................................. 30
Inserting your own Logic................................................................................................................. 31
Top-level Fine Tuning (using other special IO pins)....................................................................... 31
User Timing Constraints.................................................................................................................. 31
HINTS FOR FPGA DESIGNS ................................................................................................................... 32
Use of Clocks ................................................................................................................................... 32
Possible Sources of Clocks .............................................................................................................. 33
Flow Control.................................................................................................................................... 33
Pipeline Length or “latency” .......................................................................................................... 34
I/O FROM THE FPGA............................................................................................................................. 34
DSP WITH YOUR FPGA......................................................................................................................... 34
SOFTWARE................................................................................................................. 35
FPGA DEVELOPMENT TOOL.................................................................................................................. 35
DESIGN FILES FOR THE FPGA ............................................................................................................... 35
GENERATING DESIGN FILES................................................................................................................... 36
Files for HERON Utility (*.rbt) ....................................................................................................... 36
Files for PROMs (*.mcs) ................................................................................................................. 37
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HUNT ENGINEERING HERON-FPGA9 USER MANUAL