Download RMAP User Manual - ESA Microelectronics Section

SpaceNet – RMAP IP
VHDL User Manual
The memory structures available in the VHDL code are listed in Figure 9-1.
Figure 9-1 Synchronous and asynchronous dual port memory blocks
A description of each VHDL file is given in Table 9-7.
VHDL file
mem/mem_cell.vhd
Description
Register with write enable intended for memory block
build with flip-flop banks.
sync_fifo/sync_memblock.vhd
Single clock, dual port memory built from mem_cell
blocks.
sync_fifo/sync_memblock_bram.vhd
Single clock, dual port memory using Xilinx BRAM
components. Uses RAMB4_S16_S16 which is
compatible with Virtex and Spartan designs.
sync_fifo/sync_memblock_fpga_memory.vhd
Single clock, dual port memory using VHDL code to
instantiate technology memory blocks.
async_fifo/async_memblock.vhd
Two clock, dual port memory build from mem_cell blocks
and with additional asynchronous output filtering to the
memory output register.
async_fifo/async_memblock_and.vhd
AND gate for output data multiplexer.
async_fifo/async_memblock_dataena.vhd
Output data multiplexer build from AND gates and OR
gates.
62
© University of Dundee