Download DMP40, DMP40S2

Instruction set for the HBM Interpreter ➝ Communication
G-46
*PRE
Parallel Poll Enable Register
Input of PRE bit mask
Syntax:
*PRE p1(x)
Parameters:
p1
Decimal equivalents of 16-Bit PRE register
0 – 65 535
Effect:
This command sets the PRE register bits. Each bit in this
register is assigned to a bit in the status byte register. If a bit
from the status byte register and the associated bit from the
parallel poll enable register are set, in the event of a parallel
poll query, the parallel poll response set with the command
PPM is output (see also *IST? command).
Initial status:
65 535 (free), i.e. all available status changes in the STB
register bring about a response in the event of a parallel poll
query.
Response:
Example 1:
Example 2:
Operation with computer or terminal
Acknowledgment
Meaning
0
Command has been executed
?
Error
*PRE0(x)
0(y)
No response in event of parallel poll query
*PRE64(x)
0(y)
The DMP40 should answer in the event of a parallel poll
query, if the MSS bit (master summary status) is set.