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B • PROCESSOR GATEWAY DDT SCHEDULLER nnn PHASES BEHIND The PGDCP program is (nnn) phases behind in processing the scheduled DDT tables. This message appears when 10 phases behind and at each additional multiple of 10. This can be caused by too many DDT table entries or the total number of scheduled DDTs and ACP requests exceed the system limit. • PROCESSOR GATEWAY SCHEDULED DDT ERROR #nnn ON TAG nnnnnnnn pppppppp (sss) The PGDCP program received the Data Access Status code (nnn) that indicates an error when accessing the identified point.parameter (nnnnnnnn.pppppppp (sss)) for a scheduled DDT. An error message is not repeated for a given point.parameter until an intervening nonerror status return for that point.parameter is received. For named DDTs these codes are returned to the ACP program with the data. The Data Access Status codes are defined in Appendix A of this manual. • PROCESSOR GATEWAY DSAERR xxx AT REL nnnnn The PGDCP program received the error code (xxx) when accessing bulk storage. The relative location (nnnnn) is the program location where the request was made. When a bulk error is encountered, the PGDCP program aborts all requests and terminates execution. • PROCESSOR GATEWAY DATA LINK #nn FAILURE 00x The PGDCP program is unable to communicate over data link (nn). The failure reasons (00x) are: 001 = Response message timeout 002 = Message confirmation output error 003 = Control block output error 004 = Message input error 005 = Scheduler behind error • PROCESSOR GATEWAY DATA LINK #nn RESTART The PGDCP program has received a restart message for data link (nn). • PROCESSOR GATEWAY V3.X::: DDT SCHEDULER TURNED ON - CIU #n The PGDCP program has received the scheduled DDT turn on message from CG number (n). V3.X indicates the present version of the Processor Gateway software Processor Gateway User Manual B-2 8/95