Download E1430A VXI ADC User`s Guide

HP E1430A User’s Guide
The Control Registers
Trigger Setup Register
This register controls when the module initiates a trigger event. The module
can generate a trigger only when it is in the Start measurement state and the
SYNC line is high (indicating that all modules are ready for a trigger).
The following paragraphs describe the fields of the Trigger Setup register. The
register is summarized in the table below.
Trigger Setup register bit definitions (Write Address 1AH)
B it
p o sitio n
0-7
8
9
10
11
12
15-13
F ie ld la b e l
TRIGLEVEL
AUTOTRIG
SLOPE
TRIG_INTERNAL
TRIGSOURCE
TRIGOFF
D e scr ip t io n
Sets trigger threshold (n)
(0) Activates automatic triggering (free run)
Selects positive or negative trigger slope
Selects internal or external trigger
Selects between two internal trigger sources
Disables trigger generation by this module
Unused
TRIGLEVEL
TRIGLEVEL is an 8-bit unsigned integer which sets the trigger threshold level
for internal trigger sources.
For the magnitude trigger source (TRIGSOURCE bit = 1):
threshold level = R×2(n−237)/16
For the ADC trigger source: (TRIGSOURCE bit = 0)
threshold level = R(n/128−1)
where R is the input range ADC clipping level and n is the number specified by
TRIGLEVEL. For the lowest three ranges, R is negative due to the inverting
amplifier used on those ranges (see the ‘‘Analog Setup Register’’ section in this
chapter).
There is a fixed trigger hystersis to prevent triggering on the wrong slope in the
presence of noise. The hystersis is equivalent to two counts of n. A setting of
n<2 with positive slope or n>253 with negative slope would never allow triggers
to occur.
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