Download E1430A VXI ADC User`s Guide

HP E1430A User’s Guide
Block Diagram and Description
Data Output
There are two ways to output data from the HP E1430A: by way of the VXI
backplane or by way of the local bus.
To use the VXI backplane, the HP E1430A can be programmed so that the
output of the FIFO is sent to the Send Data register. Each 64-bit portion of the
FIFO memory is sent to the 16-bit register as four separate words. The register
can then be read by any controller compatible with the VME standard.
Maximum data flow is about 2 MB/s.
The local bus allows data transfers over a high speed 8-bit ECL bus to an
adjacent module (to the right) in the VXI mainframe. Multiple adjacent
HP E1430A modules can send data to one signal processor module. The signal
processor must be one which supports the Hewlett-Packard ECL local bus
protocol, such as the HP E1485A/B. In addition to higher speed (up to 40
MB/s), the local bus has the advantage that data can be output at the same time
that control signals are being sent over the VXI backplane.
In both of the data output modes, the samples must be read out sequentially,
beginning with the sample following the trigger.
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