1
Download HSM550 Technical Reference
Transcript
11 P9 HEADER 4X1 MEM & CLOCK P10 HEADER 4X1 VLITH VBU VCC TP3 100 CR2032H IN HOLDER Rin R9 MAX703CSA R10 VRAW PFW_L 390k 10.0k 1% INT0 NC RST_L LOADPB_L 3 10k C9 VCC R12 PFI TRIPS AT 1.25V Rp R11 33.2k 1% MCU JP25 VPFI 100nF VCC 4 VBU 2M GNDD R25 RST_L U6 TP4 R26 B1 C10 P17 DJ-005-B S1 ! 100nF S2 6 TO 12 V INPUT P16 PHOENIX2 100 D3 1nF C44 R31 U17 0.10 1% 1/2W C46 F1 Si4412DY 100pF 100nF 5V 1A MAX TPS 100uF 10V VCC SENSE C49 32.4k 1% 3 4 5 8 VCC 29.7uH 1A TPS 100uF 10V 10.0k 1% D5 LTC1624 CMSH2-40 L3 R34 R33 OTHER SHEETS C48 22uF 35V LOW ESR 470pF C47 10k C43 D4 C42 R32 C45 22uF 35V LOW ESR VRAW CMSH2-40 SMBJ24M 600W VINP 9 10 FOOT1 SYSTRONIX FOOT2 FOOT3 FOOT4 Systronix Inc Proprietary Data Use and/or disclosure is governed by the statement on the title page of this document. HSM550 DEVELOPMENT/EVAL BOARD POWER & RESET A.01 Mon Jun 21, 1999 hsm550a02.sch 11 B Boyes 11
