Download Cycle Stealing Mode - Renesas Electronics

SH7216/SH7239/SH7231 Groups
5.
5.1
Data Transfer Within On-Chip RAM (Cycle Stealing Mode) Using the DMAC
Software
Operation Overview
The sample program writes a pattern to the transfer source memory area in advance and after setting up the DMAC, it
starts an auto-request transfer to the transfer destination memory area by enabling DMAC operation in software.
Table 5.1 lists the DMAC settings. Figure 5.1 presents an overview of this operation.
Table 5.1 DMAC Settings
Item
Channel used
Transfer data length
Transfer count
Address mode
Transfer request
Bus mode
Priority
Interrupt
Description
CH0
Long word (4 bytes)
128 transfers (128 transfers × 4 byte data length = 512 bytes of data)
Dual address mode
Auto-request
Cycle stealing mode (normal mode)
Channel priority fixed mode
Interrupts disabled.
DMAC
SAR
Internal RAM
Transfer source
address
H'FFF81000
512 bytes of data
DAR
DMA transfer
Transfer destination
H'FFF82000
address
512 bytes of data
Legend:
SAR: Source address register
DAR: Destination address register
Figure 5.1 Operation Overview
R01AN1262EJ0100 Rev.1.00
Dec. 07, 2012
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