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MC68EC040 REV2.2 (11/02/99)
Figure B-3. MC68EC040 Functional Signal Groups
MC68EC040 contains two independent ACUs, one for instructions and one for data. Each
ACU allows memory selections to be made requiring attributes particular to peripherals,
shared memory, or other special memory requirements. The following paragraphs describe
the ACUs and the access control registers contained in them.
B.3.1 Access Control Registers
Each ACU has two independent access control registers (ACRs). The instruction ACU contains the instruction access control registers (IACR0 and IACR1). The data ACU contains
the data access control registers (DACR0 and DACR1). Both ACRs provide and control status information for access control of memory in the MC68EC040. Only programs that execute in the supervisor mode using the MOVEC instruction can directly access the ACRs.
The 32-bit ACRs each define blocks of MC68EC040:address space for access control.
These blocks of address space can overlap or be separate, and are a minimum of 16
Mbytes. Three blocks are used with two user-defined attributes, cachability control and
optional write protection. The ACRs specify a block of address space as serialized noncachable for peripheral selections and as write-through for shared blocks of address space in
multi-processing applications. The ACRs can be configured to support many embedded
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M68040 USER’S MANUAL
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