Download VS1005g Datasheet

VS1005g Datasheet
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VS1005g Debugger
VS1005G DEBUGGER
IN
AR
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VS1005g has a hardware debugger which uses common Joint Test Action Group (JTAG) interface. The JTAG pins are in hardware debug mode when the dbgmode pin is pulled high. This
enables the JTAG pins to access Test Acess Port (TAP) controller and swithes clocks to debug
mode.
VS1005g Hardware Debuger Pins
Package pin Description
31 Test mode select
32 Test data in
33 Test data out
34 Test clock
35 Debug interrupt
61 JTAG debug mode enable
Name
tms
tdi
tdo
tck
dbgreq
dbgmode
PR
EL
IM
Debug functions are controlled with JTAG DR (data) and IR (instruction) registers which can be
written and read in predefined JTAG states. JTAG state machine is shown in Figure 28.
Figure 28: JTAG state machine
TAP function is selected by writing a special 4-bit instruction to IR register. Additionally to debug
functions, some common JTAG functions are supported.
Version: 0.63, 2014-12-19
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