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MPC5510EVB User Manual
Revision 1.0 – September 2007
Note – This user manual is written for EVB PCB revision E
MPC5510EVB User Manual Rev 1.0
Sept 2007
Revision History:
Revision
0.1
Date
March 2007
Author
A. Robertson
1.0
September 2007
A. Robertson
Comment
Initial Release, RevA PCB’s only. Excludes BOM
and daughter card instructions.
Production EVB release. Includes BOM and
schematics for EVB, 144QFP, 176QFP and
208BGA daughter cards
Information in this document is provided solely to enable system and software implementers to use Freescale
Semiconductor products. There are no express or implied copyright licenses granted hereunder to design
or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale
Semiconductor reserves the right to make changes without further notice to any products herein. Freescale
Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor
data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor
the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as
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Learn More: For more information about Freescale products, please visit www.freescale.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, 2007; All Rights Reserved
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INDEX
1.
INTRODUCTION..................................................................................................................................................... 1
1.1
MODULAR CONCEPT........................................................................................................................................... 1
2.
EVB FEATURES ...................................................................................................................................................... 2
3.
CONFIGURATION .................................................................................................................................................. 3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.2
3.2.1
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.5
3.5.1
3.5.2
3.6
3.7
3.8
3.9
3.10
3.11
4.
POWER SUPPLY CONFIGURATION ....................................................................................................................... 4
Power Supply Connectors............................................................................................................................. 4
Power Switch (SW6) ..................................................................................................................................... 4
Regulator Power Jumpers (J42, J44, J45 and J46) ...................................................................................... 5
Power Status LED’s and Fuse ...................................................................................................................... 5
SBC Power Jumper (J41).............................................................................................................................. 5
MCU Supply Routing and Jumpers (J21, J25, J27, J29, J30, J33, J34, J36, J37, J38)............................... 6
EVB Circuitry Power Domains..................................................................................................................... 8
MCU CLOCK CONTROL (J39 AND J40)............................................................................................................... 9
Clock Selection ............................................................................................................................................. 9
RESET CONTROL (JUMPERS J17, J19, J20, SW1) .............................................................................................. 10
Reset LEDs.................................................................................................................................................. 10
Reset Buffering Scheme............................................................................................................................... 11
Reset Boot Configuration (J19) .................................................................................................................. 12
DEBUG CONFIGURATION (J24, J28, J31, J31B)................................................................................................ 12
TCLK Configuration ................................................................................................................................... 12
Reset Buffering............................................................................................................................................ 12
PFO Selection ............................................................................................................................................. 13
Vendor I/O Configuration........................................................................................................................... 13
Debug Connector Pinouts........................................................................................................................... 14
EXTERNAL MEMORY CONFIGURATION............................................................................................................. 15
Memory Power Control (J22, J32)) ............................................................................................................ 16
Port Size Select and Chip Select Control (J35)........................................................................................... 16
CAN CONFIGURATION (J3, J4, J7).................................................................................................................... 17
RS232 CONFIGURATION (J9, J10, J11) ............................................................................................................. 18
LIN CONFIGURATION (J1, J2, J5, J6) ................................................................................................................ 19
FLEXRAY CONFIGURATION (J12, J13, J14, J15, J16, J18) ................................................................................ 20
LED DOT MATRIX (J23) .................................................................................................................................. 22
TERMINATION RESISTOR CONTROL (J26) ......................................................................................................... 23
DAUGHTERCARDS .............................................................................................................................................. 24
4.1
INSTALLATION AND REMOVAL INSTRUCTIONS ................................................................................................. 24
4.2
DAUGHTERCARD CONFIGURATION ................................................................................................................... 25
4.2.1
External VREG Configuration .................................................................................................................... 25
4.2.2
Main Clock Configuration .......................................................................................................................... 25
4.2.3
32Khz Clock Configuration ........................................................................................................................ 26
4.2.4
CLKOUT Impedance Matching Control..................................................................................................... 27
4.2.5
Power LED ................................................................................................................................................. 27
5.
MCU PIN USAGE MAP......................................................................................................................................... 27
6.
DEFAULT JUMPER SUMMARY TABLE ......................................................................................................... 28
7.
USER CONNECTOR DESCRIPTIONS .............................................................................................................. 30
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Port A / ADC (Connector P16, RV1 and J8)............................................................................................... 30
Port B / ADC / SCI (P30)............................................................................................................................ 30
Port C / ADC / SCI (P24) ........................................................................................................................... 31
Port D / CAN / SCI / SPI (P15)................................................................................................................... 31
PortE / SPI / eMIOS / EIM (Connector P31).............................................................................................. 31
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Port F / EIM (Connector P17).................................................................................................................... 32
7.1.6
7.1.7
Port G / EIM (Connector P25) ................................................................................................................... 32
7.1.8
Port H / ADC / API / EIM (Connector P29) ............................................................................................... 32
7.1.9
Port J / EIM / SPI (Connector P23)............................................................................................................ 33
7.1.10
Port K / EXTAL32 / XTAL32 (Connector P33) ...................................................................................... 33
7.2
PROTOTYPING AREA AND USER LED’S / SWITCHES ......................................................................................... 34
8.
DAUGHTER CARD CONNECTORS (P9, P22).................................................................................................. 35
APPENDIX
Schematics and Bill of materials for EVB and Daughtercards
Index of Figures and Tables
FIGURE 1-1 MODULAR CONCEPT – EVB AND MCU DAUGHTER CARDS ............................................................................. 1
FIGURE 3-1 EVB FUNCTIONAL BLOCKS .............................................................................................................................. 3
FIGURE 3-2 2.1MM POWER CONNECTOR .............................................................................................................................. 4
FIGURE 3-3 2-LEVER POWER CONNECTOR ........................................................................................................................... 4
FIGURE 3-4 POWER SUPPLY ROUTING.................................................................................................................................. 6
FIGURE 3-5 EVB CLOCK SELECTION ................................................................................................................................... 9
FIGURE 3-6 EVB RESET BUFFERING SCHEME .................................................................................................................... 11
FIGURE 3-7 MPC5510 JTAG / ONCE CONNECTOR ........................................................................................................... 14
FIGURE 3-8 EXTERNAL MEMORY SUBSYSTEM ................................................................................................................... 15
FIGURE 3-9 CS AND PORT-SIZE CONTROL JUMPER ............................................................................................................ 16
FIGURE 3-10 CAN PHYSICAL INTERFACE CONNECTOR ..................................................................................................... 17
FIGURE 3-11 RS232 PHYSICAL INTERFACE CONNECTOR ................................................................................................... 18
FIGURE 3-12 LIN PHYSICAL INTERFACE CONNECTOR ....................................................................................................... 19
FIGURE 3-13 LED MATRIX CONTROL ................................................................................................................................ 22
FIGURE 4-1 DAUGHTER CARDS .......................................................................................................................................... 24
FIGURE 4-2 DAUGHTER CARD REMOVAL........................................................................................................................... 24
FIGURE4-3 DAUGHTERCARD CLOCK SELECTION ............................................................................................................... 25
FIGURE4-4 DAUGHTERCARD 32KHZ CLOCK SELECTION ................................................................................................... 26
TABLE 3-1 REGULATOR POWER JUMPERS ............................................................................................................................ 5
TABLE 3-2 SBC POWER JUMPERS ........................................................................................................................................ 5
TABLE 3-3 MCU POWER SUPPLY JUMPERS ......................................................................................................................... 7
TABLE 3-4 VDDE[1..3] PAD GROUPINGS ............................................................................................................................ 8
TABLE 3-5 POWER SUPPLY DISTRIBUTION ........................................................................................................................... 8
TABLE 3-6 CLOCK SOURCE JUMPER SELECTION .................................................................................................................. 9
TABLE 3-7 LVI MONITOR THRESHOLD VOLTAGES ............................................................................................................ 10
TABLE 3-8 LVI CONTROL JUMPERS ................................................................................................................................... 10
TABLE 3-9 RESET-OUT CONTROL JUMPER ......................................................................................................................... 11
TABLE 3-10 BOOTCFG CONTROL .................................................................................................................................... 12
TABLE 3-11 ONCE / NEXUS TCLK TERMINATION CONTROL ......................................................................................... 12
TABLE 3-12 JTAG / NEXUS TARGET RESET ROUTING ..................................................................................................... 12
TABLE 3-13 PFO EVTI / R/W FUNCTION SELECTION ........................................................................................................ 13
TABLE 3-14 VENDOR I/O2 DRIVE CONTROL ...................................................................................................................... 13
TABLE 3-15 NEXUS DEBUG CONNECTOR PINOUT ............................................................................................................ 14
TABLE 3-16 MCU PINS REQUIRED FOR EIM SRAM OPERATION ....................................................................................... 15
TABLE 3-17 SRAM, AND PLD POWER CONTROL JUMPERS (J22, J32)............................................................................... 16
TABLE 3-18 CHIP SELECT AND PORT-SIZE CONTROL JUMPER (J35)................................................................................... 16
TABLE 3-19 CAN CONTROL JUMPERS (J3, J4, J7).............................................................................................................. 17
TABLE 3-20. CAN PIN AVAILABILITY ............................................................................................................................... 17
TABLE 3-21 RS232 CONTROL JUMPERS ............................................................................................................................. 18
TABLE 3-22 SCI PIN AVAILABILITY .................................................................................................................................. 19
TABLE 3-23 LIN CONTROL JUMPERS ................................................................................................................................. 20
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TABLE 3-24 FLEXRAY MCU SIGNAL ROUTING JUMPERS (J12, J14) .................................................................................. 20
TABLE 3-25 FLEXRAY POWER CONTROL JUMPERS (J16, J18)............................................................................................ 21
TABLE 3-26 FLEXRAY CONTROL JUMPERS (J13, J15) ........................................................................................................ 21
TABLE 3-27 FLEXRAY PIN AVAILABILITY.......................................................................................................................... 21
TABLE 3-28 LED MATRIX CONTROL ................................................................................................................................. 22
TABLE 3-29 EIM PULLUP RESISTOR CONTROL (J26)......................................................................................................... 23
TABLE 4-1 VSSSYN FERRITE CONTROL ........................................................................................................................... 25
TABLE 4-2 DAUGHTERCARD CLOCK SELECTION ............................................................................................................... 26
TABLE 4-3 DAUGHTERCARD 32KHZ CLOCK SELECTION .................................................................................................... 26
TABLE 4-4 CLKOUT IMPEDANCE MATCHUING .................................................................................................................... 27
TABLE 5-1 EVB MCU PIN USAGE ...................................................................................................................................... 27
TABLE 6-1 DEFAULT JUMPER POSITIONS ........................................................................................................................... 28
TABLE 7-1 PORT A CONNECTOR PINOUT (P16) ................................................................................................................. 30
TABLE 7-2 RV1 CONNECTION JUMPER J8.......................................................................................................................... 30
TABLE 7-3 PORT B CONNECTOR PINOUT (P30).................................................................................................................. 30
TABLE 7-4 PORTC CONNECTOR PINOUT (P24) .................................................................................................................. 31
TABLE 7-5 PORTD CONNECTOR PINOUT (P15) .................................................................................................................. 31
TABLE 7-6 PORTE CONNECTOR PINOUT (P31)................................................................................................................... 31
TABLE 7-7 PORT F CONNECTOR PINOUT (P17) .................................................................................................................. 32
TABLE 7-8 PORT F CONNECTOR PINOUT (P25) .................................................................................................................. 32
TABLE 7-9 PORT H CONNECTOR PINOUT ........................................................................................................................... 32
TABLE 7-10 PORT J CONNECTOR PINOUT .......................................................................................................................... 33
TABLE 7-11 PORT K CONNECTOR PINOUT ......................................................................................................................... 33
TABLE 8-1 EXPANSION CONNECTOR PART NUMBERS ........................................................................................................ 35
TABLE 8-2 DAUGHTER CARD CONNECTOR 1 ..................................................................................................................... 35
TABLE 8-3 DAUGHTER CARD CONNECTOR 2 ..................................................................................................................... 36
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1. Introduction
This user manual details the setup and configuration of the Freescale Semiconductor MPC5510 Evaluation Board
(hereafter referred to as the EVB). The EVB is intended to provide a mechanism for easy customer evaluation of the
MPC5510 family of microprocessors, and to facilitate hardware and software development.
There are currently 3 package types supported within the MPC5510 family (and by the EVB), namely 208BGA, 176QFP
and 144QFP. For the latest product information, please speak to your freescale representative or consult the MPC5510
website at www.freescale.com
The EVB is intended for bench / laboratory use and has been designed using normal temperature specified components
(+70°C).
1.1 Modular Concept
For maximum flexibility and simplicity, the EVB has been designed as a modular development platform. The EVB main
board does not contain an MCU. Instead, the MCU is fitted to an MCU daughter card (sometimes referred to as an
adapter board). This approach means that the same EVB platform can be used for multiple package and MCU derivatives
within the MPC5510 family. High density connectors provide the interface between the EVB and MCU daughter cards as
shown in the diagram below. See section 4 for more information on the daughter card configuration.
Figure 1-1 Modular Concept – EVB and MCU Daughter Cards
MCU Daughter Card
with specific MCU and
local clock circuitry
High Density
Connectors
EVB containing all
circuitry except MCU
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2. EVB Features
The EVB provides the following key features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Support provided for different MPC5510 MCU family members by utilising MCU daughter cards.
Single 12-14V external power supply input with on-board regulators to provide all of the necessary EVB and
MCU voltages. Power may be supplied to the EVB via a 2.1mm barrel style power jack or a 2-way lever
connector. 12V operation allows in-car use if desired.
Freescale System Basis Chip footprint to allow use of the SBC power supply if required (available end 2007).
Flexible on-board power supply configuration with the option to bypass the internal MCU regulators for
diagnostic purposes. MCU power can also be sourced from either the EVB regulators or the SBC.
Master power switch and regulator status LED’s.
User reset switch with status LED’s.
User configurable LVI (Low Voltage Inhibit) device to monitor the status of the 5V regulators.
Control of the BOOTCFG status via a dedicated jumper.
Flexible MCU clocking options allow provision of an external clock via an SMA connector or 8Mhz EVB clock
oscillator circuit. Jumpers on the daughter card allow selection between these external clocks or the local
daughter card ALC oscillator circuitry. The MCU clkout signal is routed to an SMA connector for easy access.
Standard 14-pin ONCE debug connector and 38-pin MICTOR Nexus2+ connectors.
Twin 120-way polarised daughter card expansion connectors allowing connection of the MCU daughter card or
a custom board for additional application specific circuitry.
All of the MCU signals are readily accessible at a group of port-ordered 0.1” pitch headers.
Up to 256Kbytes of external SRAM memory which can be configured as either 32-bit or 16-bit data port width.
SCI channels A and B can be routed to either a standard DB9 female connector (PC RS-232 compliant) or LIN
interface header (0.1”), both will full physical transceivers (the SBC provides an additional 2 LIN interfaces).
MCU FlexCAN channels A and C can be routed to 0.1” headers via a Philips high speed CAN transceiver (The
SBC provides an additional CAN physical interface).
7x5 LED dot matrix display connected to the MCU eMIOS PWM channel [0..11] via a 16244 buffer / driver.
User prototyping area consisting of a 0.1” grid of through hole pads with easy access to the EVB ground and
power supply rails. 4 active low LED’s and 4 small pushbutton switches are adjacent to the prototype area.
Jumper selectable variable resistor connected to ATD channel 0, driving between VRH and VRL.
Liberal scattering of GND test points (surface mount loops) placed throughout the EVB.
Note – to alleviate confusion between jumpers and headers, all EVB jumpers are implemented as 2mm pitch whereas
headers are 0.1inch (2.54mm). This prevents inadvertently fitting a jumper to a header.
IMPORTANT
Before the EVB is used or power is applied, please fully read this user manual.
Failure to correctly configure the board may cause irreparable component, MCU or EVB damage.
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3. Configuration
This section details the configuration of each of the EVB functional blocks.
Throughout this document, all of the default jumper and switch settings are clearly marked with “(D)” and are shown in
blue text. This should allow a more rapid return to the default state of the EVB if required. Note that the default
configuration for 3-way jumpers is a header fitted between pins 1 and 2. On the EVB, 2-way and 3-way jumpers have
been aligned such that Pin1 is either to the top or to the left of the jumper. On 2-way jumpers, the source of the signal is
connected to Pin1.
The EVB has been designed with ease of use in mind and has been segmented into functional blocks as shown below.
Detailed silkscreen legend has been used throughout the board to identify all switches, jumpers and user connectors.
LIN
Serial (SCI)
CAN
User
Potentiometer
Flexray
Prototype
Area
LED
Matrix
Reset and
LVI
User LEDs
and switches
EIM and
SRAM
JTAG and
NEXUS
Clock
Circuitry and
SMA In / Out
User
Connectors
Power
Connectors
Daughter Card Connectors
(with MCU Daughter Card
Superimposed)
Voltage
Regulators
Power Routing
Jumpers
Figure 3-1 EVB Functional Blocks
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The Power supply
section is located in the
bottom left area of the
EVB
3.1 Power Supply Configuration
The EVB requires an external power supply voltage of 12V DC, minimum 1A. This allows the EVB to be easily used in
a vehicle if required. The 12v input is regulated on the EVB using 1 linear and 3 switching regulators to provide the
necessary EVB and MCU operating voltages of 5.0V, 3.3V and 1.5V. In addition, the EVB supports the Freescale
System Basis Chip (SBC) which is an integrated regulator for the MCU power supply lines. For flexibility there are two
different power supply input connectors on the EVB as detailed below.
3.1.1
Power Supply Connectors
2.1mm Barrel Connector – P28:
This connector should be used to connect the supplied wall-plug mains adapter. Note – if a replacement or alternative
adapter is used, care must be taken to ensure the 2.1mm plug uses the correct polarisation as shown below:
V+ (12V)
GND
Figure 3-2 2.1mm Power Connector
2-Way Lever Connector – P32:
This can be used to connect a bare wire lead to the EVB, typically from a laboratory power supply. The polarisation of
the connectors is clearly marked on the EVB. Care must be taken to ensure correct connection.
V+ (12V)
GND
Figure 3-3 2-Lever Power Connector
3.1.2
Power Switch (SW6)
Slide switch SW6 can be used to isolate the power supply input from the EVB voltage regulators if required.
Moving the slide switch to the right (away from connector P32) will turn the EVB on.
Moving the slide switch to the left (towards connector P32) will turn the EVB off.
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Regulator Power Jumpers (J42, J44, J45 and J46)
The Power supply control jumpers are located adjacent to the respective regulators.
As mentioned above, the EVB has four voltage regulators on board:
-
1.5V switching regulator (U20) to supply the MCU Core voltage when the MCU on-chip regulator is disabled.
3.3V switching regulator (U21) for EVB peripherals and MCU logic when the on-chip regulator is disabled.
5.0V switching regulator (U22) for the MCU regulator and I/O and EVB peripherals.
5.0V linear regulator (U19) for the MCU ADC power supply
All of the regulators have the option of being disabled if they are not required. The table below details the jumper
configurations for enabling and disabling the regulators. By default, all of the regulators are enabled.
Table 3-1 Regulator Power Jumpers
Jumper
J42 (5.0V-LINEAR)
J44 (1.5V)
J45 (3.3V)
J46 (5.0V)
3.1.4
Position
FITTED (D)
REMOVED
FITTED
REMOVED (D)
FITTED
REMOVED (D)
FITTED
REMOVED (D)
PCB Legend
ENABLE
DISABLE
DISABLE
DISABLE
Description
5.0V linear regulator output is Enabled
5.0V linear regulator output is Disabled
1.5V switching regulator output is Disabled
1.5V switching regulator output is Enabled
3.3V switching regulator output is Disabled
3.3V switching regulator output is Enabled
5.0V switching regulator output is Disabled
5.0V switching regulator output is Enabled
Power Status LED’s and Fuse
When power is applied to the EVB, four green LED’s adjacent to the voltage regulators show the presence of the supply
voltages as follows:
LED DS10 – Indicates that the 5.0V linear regulator is enabled and working correctly
LED DS11 – Indicates that the 1.5V switching regulator is enabled and working correctly
LED DS12 – Indicates that the 3.3V switching regulator is enabled and working correctly
LED DS13 – Indicates that the 5.0V switching regulator is enabled and working correctly
If no LED’s are illuminated when power is applied to the EVB and the regulators are correctly enabled using the
appropriate jumpers, it is possible that either power switch SW6 is in the “OFF” position or that the fuse F1 has blown.
The fuse will blow if power is applied to the EVB in reverse-bias, where a protection diode ensures that the main fuse
blows rather than causing damage to the EVB circuitry. If the fuse has blown, check the polarity of your power supply
connection then replace fuse F1 with a 20mm 500mA fast blow fuse.
3.1.5
SBC Power Jumper (J41)
The optional SBC (System Basis Chip) regulator has a single power supply input jumper as detailed in the table below.
By default, the SBC is disabled. For more details on the SBC regulator see Figure 3-4 below.
Table 3-2 SBC Power Jumpers
Jumper
J41 (SBC-PWR)
Position
FITTED
REMOVED (D)
PCB Legend
Description
SBC linear regulator output is Enabled
SBC linear regulator output is Disabled
Note – the SBC will not be available until the end of 2007 so it will not be fitted on an EVB manufactured prior to the
SBC release date.
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The MCU power supply
jumpers are located in the
centre of the EVB in a box
titled “MCU Supply”
MCU Supply Routing and Jumpers
(J21, J25, J27, J29, J30, J33, J34, J36, J37, J38)
The MCU has internal regulators to generate the 3.3V and 1.5V supplies for VDDSYN, VDD33 and VDD. Whilst this is
the intended mode of operation for the MCU, the EVB allows the internal MCU regulators to be disabled by
disconnecting VDDR and applying external voltages to the VDDSYN, VDD33 and VDD pins via jumpers J25, J27 and
J21 respectively).
The VDDE[1..3] pins control the pad voltages over 3 groupings of pads (see the MCU reference manual for details).
Jumpers J29, J30, J33 and J34 allow the VDDEx pins to be connected to the 5.0v or 3.3V switching regulators or to the
SBC auxiliary output which can is software selectable between 5.0V and 3.3V.
Each of the main supply pins (VDDA, VDDR, VPP and VDDEx) has the option of being routed from either the EVB
regulators (where VDDA has a dedicated linear regulator to ensure a accuracy) or from the SBC.
12V
J38
5V Linear
MCU Power
1
VDDA
J37
5V Switcher
1
VDDR
J36
1
VPP
J34
1
J33
1
VDDE1
SBC
MAIN
CAN Supply
AUX
5v
J30
1
5v
VDDE2
(3.3v / 5v)
1
VDDE3
J29
J25
VDDSYN
3.3V
Switcher
VDD33
J27
J21
1.5V
Switcher
VDD (1.5)
Figure 3-4 Power Supply Routing
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Table 3-3 MCU Power Supply Jumpers
Power
Domain
Jumper
J38 (VDDA)
5.0V
J37 (VDDR) *
J36 (VPP)
Position
1-2 (D)
2-3
1-2 (D)
2-3
REMOVED*
1-2 (D)
2-3
1-2 (D)
2-3
1-2 (D)
2-3
1-2 (D)
2-3
1-2 (D)
2-3
PCB
Legend
5V-L
SBC
5V-S
SBC
Description
5V-S
SBC
MCU VDDA is powered from 5V linear regulator
MCU VDDA is powered from SBC (VDD output)
MCU internal VREG is powered from 5.0V switching reg
MCU internal VREG is powered from SBC (VDD output)
MCU regulator is not powered (See note below)
MCU VPP is powered from 5.0V switching regulator
MCU VPP is powered from SBC (VCAN output)
5V-S
SBC
FRM J34
3.3V
FRM J34
3.3V
FRM J34
3.3V
VDDEx jumpers are supplied from 5V switching regulator
VDDEx jumpers are supplied from SBC (VAUX Output)
MCU VDDE1 is powered from output of J34
MCU VDDE1 is powered from 3.3V switching regulator
MCU VDDE2 is powered from output of J34
MCU VDDE2 is powered from 3.3V switching regulator
MCU VDDE3 is powered from output of J34
MCU VDDE3 is powered from 3.3V switching regulator
5.0V /
3.3V
J34
(VDDE SEL)
J33
(VDDE1)
J30
(VDDE2)
J29
(VDDE3)
3.3V
J27
(VDD33)
J25
(VDDSYN)
FITTED
REMOVED (D)
FITTED
REMOVED (D)
MCU VDD33 pin is powered from switching regulator
MCU VDD33 pin is not powered externally
MCU VDDSYN pin is powered from switching regulator
MCU VDDSYN pin is not powered externally
1.5V
J21 (VDD15)
FITTED
REMOVED (D)
MCU VDD pin is powered from 1.5v switching regulator
MCU VDD pin is not powered externally
The jumper configuration shown in Table 3-3, details the default state of the EVB. In this configuration, the SBC is not
used and all power is supplied from the Linear and Switching regulators.
- VDDA is connected to the 5.0V Linear regulator
- VDDR is connected to the 5.0V switching regulator, enabling the internal MCU 3.3V / 1.5V regulators
- VPP and VDDE[1..3] are connected to the 5.0V switching regulator
- VDD33, VDDSYN and VDD are not powered externally.
IMPORTANT
When jumper J37 (VDDR) is in position 1-2 (5V-S), the MCU internal voltage regulators are enabled and supply
power to the 3.3V and 1.5V MCU power domains. In this case, jumpers J27 (VDD33), J25 (VDDSYN) and J21
(VDD15) must not be fitted.
Similarly, when jumper J37 is removed, no power is supplied to the MCU internal voltage regulators and jumpers
J27 (VDD33), J25 (VDDSYN) and J21 (VDD15) must be fitted to power the respective MCU pins. The 3.3V and 1.5v
switching regulators must also be enabled in this case.
When the internal voltage regulator is disabled and power is applied to VDDSYN, VDD33 and VDD, a ferrite
bead on VSSSYN needs to be activated. This is achieved by de-soldering a zero-ohm link on the bottom of the
daughter card. See section 4.2.1 for details. Note that external regulator mode is not the intended mode of
operation of the MCU and should be used for test purposes only.
MPC5510EVBUM/D
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Sept 2007
3.1.6.1 VDDE[1..3] Voltage Groupings
Before changing the VDDEx voltage from the default 5.0V setting, you need to ensure that this will not impact any of the
EVB peripherals that may be in use. The table below details what EVB peripherals are tied to a particular VDDEx
grouping and also the MCU pin operating voltage suitable for that peripheral.
Table 3-4 VDDE[1..3] Pad Groupings
Item
LED Dot Matrix Display
External Memory
CANA and CANC
SCI / LIN A and B
Flexray
JTAG
Nexus
3.1.7
Port Pins
PortC[0..11]
PortG[0..15],
PortF[0..15],
PortH[14,15],
PortJ[0..7]
PortD [0..5]
PortD[6..9]
PortC[0..2, 7..9]
PF[0..11]
VDDE Group
VDDE1
VDDE2
VDDE2 / 3
VDDE2
VDDE2
VDDE1
VDDE1
VDDE1
VDDE3
VDDE2 / 3
Required Pad Voltage
5.0V or 3.3V
5.0V
5.0V
5.0V
5.0V or 3.3V (J18 selects)
5.0V
5.0V
EVB Circuitry Power Domains
Before disabling any of the EVB regulators, it is worthwhile considering if any of the EVB components or peripherals
you require will be affected. Table 3-5 details a list of the various EVB components and peripherals powered by the
regulators. Note – the SBC powers the MCU only and does not supply power to any of the EVB circuitry.
Table 3-5 Power Supply Distribution
Regulator
1.5V
(Switcher)
3.3V
(Switcher)
5.0V
(Switcher)
5.0V
(Linear)
MPC5510EVBUM/D
Used On
MCU VDD1.5 pins (ONLY use when on-chip MCU regulator is disabled)
Daughter Card Connectors (1.5V)
1.5V Power section of Prototype area
MCU VDD33 and VDDSYN pins (ONLY use when on-chip MCU regulator is disabled)
MCU VDDEx pins (when run in 3.3v mode)
Oscillator Module (Y1)
GAL22V10 (EIM Control)
Driver chip for LED Matrix
I/O supply for Flexray interface when VIO is 3.3V
Daughter Card Connectors (3.3V)
3.3V Power section of Prototype area
MCU VDDEx (5v mode), VPP and VDDR pins
LVI circuit main power (affecting Reset Switch)
Reset-In / Reset-Out logic
Reset configuration circuitry
SRAM memory and address latches
RS-232 Transceiver
LIN transceiver
CAN transceivers
Flexray transceivers
EIM signal pullup resistors
Daughter Card Connectors (5.0V)
5.0V Power section of Prototype area
eICE and Nexus connectors
MCU VDDA pin
LVI circuit monitor
Page 8 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
3.2 MCU Clock Control (J39 and J40)
3.2.1
The MCU clock
control jumpers are
located close to crystal
oscillator module Y1.
Clock Selection
The EVB supports three possible MCU clock sources:
(1) The local ALC pierce oscillator circuit (on the MCU daughter card)
(2) An 8Mhz oscillator module on the EVB (Y1), driving the MCU EXTAL signal
(3) An external clock input to the EVB via the SMA connector (P27), driving the MCU EXTAL signal
The clock circuitry is shown in the diagram below. Please refer to section 4 for specific daughter card configuration
details.
3.3V_SR
EVB Clock Circuitry
J39
Oscillator
Module
(Y1)
MCU Daughter Card
Local Clock Circuitry
J4
J40
MCU
EXTAL
SMA
(P27)
J3
Local Crystal
Circuit (Y1)
XTAL
GND
Figure 3-5 EVB Clock Selection
Table 3-6 Clock Source Jumper Selection
Jumper
J39 (Y1 PWR)
J40 (OSC SEL)
Position
FITTED (D)
REMOVED
1-2 (D)
2-3
PCB Legend
Y1
SMA
Description
EVB oscillator module Y1 is powered
EVB oscillator module Y1 is not powered
Daughter card EXT-CLK is routed from Y1
Daughter card EXT-CLK is routed from P27
The default configuration provides power to the EVB oscillator module (Y1) and routes this clock signal to the MCU
daughter card. Note that the 3.3V regulator must be enabled when using oscillator module Y1. In order to use the SMA
connector (P27) to supply a clock signal, jumper J40 must be moved to position 2-3 (SMA). The selection between local
clock circuitry or external oscillator is achieved using jumpers on the daughter card. See section 4 for details.
CAUTION
The MPC5510 clock circuitry is all 3.3v based. Any external clock signal
driven into the SMA connector must have a maximum voltage of 3.3V
MPC5510EVBUM/D
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Sept 2007
3.3 Reset Control (Jumpers J17, J19, J20, SW1)
The RESET switch (RED) and
LVI circuitry is located in the
top left corner of the EVB in
the area titled “RESET “
The EVB incorporates an LVI (Low Voltage Inhibit) device to provide under-voltage protection for the two main 5.0V
regulators (Linear and Switcher). The SBC has its on monitoring circuit so does not require external monitoring. When
either of the 5.0V regulator voltages fall below a preset threshold level, the LVI will assert the MCU reset line to prevent
incorrect operation of the MCU (or EVB circuitry).
The table below shows the approximate threshold voltages for each regulator
Table 3-7 LVI Monitor Threshold Voltages
Regulator
5.0V Linear
5.0V Switcher
Minimum Voltage Before MCU reset
4.45V
4.65V
The LVI is powered from the 5.0V switching regulator and monitors the 5.0V linear using a 2nd power fail monitor
circuit. The LVI also provides a de-bounced input for EVB reset switch SW1.
Jumpers are provided to disable either the main LVI reset out (which affects the reset from the 5.0V switching regulator
and from the reset switch) or the power fail out circuit (which only affects the reset from the 5.0V linear regulator). If the
switching regulator LVI is disabled, the reset switch will not function.
Table 3-8 LVI Control Jumpers
Jumper
Position
FITTED (D)
J20
Posn 1-2
REMOVED
J20
Posn 3-4
FITTED (D)
REMOVED
PCB Legend
MAIN
LINEAR
Description
5.0V switching regulator is monitored, Reset switch active
5.0V switching regulator is not monitored, Reset switch
inactive
5.0V linear regulator is monitored
5.0V linear regulator is not monitored
Notes:
- If the 5.0V switching regulator is disabled for any reason, the LVI circuit will attempt to assert the MCU Reset
signal. Jumper shunts on jumper J20 position 1-2 and 3-4 must be removed in this situation. This will also leave
the reset switch SW1 inoperative.
- If the 5.0V linear regulator is disabled, the shunt on jumper J20 position 3-4 must be removed to prevent the
LVI asserting reset.
3.3.1
Reset LEDs
There are two reset LED’s, DS1 (AMBER) and DS2 (RED), placed adjacent to the EVB RESET switch to indicate the
RESET status of the EVB and MCU.
LED DS2, titled “RST”, will illuminate if the MCU itself issues a reset. In this condition, LED DS1 will not illuminate.
LED DS1, titled “USR”, will illuminate when one of the following external hardware devices issues a reset to the MCU:
- LVI circuitry (either an under-voltage detection or the reset switch is pressed).
- There is a reset being asserted from the user connectors or from the daughter card.
- There is a reset being driven from the Nexus or JTAG debug probe.
Note that LED DS2 (MCU Reset) will also illuminate during an external (user) reset!
MPC5510EVBUM/D
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3.3.2
Sept 2007
Reset Buffering Scheme
The MPC5510 family has a single reset pin. This single pin functions as a dual purpose input / output signal, providing
Reset-In and Reset-Out functionality.
There is a lot of circuitry on the EVB that has access to the reset pin. In order to reduce the loading on the MCU when
driving the reset pin and also to allow connection of non open-drain reset inputs, a reset-in and reset-out buffering
scheme is implemented as shown in Figure 3-6.
Reset-In
- There are 3 possible external sources of reset:
- JTAG / Nexus connector reset
- User reset (from user connectors)
- LVI reset circuitry, including the reset switch.
Each of these reset sources is fed into the input of an AND gate and then converted to an open-drain output
which is directly connected to the MCU reset pin.
Reset-Out - The MCU reset pin is buffered to provide a reset-out signal, capable of driving the reset LED and also
all other devices requiring a reset input.
The reset buffering scheme is detailed below – note that the SBC also has an open drain reset in / out that is
connected directly to the MCU reset line.
Reset IN
From JTAG / Nexus
Tri State Buffer
MCU
From TGT
J17
From LVI (Main)
RESET
J20
From LVI (Linear)
GND
Reset OUT
Reset OUT
(To RED Reset LED, BDM
Reset In, external device reset)
Figure 3-6 EVB Reset Buffering Scheme
Jumper J17 is used to completely disconnect the reset-in buffering if desired. This is for debug purposes only and should
normally be left connected. Disconnecting this jumper will mean no external MCU reset can be achieved
Table 3-9 Reset-Out Control Jumper
Jumper
J17 (RST-IN)
Position
FITTED (D)
REMOVED
MPC5510EVBUM/D
PCB Legend
Description
External reset source (LVI, Debug or Target) will be able
to assert MCU reset
External reset is disabled (Not recommended)
Page 11 of 36
MPC5510EVB User Manual Rev 1.0
3.3.3
Sept 2007
Reset Boot Configuration (J19)
The MPC5510 has a single boot configuration pin (BOOTCFG) which determines the boot location of the MCU based
on the state of the pin at POR (Power On Reset). This is shown in the table below:
Table 3-10 BOOTCFG Control
Jumper
J19 (BOOT CFG)
Position
1-2 (D)
2-3
PCB Legend
FSH
SERIAL
Description
MCU boots from internal flash
MCU boots from external serial source
Note – there have been some problems observed when application code is present in flash and an attempt is made to load
and execute a different application from internal RAM. Depending on the configuration and speed of the debugger used,
it is feasible that the application code in flash will already have started to execute by the time the debugger gains control.
This has implications if the flash code has already done some configuration of the device that is in conflict with the
operation of the code that is about to be loaded into RAM. To prevent this occurring, it is advised to either erase the
internal flash or to prevent the MCU booting from flash by moving jumper J19 to position 2-3.
The ONCE and NEXUS
connectors are located at the
left hand edge of the EVB
3.4 Debug Configuration
(J24, J28, J31, J31B)
The EVB supports a standard ONCE cable with a 14-pin 0.1” walled header footprint. There is also a 38-pin MICTOR
connector for Nexus 2+ debug. Four generic jumpers are associated with both the ONCE and Nexus, as detailed below.
3.4.1
TCLK Configuration
Some debug manufacturers specify whether the debug TCLK signal is pulled low or high. Jumper J28 provides the
ability to select whether TCLK is pulled to GND or 5V.
Table 3-11 ONCE / NEXUS TCLK Termination Control
Jumper
J28
(TCLK PULL)
Position
1-2 (D)
2-3
PCB Legend
5V
GND
Description
TCLK signal is pulled to 5.0V via 10KΩ
TCLK signal is pulled to GND via 10KΩ
Notes:
- J28 is located to the right of the reset switch, out-with the ONCE / Nexus connector area.
- To achieve accurate low power current measurements, TCLK should be pulled to GND
3.4.2
Reset Buffering
Most debug probes only assert the MCU reset line but some also have the ability to also monitor the status of the reset
line. This is not possible when the reset signal is buffered so jumper J31 is included to allow routing the debug reset
signal direct to the MCU reset pin or via the EVB Reset-In buffering.
Table 3-12 JTAG / NEXUS Target Reset Routing
Jumper
J31 (JRST)
Position
PCB Legend
1-2 (D)
BUFFER
2-3
DIRECT
Description
JTAG reset signal is buffered to MCU RESET pin
(connected to the MCU Reset-In circuitry)
JTAG reset signal is connected direct to MCU RESET pin
The default configuration connects the JTAG reset signal to the MCU reset via a buffer so the probe cannot monitor the
reset. If your debug probe has an open-drain reset capable of monitoring the reset signal, this can be enabled by moving
jumper J31 to position 2-3.
MPC5510EVBUM/D
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Sept 2007
CAUTION
If jumper J31 is positioned 2-3 and the debug probe actively drives the reset line high and
low, nothing else will be able to assert the MCU reset (including the MCU itself).
3.4.3
PFO Selection
MCU pin PF0 has alternate functions of EVTI (debug control signal) and R/W. To prevent conflicts between the external
memory and debug interface, jumper J31B is used to route PF0 to either the debug connectors or the external memory as
shown in the table, below.
Table 3-13 PFO EVTI / R/W Function Selection
Jumper
J31B (PFO Sel)
Position
1-2 (D)
2-3
PCB Legend
EVTI
RW
Description
MCU PFO is routed to the ONCE / Nexus debug connector
MCU PFO is routed to the external memory system
The default configuration connects PF0 to the debug connectors to act as EVTI. If the external bus is to be used then
J31B must be moved to position 2-3 to route PF0 to the memory subsystem as the R/W signal.
Note – EVTI is optional for ONCE debug and generally not required so with the jumper configured in position 2-3 to
enable RW, a “ONCE” debug session can still be established.
3.4.4
Vendor I/O Configuration
Some Nexus debug probes can use the “Vendor I/O2” signal to drive BOOTCFG reset configuration data at reset. The
EVB is designed such that this will over-ride any BOOTCFG data supplied by jumper J19 (see section 3.3.3). A jumper
is supplied to allow this feature to be enabled if desired.
Table 3-14 Vendor I/O2 Drive Control
Jumper
J24
(VEND-IO)
Position
FITTED
REMOVED (D)
PCB Legend
Description
Vendor I/O2 pin disconnected
Vendor I/O2 pin can drive BOOTCFG at reset
By default, the debug tool will not have the ability to over-ride the EVB BOOTCFG settings and J24 will be removed. To
enable this feature, fit jumper J24.
Note – Be careful when fitting jumper J24 as this will override the EVB BOOTCFG setting when a nexus probe is fitted
to the EVB.
MPC5510EVBUM/D
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MPC5510EVB User Manual Rev 1.0
3.4.5
Sept 2007
Debug Connector Pinouts
The EVB is fitted with 14-pin JTAG / ONCE and 38-pin Nexus 2+ debug connectors. The following diagram shows the
14-pin JTAG / ONCE connector pinout (0.1” keyed header).
TDI
TDO
TCLK
EVTI
RESET
VDD5V
RDY
2
4
6
8
10
12
14
1
3
5
7
9
11
13
VSS
VSS
VSS
N/C
TMS
VSS
JCOMP
Figure 3-7 MPC5510 JTAG / ONCE Connector
The Nexus module used on the MPC5510 family uses the JTAG pins (for control of the Nexus block) along with
additional Nexus pins for trace messages. Nexus mode is entered by a JTAG sequence whereby the Nexus EVTI pin is
sampled on the rising edge of the JTAG TRST pin. If the EVTI is asserted on TRST, Nexus is enabled.
The table below shows the pinout of the 38-pin MICTOR Nexus connector for the MPC5510
Table 3-15 NEXUS Debug Connector Pinout
Pin No
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
Function
Reserved
Reserved
Vendor I/O-0
Vendor I/O-2
Reset-In
TDO
Vendor I/O-4
TCLK
TMS
TDI
TRST
Vendor I/O-1
Tool I/O-3
Tool I/O-2
Tool I/O-1
UBATT
UBATT
Tool I/O-0
VALTREF
Connection
------BOOTCFG
Reset CCT
MCU TDO
--MCU TCK
MCU TMS
MCU TDI
JCOMP
--RST-OUT
----12V Vin
12V Vin
--P5V
Pin No
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Function
Reserved
Reserved
CLKOUT
Vendor I/O-3
EVTI
VREF
RDY
MDO[7]
MDO[6]
MDO[5]
MDO[4]
MDO[3]
MDO[2]
MDO[1]
MDO[0]
EVTO
MCK0
MSE1
MSEO
Connection
----MCU PE6
--MCU PF0
P5V
--MCU PF11
MCU PF10
MCU PF9
MCU PF8
MCU PF7
MCU PF6
MCU PF5
MCU PF4
MCU PF1
MCU PF3
----
MCU PF2
Note - In order to preserve the ability to accurately measure power consumption on the MCU pins, the JTAG and Nexus
connector reference voltages are sourced directly from the 5V regulator or from the 12V unregulated input.
MPC5510EVBUM/D
Page 14 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
The external memory block is
located on the right had side of
EVB with some jumpers to
right of the reset switch
3.5 External Memory Configuration
The MPC5510 external bus interface supports a multiplexed address/data bus with a configurable data-port size of either
16-bits or 32-bits. The EVB uses 3 x 128Kbyte (16-bit) asynchronous SRAM memories to provide either 128Kbytes of
memory in 16-bit port width mode or 256Kbytes of memory in 32-bit port width. A high speed PLD is used to control the
routing of the relevant control signals depending on the selected port size.
Note that the SRAM does not supply a transfer acknowledge (TA) signal to the MCU at the end of a data cycle so the
MCU external bus must be configured with auto TA acknowledge enabled. Additional wait states may be required
depending on the MCU bus speed. See the relevant MCU reference manual for more details.
MPC5516
Mux’d
Address/Data
Address
Latch
(Upper)
Demux’d
Address
A[13..29]
SRAM
64Kx16
(Upper)
D[0..15]
Address
Latch
(Lower)
32-bit
Port
A[13..29]
SRAM
64Kx16
(Lower)
D[16..31]
Naming
Conventions:
Address A31 is LSB
Data D31 is LSB
A[15..30]
Data
(Effectively)
SARAM
64Kx16
16-bit
Port
D[16..31]
Figure 3-8 External Memory Subsystem
The MPC5510 family does not have an “expanded mode” of operation unlike other MCU families you may have
encountered. Instead the individual port pins must be switched to the correct mode of operation for the external bus. The
table below shows what MCU pins are required for correct bus operation in 16-bit and 32-bit port size modes.
Table 3-16 MCU pins required for EIM SRAM operation
SRAM Port Size
Configuraiton
16-Bit
32-Bit
Notes:
-
PortE
6
6
Port F
Port G
Port H
Port J
0, 1, 9, 10, 11, 12, 13, 14, 15
[0..15]
[0..15]
[0..15]
14, 15
[0..7]
PE6 is the MCU CLKOUT pin which is required for the operation of the external memory
PortF is shared with the Nexus debug port so the external memory cannot be used at the same time as Nexus.
Jumpers are provided as detailed in the following sections to enable the memory system and also to control the MCU
chip select assignment and port size configuration. Note that the 3.3V and 5.0V switching regulators must be enabled for
the external memory system to function.
MPC5510EVBUM/D
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3.5.1
Sept 2007
Memory Power Control (J22, J32))
The memory subsystem has components operating at 3.3V and 5.0V. Each of these power domains has a separate power
jumper as detailed below. The SRAM devices and address latch buffers operate at 5.0V, controlled by jumper J22. The
PLD used to control the logic is powered from 3.3V (with 5.0V tolerant I/O). This has a separate power jumper J32.
Table 3-17 SRAM, and PLD Power Control Jumpers (J22, J32)
Jumper
J22
(SRAM PWR)
J32
(GAL-PWR)
Position
FITTED (D)
REMOVED
FITTED
REMOVED (D)
PCB Legend
Description
The SRAM and address latches are powered (enabled)
The SRAM and latches are not powered (disabled)
The control PLD is powered (enabled)
The control PLD is not powered (disabled)
By default the SRAM memory and latches are powered but the PLD is disabled. This ensures that outputs on the buffers
and SRAM’s are tri-stated so do not affect the corresponding GPIO signals. To power down the memory and latches if
desired, remove jumper J22. In order to use the external SRAM, the memory, latches and GAL must all be powered by
fitting jumpers J22 and J32.
Note – The SRAM and buffers are 5.0V devices so the corresponding MCU pins must be configured as 5.0V.
3.5.2
Port Size Select and Chip Select Control (J35)
Jumper J35 serves 2 purposes with a single jumper. Firstly it determines which MCU chip select (CS0 or CS1) is used to
control the SRAM and secondly it determines whether the SRAM is configured for a 16-bit or 32-bit data port size.
Table 3-18 Chip select and Port-Size Control Jumper (J35)
Jumper
J35
Position
REMOVED
2-4 (D)
4-6
1-3
3-5
PCB Legend
CS0 / 16-Bit
CS1 / 16-Bit
CS0 / 32-Bit
CS1 / 32-Bit
Description
No SRAM system is enabled
MCU chip select 0 is used to control 16-bit SRAM
MCU chip select 1 is used to control 16-bit SRAM
MCU chip select 0 is used to control 32-bit SRAM
MCU chip select 1 is used to control 32-bit SRAM
Notes:
- The jumper shunts should be placed horizontally! Any jumper combination other than those shown in the table
above is invalid and will cause mal-function of the EVB or MCU.
- This jumper header has no effect unless jumper J22 and J32 are fitted.
J35
2
6
16-Bit
32-Bit
1
5
CS0
CS1
Figure 3-9 CS and Port-Size Control Jumper
By default, jumper header J35 is fitted to position 2-4. This enables the 16-bit SRAM system connected to MCU chip
select CS0. Moving the jumper horizontally determines which chip select is used, whereas moving the jumper header
vertically determines whether the 16-bit or 32-bit wide SRAM system is enabled.
Two LED’s adjacent to the GAL (DS8 / DS9) indicate the GAL operation and status.
DS9 shows GAL is powered and programmed and goes out when the EVB or MCU is in reset.
DS8 illuminates when an external SRAM access is taking place.
MPC5510EVBUM/D
Page 16 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
The CAN section is located in
the top right corner of the EVB
in an area marked “CAN”
3.6 CAN Configuration (J3, J4, J7)
The EVB has a Philips PCA82C250T high speed CAN transceiver on each of the MCU CAN-A and CAN-C channels.
The transceiver is pre-configured for high speed operation by tying pin 8 of each PCA82C250T to ground via a zero ohm
resistor. If required, these resistors can be exchanged to provide slope control mode of operation. See the EVB
schematics at the end of this manual for details on the resistor to change.
For flexibility, the CAN transceiver I/O is connected to a standard 0.1” connector at the top edge of the PCB. Connector
P3 provides the CAN bus level signal interface for CAN-A and connector P4 for CAN-B. The pinout for these
connectors is shown below.
1
HI
LOW GND
Figure 3-10 CAN Physical Interface Connector
Each of the MCU signals to the CAN transceivers is jumpered, allowing the transceiver to be isolated if the respective
MCU pin is not configured or used for CAN operation. There is a 2x2 jumper for each CAN channel (one for Rx, one for
Tx), as shown in the table below. The Global power jumper (J7) physically removes power from both CAN transceivers.
Table 3-19 CAN Control Jumpers (J3, J4, J7)
Jumper
J7
(VDD-CAN)
Position
FITTED (D)
REMOVED
J3 (CAN-A)
Posn 1-2
J3 (CAN-A)
Posn 3-4
FITTED (D)
REMOVED
FITTED (D)
REMOVED
J4 (CAN-C)
Posn 1-2
J4 (CAN-C)
Posn 3-4
FITTED (D)
REMOVED
FITTED (D)
REMOVED
PCB Legend
TX
RX
TX
RX
Description
Power is applied to both CAN transceivers
No power is applied to CAN transceivers
MCU CNTX-A is connected to CAN controller A
MCU CNTX-A is NOT routed to CAN controller .
MCU CNRX-A is connected to CAN controller A
MCU CNRX-A is NOT routed to CAN controller.
MCU CNTX-C is connected to CAN controller C
MCU CNTX-C is NOT routed to CAN controller .
MCU CNRX-C is connected to CAN controller C
MCU CNRX-C is NOT routed to CAN controller.
The default configuration is with all jumpers fitted. This fully enables both CAN-A and CAN-C, with all MCU signals
routed to the transceivers. If the MCU is configured such that a CAN channel is used as GPIO, then the respective
jumpers must be removed from J3 or J4 or conflicts will occur.
Notes
-
Both CAN channels are available on all current package derivatives (see table below)
Care should be taken when fitting the jumper headers to the 2x2 jumper blocks J3 and J4 as they can easily be
fitted in the incorrect orientation. Jumpers J3 and J4 are fitted horizontally.
Table 3-20 CAN Pin Availability
CAN
A
B
C
MPC5510EVBUM/D
1ST Alternate
TX
RX
PD0
PD1
PD3
PD2
PD4
PD5
Pin Availability
144 Pin
176 Pin
208 Pin
D
D
D
D
D
D
D
D
D
Page 17 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
3.7 RS232 Configuration (J9, J10, J11)
The RS232 circuitry is located
at the top edge of the EVB in
an area titled “SCI”
The EVB has a single MAX232CSE RS232 transceiver device, providing RS232 signal translation for MCU SCI
channels A and B.
Each of the two RS232 outputs from the MAX232 device is connected to a 9-way female D-Type connector, allowing a
direct RS232 connection to a PC or terminal. Connector P5 provides the RS232 level interface for MCU SCI-A and P6
for MCU SCI-B. The pinout of these connectors is detailed below. Note that hardware flow control is not supported on
this implementation.
Figure 3-11 RS232 Physical Interface Connector
The MPC5516 eSCI also provides hardware LIN master capability which is supported on the EVB via LIN transceivers
(see section 3.8 for details). Jumpers J10 and J11 are provided to route the MCU SCI signals to either the RS232 or LIN
physical interfaces as described below. There is also a global power jumper (J9) controlling the power to the RS232
transceivers.
Jumper
J9
(SCI-PWR)
J10 (SCI-A)
Top Row
J10 (SCI-A)
Bottom Row
J11 (SCI-B)
Top Row
J11 (SCI-B)
Bottom Row
Position
FITTED (D)
REMOVED
2-4 (D)
4-6
REMOVED
1-3 (D)
3-5
REMOVED
2-4 (D)
4-6
REMOVED
1-3 (D)
3-5
REMOVED
Table 3-21 RS232 Control Jumpers
PCB Legend
Description
Power is applied to the MAX232 transceiver
No power is applied to the MAX232 transceiver
TXD
RXD
TXD
RXD
MCU TXD-A is routed via MAX232 to P5
MCU TXD-A is routed via LIN transceiver to P8
MCU TXD-A signal is disconnected from CAN/LIN
MCU RXD-A is routed via MAX232 to P5
MCU RXD-A is routed via LIN transceiver to P8
MCU RXD-A signal is disconnected from CAN/LIN
MCU TXD-B is routed via MAX232 to P6
MCU TXD-B is routed via LIN transceiver to P7
MCU TXD-B signal is disconnected from CAN/LIN
MCU RXD-B is routed via MAX232 to P6
MCU RXD-B is routed via LIN transceiver to P7
MCU RXD-B signal is disconnected from CAN/LIN
The default configuration enables SCI-A and SCI-B channels. RS232 compliant interfaces (with no hardware flow
control) are available at DB9 connectors P5 and P6. If the MCU is configured such that the pins used on SCI-A or SCI-B
are used for GPIO (see Table 3-22), then the relevant jumpers must be removed to avoid any conflicts occurring. If
required, jumper J9 can be used to completely disable the SCI transceiver.
Note - Care should be taken when fitting the jumper headers to the 2x3 jumper blocks J10 and J11 as they can easily be
fitted in the incorrect orientation. Jumpers J10 and J11 are fitted horizontally.
MPC5510EVBUM/D
Page 18 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
Table 3-22 SCI Pin Availability
SCI
A
B
C
D
E
F
G
h
1ST Alternate
TX
RX
PD6
PD7
PD8
PD9
PF10 PF11
PF12 PF13
PH4
PH5
PH6
PH7
PB12 PB13
PB14 PB15
Pin Availability
144 Pin
176 Pin
208 Pin
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
x
D
D
x
3.8 LIN Configuration (J1, J2, J5, J6)
The LIN circuitry is located in
the top edge of the EVB in an
area titled “LIN”
The EVB is fitted with two freescale MC33399 LIN transceivers. The MCU SCI channels incorporate a hardware
controlled LIN master, and as such, the LIN transceiver is connected to the same MCU pins as the RS232 transceiver.
Jumpers J10 and J11 are used as described in section 3.7 (and in the table below) to determine whether the relevant MCU
pins are connected to the LIN transceiver or the SCI transceiver.
For flexibility, the LIN transceivers are connected to a standard 0.1” connector (P8 for LIN-A and P7 for LIN-B) at the
top edge of the PCB as shown in the figure below. For ease of use, the 12V EVB supply is fed to pin1 of the connectors
and the LIN transceiver power input to pin 2. This allows the LIN transceiver to be powered directly from the EVB
supply by simply linking pins 1 and 2 of connector P7/P8 using a 0.1” jumper shunt.
P7/P8
1
VDD UNREG
LIN VSUP
LIN
GND
LIN
Figure 3-12 LIN Physical Interface Connector
Along with the MCU signal routing jumpers (J10 / J11), there are jumpers (J5 / J6) to enable or disable the LIN
transceiver and jumpers (J1 and J2) which determine if the LIN transceiver is operating in master or slave mode, as
defined in the table below.
MPC5510EVBUM/D
Page 19 of 36
MPC5510EVB User Manual Rev 1.0
Jumper
J1
(LINB-M)
J2
(LINA-M)
Position
FITTED (D)
REMOVED
FITTED (D)
REMOVED
J5*
(LINB-EN)
J6*
(LINA-EN)
FITTED (D)
REMOVED
FITTED (D)
REMOVED
J10 (SCI-A)
Top Row
J10 (SCI-A)
Bottom Row
J11 (SCI-B)
Top Row
J11 (SCI-B)
Bottom Row
2-4 (D)
4-6
REMOVED
1-3 (D)
3-5
REMOVED
2-4 (D)
4-6
REMOVED
1-3 (D)
3-5
REMOVED
Sept 2007
Table 3-23 LIN Control Jumpers
PCB Legend
Description
LIN-B transceiver is configured for LIN Master mode
LIN-B transceiver is configured for LIN Slave mode
LIN-A transceiver is configured for LIN Master mode
LIN-A transceiver is configured for LIN Slave mode
The LIN-B transceiver is enabled
The LIN-B transceiver is disabled
The LIN-A transceiver is enabled
The LIN-A transceiver is disabled
TXD
RXD
TXD
RXD
MCU TXD-A is routed via MAX232 to P5
MCU TXD-A is routed via LIN transceiver to P8
MCU TXD-A signal is disconnected from CAN/LIN
MCU RXD-A is routed via MAX232 to P5
MCU RXD-A is routed via LIN transceiver to P8
MCU RXD-A signal is disconnected from CAN/LIN
MCU TXD-B is routed via MAX232 to P6
MCU TXD-B is routed via LIN transceiver to P7
MCU TXD-B signal is disconnected from CAN/LIN
MCU RXD-B is routed via MAX232 to P6
MCU RXD-B is routed via LIN transceiver to P7
MCU RXD-B signal is disconnected from CAN/LIN
* Note – Jumpers J5/J6 do NOT route power to LIN transceivers, they only control an enable line on the LIN device.
Power to the LIN transceiver is supplied via connectors P7 / P8, pin 2.
The Default LIN configuration is with the module enabled in master mode. By default, the EVB SCI/LIN signals are
routed to the SCI transceivers. To use the LIN interface, the corresponding RX and TX pins must be routed to the LIN
transceivers by re-configuring jumpers J10 and J11 with the shunts positioned on pins 2-3 and 5-6. LIN slave mode can
be enabled by removing jumpers J1 / J2.
The Flexray circuitry is
located in the top edge of the
EVB in an area titled
“Flexray”
3.9 Flexray Configuration
(J12, J13, J14, J15, J16, J18)
The EVB is fitted with 2 flexray physical interfaces connected to MCU flexray channels A and B. Jumpers J12 and J14
are provided to route the respective MCU signals to the physical interfaces as described below.
Table 3-24 Flexray MCU Signal Routing Jumpers (J12, J14)
Jumper
J12 (Flex-A)
Posn 1-2
J12 (Flex-A)
Posn 3-4
J12 (Flex-A)
Posn 5-6
Position
FITTED
REMOVED (D)
FITTED
REMOVED (D)
FITTED
REMOVED (D)
J14 (Flex-A)
Posn 1-2
J14 (Flex-A)
Posn 3-4
J14(Flex-A)
Posn 5-6
FITTED
REMOVED (D)
FITTED
REMOVED (D)
FITTED
REMOVED (D)
MPC5510EVBUM/D
PCB Legend
TX
TXEN
RX
TX
TXEN
RX
Description
MCU PC1 is connected to Flexray A transceiver TX
MCU PC1 is not connected to Flexray A transceiver TX
MCU PC0 is connected to Flexray A transceiver TXEN
MCU PC1 is not connected to Flexray A transceiver TXEN
MCU PC2 is connected to Flexray A transceiver RXEN
MCU PC2 is not connected to Flexray A transceiver RXEN
MCU PC8 is connected to Flexray B transceiver TX
MCU PC8 is not connected to Flexray B transceiver TX
MCU PC9 is connected to Flexray B transceiver TXEN
MCU PC9 is not connected to Flexray B transceiver TXEN
MCU PC7 is connected to Flexray B transceiver RXEN
MCU PC7 is not connected to Flexray B transceiver RXEN
Page 20 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
The power to the Flexray physical interface is controlled via jumper J16 to allow disconnection if required. The Flexray
physical interface is capable of interfacing with MCU I/O voltages of 3.3V or 5.0V as defined by the voltage supplied to
VIO via jumper J18. On the MPC5516, the MCU pad voltage is controlled by the voltage supplied to VDDE[1..3]. The
user must ensure that the voltage on the respective PortC pads is the same as VIO supplied to the flexray interface.
Table 3-25 Flexray Power Control Jumpers (J16, J18)
Jumper
J16 (Flex-PWR)
Posn 1-2
J16 (Flex-PWR)
Posn 3-4
J16 (Flex-PWR)
Posn 5-6
J18
(VIO)
Position
FITTED
REMOVED (D)
FITTED
REMOVED (D)
FITTED
REMOVED (D)
1-2 (D)
2-3
REMOVED
PCB Legend
Description
12V Flexray circuitry is powered from main 12Vinput
12V Flexray circuitry is not powered
5V Flexray circuitry is powered from 5.0V switching reg
5V Flexray circuitry is not powered
VIO Flexray circuitry is powered from J18
VIO Flexray circuitry is not powered
12V
5V
VIO
VIO is selected as 5.0V.
VIO is selected as 3.3V
No Power is applied to the VIO jumper J16, posn 5-6
5V
3.3V
The flexray interface has 4 pins which are used for configuration and are pulled high or low controlled by a jumper as
described in the table below. By default, all of the jumper headers are fitted. Please consult the Flexray physical interface
specification before changing any of these jumpers.
Table 3-26 Flexray Control Jumpers (J13, J15)
Jumper
J13 (Flex-A)
Posn 1-2
J13 (Flex-A)
Posn 3-4
J13 (Flex-A)
Posn 5-6
J13 (Flex-A)
Posn 7-8
Position
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
J15 (Flex-B)
Posn 1-2
J15 (Flex-B)
Posn 3-4
J15 (Flex-B)
Posn 5-6
J15 (Flex-B)
Posn 7-8
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
PCB Legend
BGE
EN
STBEN
WAKE
BGE
EN
STBEN
WAKE
Description
Flexray-A interface BGE signal is pulled to VIO
Flexray-A interface BGE signal is unterminated
Flexray-A interface EN signal is pulled to VIO
Flexray-A interface EN signal is unterminated
Flexray-A interface STBN signal is pulled to VIO
Flexray-A interface STBN signal is unterminated
Flexray-A interface WAKE signal is pulled to GND
Flexray-A interface WAKE signal is unterminated
Flexray-B interface BGE signal is pulled to VIO
Flexray-B interface BGE signal is unterminated
Flexray-B interface EN signal is pulled to VIO
Flexray-B interface EN signal is unterminated
Flexray-B interface STBN signal is pulled to VIO
Flexray-B interface STBN signal is unterminated
Flexray-B interface WAKE signal is pulled to GND
Flexray-B interface WAKE signal is unterminated
Notes:
- The default configuration has the flexray controller disabled. Flexray A and B are a second alternate function of
PortC (as shown in the table below). Before enabling Flexray, you must ensure that none of the associated port
pins are being used for any other function. On the EVB, PortC is shared with the LED Dot matrix display.
- The flexray physical interfaces use molex 1.25mm shrouded 2-pin connectors to connect to the flexray bus (as
are standard fit on many Freescale development platforms using flexray).
Important:
A 40Mhz oscillator is required for the correct operation of the flexray controller. Please ensure that
an appropriate crystal is fitted to the MCU daughter card or use a 40Mhz external clock source.
Table 3-27 Flexray Pin Availability
Flexray
A
B
MPC5510EVBUM/D
2nd Alternate
TXEN
TX
RX
PC0
PC1
PC2
PC9
PC8
PC7
Pin Availability
144 Pin
176 Pin
208 Pin
D
D
D
D
D
D
Page 21 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
The LED matrix is located
beneath the prototype area
3.10 LED Dot Matrix (J23)
The EVB includes a 5x7 LED dot matrix display connected via a 16244 buffer to MCU PortC / eMIOS [0..11] pins. The
PWM ability on the pins allows strobing effects or the brightness of the matrix to be controlled if desired.
The LED matrix does not have any automatic character generation circuitry so to generate characters, the 7 rows of the
display must be written row at a time with sufficient scan speed to form the character without flicker. This is potentially a
good background task for the Z0 core on the 5510!
The diagram below shows how the matrix is connected. Note that this is a common anode display so is illuminated by
asserting the columns “high” and the rows “low”. If desired, the top two rows can be disabled for use with GPIO leaving
5 rows enabled which is still sufficient for most characters.
PC/eMIOS11
Top 2 rows can be
disabled if required
PC/eMIOS10
PC/eMIOS9
PC/eMIOS5
16244
Buffer
Resistors to give
approx 8mA
PC/eMIOS4
PC/eMIOS0
Figure 3-13 LED Matrix Control
The 16244 buffers provide 4 separate output enable blocks. These have been configured such that one block controls
PortC outputs 10 and 11 and the remaining 3 blocks control PortC outputs [0..9]. This allows the top two rows to be
disabled if required. A single jumper provides this functionality as described below.
Table 3-28 LED Matrix Control
Jumper
J23
(LED-Enable)
Posn 1-2
J23
(LED-Enable)
Posn 3-4
MPC5510EVBUM/D
Position
FITTED (D)
REMOVED
FITTED (D)
REMOVED
PCB Legend
HIGH
LOW
Description
MCU PortC[10..11] signals are connected to LED Matrix
MCU PortC[10..11] are not connected to LED Matrix
MCU PortC[1..9] signals are connected to LED Matrix
MCU PortC[1..9] are not connected to LED Matrix
Page 22 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
By default, the LED matrix is fully enabled with MCU PortC[0..11] signals being routed to the LED Matrix. If you don’t
wish to use the matrix, both jumpers should be removed from J23.
Caution – PortC is also used by the Flexray interface so the LED matrix and flexray interface cannot be used
concurrently. See section 5 for more details.
3.11 Termination Resistor Control (J26)
The termination control jumper
is located to the right of the
Reset switch. .
When using the external bus, there are some of the MCU control signals that must be pulled high. In most normal
circumstances these signals can also be left pulled high when the external bus is not used, however a jumper (J26) is
provided to disconnect the power to these pulllup resistors if desired.
Jumper
J26
(EIM Pullup)
MPC5510EVBUM/D
Table 3-29 EIM Pullup Resistor Control (J26)
Position
PCB Legend
Description
FITTED (D)
The external bus pullup resistors are powered (enabled)
REMOVED
The external bus pullup resistors are not powered (disabled)
Page 23 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
4. Daughtercards
This section of the user manual details how to configure, install and remove the MCU daughtercards. Failure to follow
the installation and removal instructions could cause damage to the daughtercard connectors. There are 3 daughtercards
available as shown in the picture below. The jumper naming has been standardised between the daughtercards so the
configuration steps are identical, making it extremely easy to migrate between cards.
144QFP
208BGA
176QFP
Figure 4-1 Daughter Cards
4.1 Installation and Removal Instructions
The MPC5510EVB daughtercard connectors have a unique placement footprint meaning that only daughtercards from
the MPC5510 family can be fitted.
To fit the daughtercard:
- Ensure that the EVB is powered off
- With the white arrow on the daughtercard pointing towards the top of the EVB, carefully line up the connectors
on the underside of the daughtercard with those on the EVB and gently press down to fit the daughtercard.
Ensure the connectors are fully mated by pushing down on all corners of the daughtercard, or the EVB may not
function as expected.
To remove the daughtercard:
- Ensure the EVB is powered off
- Gently rock the daughter card along the axis shown in the picture below. Note that attempting to pull the
daughtercard off the board in any other manner will probably cause damage to the connectors.
Figure 4-2 Daughter Card Removal
MPC5510EVBUM/D
Page 24 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
4.2 Daughtercard Configuration
4.2.1
External VREG Configuration
The default (and recommended) mode of operation of the MCU is to use the internal voltage regulators. If you need to
bypass the internal voltage regulators and supply 3.3V and 1.5V externally, then a modification is required to the
daughtercard to enable a ferrite bead on VSSSYN.
This is performed by de-soldering a zero ohm link located on the underside of the board.
Table 4-1 VSSSYN Ferrite Control
Daughtercard
Zero Ohm link to remove
144QFP
R6
176QFP
R103
208BGA
R6
CAUTION
Please ensure that any solder modifications to the daughter cards are carried out in
an anti-static environment with the correct equipment and personnel for the job.
4.2.2
Main Clock Configuration
Each daughtercard contains a local crystal oscillator circuit and jumpers to allow the source of the clock to be selected
from either the EVB or from the local crystal circuit.
MPC5510EVB Clock Circuitry
Oscillator
Module
(Y1)
Daughtercard Clock Circuitry
3.3V
J39
1
Y2
EXTAL
J40
SMA
(P27)
J3
Y1
SMA
OSC SEL
1
XTAL
Page 25 of 36
Y2
GND
Local Crystal
Circuit (Y2)
Figure 4-3 Daughtercard Clock Selection
MPC5510EVBUM/D
EXTAL
EVB
Y2 PWR
1
MCU
J4
XTAL
MPC5510EVB User Manual Rev 1.0
Sept 2007
Table 4-2 Daughtercard Clock Selection
Jumper
J3
XTAL
J4
EXTAL
Position
1-2 (D)
2-3
1-2 (D)
2-3
PCB Legend
Y2
GND
Y2
EVB
Description
Clock is sourced from daughtercard crystal circuit
XTAL is grounded. Use when J4 is in posn 2-3
Clock is sourced from daughtercard crystal circuit
Clock is sourced from EVB clock (oscillator or SMA)
The default configuration uses the local daughtercard clock. If you wish to drive a clock into the MCU EXTAL line from
the EVB (either via the SMA connector or using the 8Mhz oscillator module), move both the EXTAL and XTAL
jumpers to position 2-3.
4.2.3
32Khz Clock Configuration
The MPC5510 supports an optional 32Khz oscillator circuit used to drive an RTC (Real Time Counter). The 32Khz clock
circuitry is populated on the daughtercard with 2 jumpers to allow selection of the 32Khz oscillator if required.
MPC5510EVB Clock Circuitry
Daughtercard Clock Circuitry
1
User
Connectors
J2
MCU
PK0 / PA14
EXTAL32
Y1
1
XTAL32
EXTAL32
J1
PK1 / PA15
Y1
Local Crystal
Circuit (Y1)
XTAL32
Figure4-4 Daughtercard 32Khz Clock Selection
Table 4-3 Daughtercard 32KHz Clock Selection
Jumper
J1
XTAL32
J2
EXTAL32
Position
1-2 (D)
2-3
1-2 (D)
2-3
PCB Legend
PK0 / PF14
Y1
PK1 / PF15
Y1
Description
MCU pin is routed to EVB user connectors
MCU pin is connected to 32Khz crystal
MCU pin is routed to EVB user connectors
MCU pin is connected to 32Khz crystal
The default configuration has the MCU EXTAL32 / XTAL32 pins connected to the MCU ports (PortH or PortF
depending on the package used). If you wish to use the 32KHz crystal, jumpers J1 and J2 must both be moved to position
2-3.
MPC5510EVBUM/D
Page 26 of 36
MPC5510EVB User Manual Rev 1.0
4.2.4
Sept 2007
CLKOUT Impedance Matching Control
The MCU PE6/CLKOUT line has a 33ohm series resistor close to the MCU in order to provide CLKOUT impedance
matching. If required, this resistor can be shorted out (bypassed) by fitting a jumper header. To minimise the effect of
radiated emissions, it is recommended this jumper is removed when PE6 is used for CLKOUT.
Table 4-4 Clkout Impedance Matchuing
Jumper
J5
CLKOUT
DISABLE
Position
PCB Legend
Description
FITTED
MCU PE6 has no series termination
REMOVED (D)
MCU PE6 has in line 33ohm series resistor.
By default the jumper is removed to enable CLKOUT impedance matching. To disable impedance matching, fit the
jumper.
CAUTION
Fitting daughtercard jumper J5 when CLKOUT is enabled on MCU PE6 will result in
increased radiated emissions. Ensure this jumper is removed when CLKOUT is active.
4.2.5
Power LED
There is a green power LED fitted to the top left corner of the daughtercard. If the daughtercard is connected to the EVB
and power is applied, this LED should illuminate. If the LED does not illuminate, please check the daughtercard is
installed correctly and follow the main EVB power fault-finding tips detailed in section 3.1.4
5. MCU Pin Usage Map
The table below provides a useful cross reference to see what MCU port pins are used by the various EVB peripherals
and functions. Note that there are some overlapping functions for example the Nexus and External bus as shown by the
shaded boxes in the table below.
Table 5-1 EVB MCU Pin Usage
Function
PortA
Enabled By Default
Nexus
CANA
CANC
SCI / LINA
SCI / LINB
Reset Config
Led Matrix
PA[0]
User RVAR
Disabled By Default
SRAM
Flexray A
Flexray B
MPC5510EVBUM/D
PortB
PortC
PortD
PortE
PortF
PE[6]
PF0..11]
PE[6]
PF[0..15]
PortG
PortH
PortJ
PG[0..15]
PH[14,15]
PJ[0..7]
PD[0..1]
PD[4..5]
PD[6..7]
PD[8..9]
PD[2]
PC[0..11]
PC[0..2]
PC[7..9]
Page 27 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
6. Default Jumper Summary Table
The following table details the DEFAULT jumper configuration of the EVB as explained in detail in section 3.
Table 6-1 Default Jumper Positions
Jumper
Default Posn
J1 (LINB-M)
J2 (LINA-M)
FITTED
FITTED
1-2
3-4
1-2
3-4
FITTED
FITTED
FITTED
FITTED
FITTED
2-4
1-3
2-4
1-3
REMOVED
1-2
3-4
5-6
7-8
REMOVED
1-2
3-4
5-6
7-8
REMOVED
FITTED
1-2
1-2
1-2
3-4
REMOVED
FITTED
1-2
3-4
REMOVED
REMOVED
FITTED
REMOVED
1-2
1-2
1-2
1-2
1-2
REMOVED
1-2
1-2
J3 (CAN-A)
J4 (CAN-C)
J5 (LINB-EN)
J6 (LINA-EN)
J7 (VDD-CAN)
J8 (RV1)
J9 (SCI-PWR)
J10 (SCI-A)
J11 (SCI-B)
J12 (Flex-A)
J13 (Flex-A)
J14 (Flex-B)
J15 (Flex-B)
J16 (Flex-PWR)
J17 (RST-IN)
J18 (VIO)
J19 (BOOT CFG)
J20
J21 (VDD15)
J22 (SRAM PWR)
J23 (LED-Enable)
J24 (VEND-IO)
J25 (VDDSYN)
J26 (EIM Pullup)
J27 (VDD33)
J28 (TCLK PULL)
J29 (VDDE3)
J30 (VDDE2)
J31 (JRST)
J31B (PFO SEL)
J32 (GAL-PWR)
J33 (VDDE1)
J34 (VDDE SEL)
MPC5510EVBUM/D
PCB Legend
TX
RX
TX
RX
TXD
RXD
TXD
RXD
BGE
EN
STBEN
WAKE
BGE
EN
STBEN
WAKE
5V
FSH
MAIN
LINEAR
HIGH
LOW
5V
FRM J34
FRM J34
BUFFER
EVTI
FRM J34
5V-S
Description
LIN-B transceiver is configured for LIN Master mode
LIN-A transceiver is configured for LIN Master mode
MCU CNTX-A is connected to CAN controller A
MCU CNRX-A is connected to CAN controller A
MCU CNTX-C is connected to CAN controller C
MCU CNRX-C is connected to CAN controller C
The LIN-B transceiver is enabled
The LIN-A transceiver is enabled
Power is applied to both CAN transceivers
Output from variable resistor RV1 is applied to MCU PA0
Power is applied to the MAX232 transceiver
MCU TXD-A is routed via MAX232 to P5
MCU RXD-A is routed via MAX232 to P5
MCU TXD-B is routed via MAX232 to P6
MCU RXD-B is routed via MAX232 to P6
All 3 shunts removed. No MCU signals connected to Flexray
Flexray-A interface BGE signal is pulled to VIO
Flexray-A interface EN signal is pulled to VIO
Flexray-A interface STBN signal is pulled to VIO
Flexray-A interface WAKE signal is pulled to GND
All 3 shunts removed. No MCU signals connected to Flexray
Flexray-B interface BGE signal is pulled to VIO
Flexray-B interface EN signal is pulled to VIO
Flexray-B interface STBN signal is pulled to VIO
Flexray-B interface WAKE signal is pulled to GND
All 3 flexray power supply voltages are disconnected
External reset source can assert MCU reset
MCU boots from internal flash
5.0V switching regulator is monitored, Reset switch active
5.0V linear regulator is monitored
MCU VDD pin is not powered externally
The SRAM and latches are powered
MCU PortC[10..11] signals are connected to LED Matrix
MCU PortC[1..9] signals are connected to LED Matrix
Vendor I/O2 pin can drive BOOTCFG at reset
MCU VDDSYN pin is not powered externally
The external bus pull-up resistors are powered (enabled)
MCU VDD33 pin is not powered externally
JTAG / NEXUS TCLK signal is pulled to 5.0V via 10KΩ
MCU VDDE3 is powered from output of J34
MCU VDDE2 is powered from output of J34
JTAG reset signal is buffered to MCU RESET pin
PFO is routed to Nexus for use as EVTI
The control PLD is not powered (disabled)
MCU VDDE1 is powered from output of J34
VDDEx jumpers are supplied from 5V switching regulator
Page 28 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
Default Jumper Positions Continued
Jumper
Default Posn
PCB Legend
Description
J35
J36 (VPP)
J37 (VDDR)
J38 (VDDA)
J39 (Y1 PWR)
J40 (OSC SEL)
J41 (SBC-PWR)
J42 (5.0V-LINEAR)
J43 Not Impelemted
J44 (1.5V)
J45 (3.3V)
J46 (5.0V)
2-4
1-2
1-2
1-2
FITTED
1-2
REMOVED
FITTED
CS0 / 16-Bit
5V-S
5V-S
5V-L
ENABLE
MCU chip select 0 is used to control 16-bit SRAM
MCU VPP is powered from 5.0V switching regulator
MCU internal VREG is powered from 5.0V switching reg
MCU VDDA is powered from 5V linear regulator
EVB oscillator module Y1 is powered
Daughter card EXT-CLK is routed from Y1
SBC linear regulator output is Disabled
5.0V linear regulator output is Enabled
REMOVED
REMOVED
REMOVED
DISABLE
DISABLE
DISABLE
1.5V switching regulator output is Enabled
3.3V switching regulator output is Enabled
5.0V switching regulator output is Enabled
MPC5510EVBUM/D
Y1
Page 29 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
The user connectors are
located on the right hand side
of the PCB
7. User Connector Descriptions
This section details the pinout of the EVB user connectors. The connectors are 0.1 inch pitch turned pin headers and are
located to the right hand side of the EVB. Pins are grouped by port functionality and the PCB legend shows the
respective port number adjacent to each pin.
Shaded GREEN areas represent pins that are shared with the Nexus port
Shaded BLUE areas represent a GPIO pin that is also used on the EVB for another purpose
Note that not all of the port functionality is available on all of the derivatives. Please consult your particular MCU
documentation for details on available ports.
7.1.1 Port A / ADC (Connector P16, RV1 and J8)
Table 7-1 Port A Connector Pinout (P16)
Pin
1
3
5
7
9
11
13
15
17
Function
GPIO
1st Alt
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
AN0
AN2
AN4
AN6
AN8
AN10
AN12
AN14
GND
144
9
9
9
9
9
9
9
9
Availability
176
208
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Pin
2
4
6
8
10
12
14
16
18
Function
GPIO
1st Alt
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
AN1
AN3
AN5
AN7
AN9
AN11
AN13
AN15
GND
Availability
208
144
176
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
To provide a quick means of supplying input to the ATD (Analogue To Digital converter), a 2KΩ variable resistor (RV1)
will be connected between P5V and GND, with the output (centre tap) connected to PA0 / AN0 via jumper J8. By
removing jumper J8, PA0 is disconnected from the variable resistor and can function as a normal I/O port. J8 and RV1
are located in the top right hand corner of the EVB
Jumper
J8
(RV1)
Table 7-2 RV1 Connection Jumper J8
PCB Legend
Description
Output from variable resistor RV1 is applied to MCU PA0
Output from RV1 is not connected to MCU (disabled)
Position
FITTED (D)
REMOVED
Note - PA14 and PA15 can also be used for the EXTAL32 and XTAL32 32Khz reference clock. If these pins are used for
this purpose, they will not be available for GPIO / ADC input. See section 4.2.3 for details.
7.1.2 Port B / ADC / SCI (P30)
Table 7-3 Port B Connector Pinout (P30)
Pin
Function
GPIO
1st Alt
1
3
5
7
9
11
13
15
17
MPC5510EVBUM/D
PB0
PB2
PB4
PB6
PB8
PB10
PB12
PB14
AN28
AN30
AN32
AN34
AN36
AN38
TXD_G
TXD_H
GND
144
9
9
9
9
9
9
Availability
176
208
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Pin
2
4
6
8
10
12
14
16
18
Page 30 of 36
Function
GPIO
1st Alt
PB1
PB3
PB5
PB7
PB9
PB11
PB13
PB15
AN29
AN31
AN33
AN35
AN37
AN39
RXD_G
RXD_H
GND
Availability
144
9
9
9
9
9
9
176
9
9
9
9
9
9
9
9
208
9
9
9
9
9
9
9
9
MPC5510EVB User Manual Rev 1.0
Sept 2007
7.1.3 Port C / ADC / SCI (P24)
Table 7-4 PortC Connector Pinout (P24)
Pin
1
3
5
7
9
11
13
15
17
Function
GPIO
1st Alt
PC0
PC2
PC4
PC6
PC8
PC10
PC12
PC14
eMIOS[0]
eMIOS[2]
eMIOS[4]
eMIOS[6]
eMIOS[8]
eMIOS[10]
eMIOS[12]
eMIOS[14]
GND
Availability
144
176
208
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Pin
2
4
6
8
10
12
14
16
18
Function
GPIO
1st Alt
PC1
PC3
PC5
PC7
PC9
PC11
PC13
PC15
eMIOS[1]
eMIOS[3]
eMIOS[5]
eMIOS[7]
eMIOS[9]
eMIOS[11]
eMIOS[13]
eMIOS[15]
GND
Availability
144
9
9
9
9
9
9
9
9
176
9
9
9
9
9
9
9
9
208
9
9
9
9
9
9
9
9
Notes:
- PC[0..11] is used to drive the LED dot matrix display if enabled. See section 3.10 for details.
- PC[0..2] and PC[7..9] are also used for the flexray interface. See section 3.9 for details.
7.1.4 Port D / CAN / SCI / SPI (P15)
Table 7-5 PortD Connector Pinout (P15)
Pin
1
3
5
7
9
11
13
15
17
Notes:
-
Function
GPIO
1st Alt
PD0
PD2
PD4
PD6
PD8
PD10
PD12
PD14
CNTX_A
CNRX_B
CNTX_C
TXD_A
TXD_B
PCS_B[2]
PCS_B[0]
SOUT_B
GND
Availability
144
176
208
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Pin
2
4
6
8
10
12
14
16
18
Function
GPIO
1st Alt
PD1
PD3
PD5
PD7
PD9
PD11
PD13
PD15
CNRX_A
CNTX_B
CNRX_C
RXD_A
RXD_B
PCS_B[1]
SCK_B
SIN_B
GND
Availability
144
9
9
9
9
9
9
9
9
176
9
9
9
9
9
9
9
9
208
9
9
9
9
9
9
9
9
PD2 is used for BOOTCFG data. See section 3.3.3
PD0, PD1, PD4 and PD5 are used for the EVB CAN interface. See section 3.6
PD6, PD7, PD8 and PD9 are used on the EVB SCI / LIN Physical Interfaces. See sections 3.7 and 3.8
PD12, PD13, PD14, PD15 are used by the SBC SPI communication. See section 3.1.5
7.1.5 PortE / SPI / eMIOS / EIM (Connector P31)
Table 7-6 PortE Connector Pinout (P31)
Pin
1
3
5
7
9
11
13
15
17
Function
GPIO
1st Alt
PE0
PE2
PE4
PE6
PE8
PE10
PE12
PE14
PCS_A[2]
PCS_A[0]
SOUT_A
CLKOUT
eMIOS[24]
eMIOS[26]
eMIOS[28]
eMIOS[30]
GND
Availability
144
176
208
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Pin
2
4
6
8
10
12
14
16
18
Function
GPIO
1st Alt
PE1
PE3
PE5
PE7
PE9
PE11
PE13
PE15
PCS_A[1]
SCK_A
SIN_A
--eMIOS[25]
eMIOS[27]
eMIOS[29]
eMIOS[31]
GND
Availability
144
9
9
9
176
9
9
9
9
9
9
208
9
9
9
9
9
9
9
9
Note – Port PE6 has a 33ohm series resistor close to the MCU on the MCU daughter-card to provide some CLKOUT
impedance matching. This can be disabled with a jumper if required. See the daughter-card user manual for details.
MPC5510EVBUM/D
Page 31 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
7.1.6 Port F / EIM (Connector P17)
Table 7-7 Port F Connector Pinout (P17)
Pin
1
3
5
7
9
11
13
15
17
Notes
-
Function
GPIO
1st Alt
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
RD_WR
AD[8]
AD[10]
AD[12]
AD[14]
CS[1]
TS
WE[0]
GND
Availability
144
176
208
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Pin
2
4
6
8
10
12
14
16
18
Function
GPIO
1st Alt
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
TA
AD[9]
AD[11]
AD[13]
AD[15]
CS[0]
OE
WE[1]
GND
Availability
144
9
9
9
9
9
9
9
9
176
9
9
9
9
9
9
9
9
208
9
9
9
9
9
9
9
9
PF[0..15] are used to drive the EBI. See section 3.5
PF[0..11] are used for the Nexus interface. When using Nexus, the EBI must be disabled and nothing connected
to these GPIO pins. See section 3.4
7.1.7 Port G / EIM (Connector P25)
Table 7-8 Port F Connector Pinout (P25)
Pin
1
3
5
7
9
11
13
15
17
Function
GPIO
1st Alt
PG0
PG2
PG4
PG6
PG8
PG10
PG12
PG14
AD[16]
AD[18]
AD[20]
AD[22]
AD[24]
AD[26]
AD[28]
AD[30]
Availability
144
176
208
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Pin
2
4
6
8
10
12
14
16
18
GND
Function
GPIO
1st Alt
PG1
PG3
PG5
PG7
PG9
PG11
PG13
PG15
AD17]
AD[19]
AD[21]
AD[23]
AD[25]
AD[27]
AD[29]
AD[31]
Availability
144
9
9
9
9
9
9
9
9
176
9
9
9
9
9
9
9
9
208
9
9
9
9
9
9
9
9
GND
Note – PG[0..15] are used to drive the EBI. See section 3.5
7.1.8 Port H / ADC / API / EIM (Connector P29)
Table 7-9 Port H Connector Pinout
Pin
1
3
5
7
9
11
13
15
17
Function
GPIO
1st Alt
PH0
PH2
PH4
PH6
PH8
PH10
PH12
PH14
AN[27]
AN[25]
AN[23]
AN[21]
AN[19]
AN[17]
PCS_D[5]
WE[2]
GND
Availability
144
176
208
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Pin
2
4
6
8
10
12
14
16
18
Function
GPIO
1st Alt
PH1
PH3
PH5
PH7
PH9
PH11
PH13
PH15
AN[26]
AN[24]
AN[22]
AN[20]
AN[18]
AN[16]
--WE[3]
GND
Note – PH[14..15] are used to drive the EBI (32-bit data port mode). See section 3.5
MPC5510EVBUM/D
Page 32 of 36
Availability
144
9
9
9
9
9
9
176
9
9
9
9
9
9
9
208
9
9
9
9
9
9
9
9
MPC5510EVB User Manual Rev 1.0
Sept 2007
7.1.9 Port J / EIM / SPI (Connector P23)
Table 7-10 Port J Connector Pinout
Pin
1
3
5
7
9
11
13
15
17
Function
GPIO
1st Alt
PJ0
PJ2
PJ4
PJ6
PJ8
PJ10
PJ12
PJ14
AD[0]
AD[2]
AD[4]
AD[6]
PCS_D[4]
PCS_D[2]
PCS_D[0]
SOUT_D
GND
Availability
144
176
208
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Pin
2
4
6
8
10
12
14
16
18
Function
GPIO
1st Alt
PJ1
PJ3
PJ5
PJ7
PJ9
PJ11
PJ13
PJ15
AD[1]
AD[3]
AD[5]
AD[7]
PCS_D[3]
PCS_D[1]
SCK_D
SIN_D
GND
Availability
144
176
9
9
9
9
9
9
208
9
9
9
9
9
9
9
9
Note –PJ[0..7]are used to drive the EBI (32-bit data port mode). See section 3.5
7.1.10 Port K / EXTAL32 / XTAL32 (Connector P33)
Table 7-11 Port K Connector Pinout
Pin
1
17
Function
GPIO
1st Alt
PK0
EXTAL32
GND
Availability
100
144
208
9
Pin
2
18
Function
GPIO
1st Alt
PK1
EXTAL32
GND
Availability
208
100
144
9
Note – The EXTAL32 and XTAL32 function is available on pins PA14 and PA15 for all packages that do not provide
PortK.
MPC5510EVBUM/D
Page 33 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
7.2 Prototyping Area and User LED’s / Switches
The prototyping area is located
on the right hand side of the
EVB, above the user
connectors.
There is a rectangular prototype area on the EVB, consisting of a 0.1inch pitch array of through-hole plated pads. Power
from all three voltage regulators is readily accessible along with GND. This area is ideal for the addition of any custom
circuitry. Adapters are available to convert SMD devices to 0.1inch pitch through-hole.
Note the power supply lines to the prototype area are connected directly to the regulator outputs and not connected to
the jumpered MCU supply.
There are 4 active low user LED’s DS4, DS5, DS6 and DS7, These are driven by connecting a logic 0 signal to the
corresponding pin on 0.1” header P10 (user LED’s).
There are 4 active high pushbutton switches SW2, SW3, SW4 and SW5 which will drive 5V onto the respective pins on
0.1” connector P11 when pressed. The switch outputs are pulled to GND with a 10K resistor network.
MPC5510EVBUM/D
Page 34 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
8. Daughter Card Connectors (P9, P22)
The daughter card connectors
are located roughly in the
centre of the board. .
As mentioned previously, there are two 120-way expansion connectors fitted to the EVB, allowing connection of an
MCU daughter card or another board providing functionality enhancement.
The part numbers of possible connectors are detailed in Table 8-1 below.
Table 8-1 Expansion Connector Part Numbers
Connector Location
EVB
Daughter Card
Height
8mm
9mm
13mm
Pitch
0.8mm
0.8mm
0.8mm
TYCO / AMP Part Number
179031-5
5-179009-5
5-179010-5
The pinout of the expansion connectors is detailed below for reference.
Table 8-2 Daughter Card Connector 1
Pin
Number
Signal
Name
(0dd)
Signal
Name
(Even)
Pin
Number
Signal
Name (0dd)
Signal Name
(Even)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
PB2
PK0
PA8
VDDA
VDD
3.3V-SR
PB13
VDD
PA12
PB4
PA15
GND
PA6
PB5
PA14
PA10
PA4
GND
-PA1
PH10
PH11
PH13
GND
PH9
VDDE2
PJ11
PJ12
PJ10
GND
PB12
PA13
3.3V-SR
VDDA
VDD
PB3
PK1
VDD
GND
PB0
PA11
PA9
PA7
PB1
GND
PA3
PA5
MCU-RST
PA0
PA2
GND
PH12
PJ13
PJ14
PJ15
VDDE2
GND
PH8
PH5
PH6
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
PH7
PH4
PJ9
VDDE2
PH0
GND
PG12
PG14
PF8
PF12
VDDE2
GND
PG10
PF7
PF14
PG0
VDDE2
5.0V-SR
PJ7
PF13
PG2
PG5
VDD
P12V
PF9
VDDR
PG1
PG4
VDD
TGT-RST
PH3
PJ8
GND
VDDE2
PH1
PH2
PG13
PG15
GND
PF15
VDDE2
PG9
PG11
PF11
GND
PG3
VDDE2
PG8
PF10
PH15
5.0V-SR
PG7
VDD
PF6
PH14
VDDR
P12V
PG6
VDD
RST-OUT
MPC5510EVBUM/D
Page 35 of 36
MPC5510EVB User Manual Rev 1.0
Sept 2007
Table 8-3 Daughter Card Connector 2
Pin
Number
Signal
Name
(0dd)
Signal
Name
(Even)
Pin
Number
Signal
Name (0dd)
Signal Name
(Even)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
PB6
PB15
PC7
VDDE1
VDD
GND
PB7
PC0
PC8
VDD
PC11
GND
PB14
PC5
PC13
PC14
VDDE1
GND
PC6
PD0
PD2
VDDE1
PD3
GND
PD6
PD9
PD10
VDDE1
PD11
PE7
PB10
PC3
GND
VDDE1
VDD
PC10
PB11
PC4
GND
VDD
PC12
PB8
PC1
PC9
GND
PB9
VDDE1
PC2
PC15
PD1
GND
VDDE1
PD4
PD5
PD7
PD8
GND
VDDE1
PD12
PD13
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
PE8
PD14
PE10
PE12
VDDE1
GND
PE13
PE2
PE3
PE15
VDDE3
GND
PJ0
VDD33
PE4
CLK-IN
PJ4
GND
VPP
PE6
PJ3
PF2
VDD
1.5V-SR
VDDSYN
PJ5
VDDE3
VDDE3
JCOMP
TMS
PE9
PE11
GND
PD15
VDDE1
PE0
PE1
PE14
GND
PE5
VDDE3
PJ2
PF0
VDD33
GND
PJ6
PJ1
PF1
VPP
PF5
GND
TDI
VDD
TCLK
VDDSYN
PF4
1.5V-SR
PF3
TDO
VDD
Notes:
- Power connections shown with red shading are from the outputs of the respective MCU power jumpers. The
power connections shown in orange shading (1.5V-SR, 3.3V-SR, 5.0V-SR and P12V) are direct outputs from the
regulators / main power input and are not jumpered. These are designed to drive any non-MCU daughter card
circuitry.
- The TGT-RESET signal provides a mechanism of driving the MCU reset line from a non open-drain source.
This can be used by a target system to control the system reset. RST-OUT is a driven reset signal which should
be connected to Reset-in of any custom devices on the daughter card. The MCU-Reset line provides a direct
connection to the bidirectional MCU Reset pin. Extreme caution should be exercised if this pin is used.
- All of the MCU signals with the exception of VRH, VRL, EXTAL, XTAL, and REFBYPC, are routed to the
connectors.
MPC5510EVBUM/D
Page 36 of 36
MPC5516EVBUM/D
Appendix ID
Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F Appendix G Appendix H -
Description
EVB Schematics (Rev E0)
EVB Bill Of Materials
144QFP Daughtercard Schematics (Rev B1)
144QFP Daughtercard Bill Of Materials
176QFP Daughtercard Schematics (Rev C0)
176QFP Daughtercard Bill Of Materials
208BGA Daughtercard Schematics (Rev B1)
208BGA Daughtercard Bill Of Materials
Page B-1
The EVB and daughtercard BOM (Bill of Materials) and Schematics are detailed in the Appendix as shown below.
Appendix
MPC5516EVB User Manual Rev 1.0
Sept 2007
SHEET 2
SHEET 3
SHEET 4
SHEET 5
SHEET 6
SHEET 7
SHEET 8
SHEET 9
SHEET 10
SHEET 11
SHEET 12
SHEET 13
SHEET 14
MPC5516EVBUM/D
Specific PCB LAYOUT notes are detailed in ITALICS
User notes are given throughtout the schematics.
- Test Point Vias are denoted TPVx
- All test points are denoted TPx
- All Switches are denoted SWx
Page B-2
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2
- All jumpers are denoted Jx. Jumpers are 2mm pitch
- All connectors are denoted Px. All connectors and headers are 2.54mm pitch unless otherwise stated
- All decoupling caps greater than 0.1uF are X7R unless otherwise stated
- All decoupling caps less than 0.1uF are COG unless otherwise stated
- Variable resistors are denoted RVx
Revision Information
Rev Date
0.1 10 Dec 2006
0.2 03 Jan 2007
B0 03 Jul 2007
C0 11 Jul 2007
D0 31 Jul 2007
D1 07 Aug 2007
D2 10 Sept 2007
E0 12 Sept 2007
Comments
Provisional (Pre Back Annotation)
Additional power on DC. Proto Release - PCB RevA
FCL Prodn Release - PCB RevB
Fixed connectivity on Power Jack (P28)
Changed Power Supply Caps (C13, C14, C15 & C20)
Changed P3 and P4 from 2mm to 2.54mm
Post FCL Tidy Up. Correction to J13 / J15
Released to Production - PCB RevE
Page Title:
Size
B
Drawn by :
A. Robertson
Approv ed:
A. Robertson
Date: Wednesday , September 12, 2007
SCH-23130
Sheet
1
PDF: SPF-23130
Front Page Contents and Notes
MPC5510 Evaluation Board
Document Number
Drawing Title:
Designer:
A. Robertson
of
14
MCD Applications East Kilbride
Colv illes Road, Kelv in Industrial Estate, East Kilbride G75 0TG
Transportation & Standard Products Group
These schematics are provided for reference purposes only. As
such, Freescale does not make any warranty, implied or
otherwise, as to the suitability of circuit design or component
selection (type or value) used in these schematics for hardware
design using the Freescale MPC5510 family of
Microprocessors. Customers using any part of these schematics
as a basis for hardware design, do so at their own risk and
Freescale does not assume any liability for such a hardware
design.
Note:
Designer
A. Robertson
A. Robertson
A. Robertson
A. Robertson
A. Robertson
A. Robertson
A. Robertson
A. Robertson
MPC5510 Evaluation Board
- Resistor networks are donated RNx. All resistor networks are SMD 1206 style package.
- All components and board processes are to be ROHS compliant
Notes:
POWER SUPPLY 1 (INPUT, LINEAR AND SWITCHERS)
POWER SUPPLY 2 (SBC AND VOLTAGE ROUTING)
EVB CLOCK OSCILLATOR AND SMA CONNECTORS
RESET GENERATION, CONTROL AND BOOTCFG
JTAG AND NEXUS CONNECTORS
SRAM
CAN TRANSCEIVERS
SCI AND LIN TRANSCEIVERS
FLEXRAY TRANSCEIVERS
DAUGHTERCARD CONNECTORS
USER IO CONNECTORS (PORT HEADERS)
USER (PROTOTYPE) AREA AND I/O PEIPHERALS
TERMINATION RESISTORS
Table Of Contents:
Appendix A - EVB Schematics
MPC5516EVB User Manual Rev 1.0
Rev
E0
Sept 2007
P32
B
A
1
2
3
2
1
GND
P12V
GND
1
J42
12V-IN
TP5
1
TP4
1
TP3
1
TP2
1
1
VIN
U19
LM2937-5.0
VO
3
TP10 TP11
GND
PT10
PT9
PT8
PT7
PT6
VFused
2
PT15
PT14
PT13
PT12
1
1
1
1
PT20
PT19
PT18
PT17
PT16
1
1
1
1
1
PT5
PT4
PT3
PT2
PT1
5.0V_SR
TP12
R45
GND
1
1
1
1
1
P12V
Page B-3
P12V_R
Nexus Connector
Power Monitor
100 OHM
GND
C16
1000UF
5.0V_LR
+
P12V
Protoype Area Reference Points
1
1
1
1
1
PT11
LED GREEN
DS10
R42
560 OHM
C12
68UF
1
1
C20
100uF
+
3.3V_SR
+
D3
2
L3 47UF
1.5V_SR
Fuse Holder
C84
1000PF
1
5V LinearRegulator
C79
0.1 UF
1
C83
0.1 UF
VSwitched
F1
Main Power-In
GND
GND
GND
C17
3.3UF
R46 1.80K
C18
3.3UF
C19
4.7uF
J44
2
J45
J46
5
7
6
2
LM2676S-5.0
LM2676S-3.3
ON/OFF SW_OUT
FEEDBACK
ON/OFF SW_OUT
FEEDBACK
NC
1
3
C81
D6
0.1 UF
R44
1.2K
L4 68UH
L6 47UF
D7
0.1 UF
Date:
Size
B
Title
100UH
L5
R41 68 OHM
+
+
+
3
2
R47
R48
GND
2
Q3 BSH103
LED GREEN
DS12
C13
100uF
GND
1
2
LED GREEN
DS13
C14
100uF
1
C15
100uF
TP13
1.5V_SR
TP14
3.3V_SR
TP15
5.0V_SR
Sheet
(MPC5510EVB)
Tuesday , September 11, 2007
Document Number
Drawing SCH-23130
2
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
1.5V Switching Regulator
1
C82
R43 220 OHM
Vout = 1.21(1 + R2/R1)
(R2 = 2 Ressitors in series)
LM2676S-ADJ
3
INPUT C_BOOST
U20
D8
0.1 UF
3.3V Switching Regulator
1
NC
1
C80
5V Switching Regulator
INPUT C_BOOST
U21
NC
ON/OFF SW_OUT
FEEDBACK
3
Switching Regulators
INPUT C_BOOST
U22
LED GREEN
DS11
5
7
6
2
5
7
6
2
Sept 2007
Rev
E0
POWER SUPPLY 1 (Input and Non-SBC)
B130LB-13
MPC5516EVBUM/D
TP6
1
GND Test Points
TP9
TP8
TP7
1
TP1
2
POWER SWITCH
1
Test and reference points
2 Lever
Connector
P28
2.1mm Barrel
Connector
5
1
Power supply input and filter
1
GND
GND
2
4
1
2
SW6
G-107-0513
1
3
4
2
1
1
2
1
2
1
1
MPC5516EVB User Manual Rev 1.0
1
GND
TAB
4
8
GND
TAB
4
8
1
GND
TAB
4
8
1
2
1
2
1
2
B130LB-13
270 OHM
2
B130LB-13
1
B130LB-13
1
560 OHM
MCU-RSTx
PD[0..15]
MCU DSPI-B
PA[0..15]
(MCU ADC)
MPC5516EVBUM/D
5,8,9,11,12 PD[0..15]
5,6,11
11,12,13 PA[0..15]
1
2
3
4
5
1
3
5
7
9
11
J43
2
4
6
8
10
12
SBC-IO0
SBC-IO1
SBC-SAFE
SBC-DBG
SBC-INT
GND
GND
R53
0 OHM
SBC-M
SBC-R
SBC-CS
SBC-SCLK
SBC-MOSI
SBC-MISO
R52 10K
2
TPV24
PD14 - MASTER SERIAL OUT (SLAVE IN)
PD15 - MASTER SERIAL IN (SLAVE OUT)
PA1 (AN1)
MCU-RSTx
PD12 (PCS-B0)
PD13 (SCK-B)
PD14 (SOUT-B)
PD15 (SIN-B)
P18
1
24
25
26
27
23
22
5
16
14
21
15
3
SBC
MCU SPI COMMS
MC33905S
CSB
SCLK
MOSI
MISO
INT
RST
SAFE
DBG
MUX-OUT
IO-1
IO-0
IO-3
U18
R37 1.0K
C8
4.7uF
20
Vsense
1
VSUP
2
GND
VSUP1
J41
0.1 UF
0.1 UF
C74
C72
5V-CAN
VDD
VBASE
VEM
Vaux
VCaux
VBaux
GND
LIN
Transceiver
LIN
TXD-L
RXD-L
LIN-T
CAN
RXD
Transceiver
TXD
and Regulator CANL
SPLIT
CANH
External
VDD
transistor
External Vaux
transistor
VINaux
0.1 UF
C76
Q2
BCP52-16
Q1
R40 1.0K
Page B-4
SBC-LIN2
SBC-LIN2TX
SBC-LIN2RX
4
17
18
19
SBC-CNRX
SBC-CNTX
SBC-CANL
SBC-SPLIT
SBC-CANH
SBC-VDD
(5.0V)
SBC-VCAN
(5.0V)
1
D4 GF1A
2
1
30
29
8
10
7
6
28
VB
VE
31
32
SBC-VAUX
(3.3V / 5.0V)
13
1
VCaux
VBaux
12
11
3
P12V
B
MPC5516EVB User Manual Rev 1.0
3
2
4
E
C
TAB
GND_CAN
B
2
4
4
3
2
1
1
2
3
GND
P26
C77
C11
C75
C10
C78
C9
+
+
+
E
C
33
9
BCP52-16
GND
GND
60.4OHM
60.4OHM
SBC-VAUX 3
(SBC 3.3/5V)
1
(5v Switcher)
J34
2
SBC-VCAN
3
1
3
1
3
(1.5v Switcher)
(3.3v Switcher)
(3.3v Switcher)
(3.3v Switcher)
1
1
1
3
V3.3-5.0
1
(5v Switch / SBC)
(3.3v Switcher)
V3.3-5.0
1
(5v Switch / SBC)
(3.3v Switcher)
3
V3.3-5.0
1
(5v Switch / SBC)
(SBC 5v CAN)
(5v Switcher)
(SBC 5v Main)
SBC-VDD
(5v Switcher)
J21
J25
J27
J29
J30
J33
J36
J37
(5v Linear)
J38
1
SBC-VDD
3
(SBC 5v Main)
5.0V_LR
VDDR
(On Chip
Regulator)
VDDA
(ADC Supply)
VDDR
VDDA
2
2
2
VDDSY N
VDDSY N
VDD33
VDDE3
VDDE2
VDD15
2
(MCU core supply when
NOT using VReg)
2
2VDD33
VDDE3
(I/O Segment 3)
VDDE2
(I/O Segment 2)
VDDE1
(I/O Segment 1) VDDE1
VPP
2
(Flash Programming) VPP
2
2
VDD15
11
11
11
11
11
11
11
11
Date:
Size
B
Title
Sheet
(MPC5510EVB)
Monday , September 10, 2007
Document Number
Drawing SCH-23130
3
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
VDDR jumper MUST be in posn 2-3 when VDD33, VDDSYN or VDD15 jumpers are fitted
P19
C71
2200PF
R34
R35
0.1 UF
GND
10UF
0.1 UF
10UF
0.1 UF
10UF
5.0V_SR
3.3V_SR
1.5V_SR
Rev
E0
11
POWER SUPPLY 2 (SBC and Routing Jumpers)
Sept 2007
MPC5516EVBUM/D
SMA style
Connector
SMA style
Connector
Note - Internal
Pull-Up on Pin 1
P21
P27
1
FB1
1
gnd
Vdd
1
1
CLK
OUT
2
1
1
FB2
FB3
GND
3
R38
Y1
0.1 UF
8MHz
C73
4
2
MPC5516EVB User Manual Rev 1.0
3
2
4
5
3
2
4
5
J39
2
2
100 OHM
2
3
1
GND
PE[0..15]
(PE6 CLKOUT)
EVB-EXTAL
2
(To Daughter Card)
PE[0..15]
EVB-EXTAL
Note - External 3.3V
regulator MUST be
enabled when using
oscillator module
J40
3.3V_SR
(CLKOUT) PE6
From daughter card
GND
EXTAL-SMA
OSC-MOD
1
Page B-5
6,7,11,12
11
Date:
Size
B
Title
Sheet
(MPC5510EVB)
Monday , September 10, 2007
Document Number
Drawing SCH-23130
4
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
Rev
E0
CLOCK CIRCUITRY
Sept 2007
MPC5516EVBUM/D
GND
SW1
KS11R23CQD
2
GND
(Approx 1.4V Out)
GND
0.1 UF
11,12 TGT-RSTx
C52
5.0V_SR
R23
4
470 OHM
R22
1.2K
5.0V_LR
GND
3
1
2
3
4
2
4
WDO
RESET
WDI
PFO
8
7
6
5
5VL-RSTx
LVI-RSTx
4.65V Threshold LVI
IF PFI < 1.25V, PFO Goes LOW
MAX705CSA+
MR
VCC
GND
PFI
U11
LVI Circuit
J20
3
1
2
3
4
8
7
6
5
5
4
3
GND
5.0V_SR
U8C
9
GND
Serial Boot Mode
2
8
SN74LV125
2
1
2
5.0V_SR
VCC
3
GND
Page B-6
U8D
12
R16
10K
GND
UNUSED PARTS
BOOTCFG
5
1
11
U8B
SN74LV125
6
2
R13
10K
5.0V_SR
Reset-In
Disable
J17
SN74LV125
U8A
GND
SN74LV125
Boot Config
GND
6
Y ELLOW LED
MC74ACT08DG
U9B
J19
5.0V_SR
1
R18
DS1
USR RESET LED
560 OHM
5.0V_SR
5.0V_SR
Internal Flash
10K
RN6
MC74ACT08DG
8
GND
MC74ACT08DG
7
GND
U9C
JTAG-RSTx
TGT-RSTx
LVI-RSTx
5VL-RSTx
10
9
2
TGT-RSTx
(From Expansion Conn
/ User Connectors)
1
3
1
JTAG-RSTx
(From JTAG / NEXUS)
U9A
VCC
14
5.0V_SR
1
14
7
6 JTAG-RSTx
1
Tri-State Buffered RESET signal to MCU (Reset-IN)
13
MPC5516EVB User Manual Rev 1.0
10
4
R15
R14
PD3
PD2
Do Not Fit
0 OHM
2
(RevA+)
(Rev0)
11
LED RED
DS2
MC74ACT08DG
U9D
RST-OUTx
13
12
1
RST-OUTx
PD[0..15]
Buffered
RESET-OUT
Date:
Size
B
Title
6
3,8,9,11,12
6,7,11,12
3,6,11
Sheet
(MPC5510EVB)
Monday , September 10, 2007
Document Number
Drawing SCH-23130
5
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
BOOTCFG-R
PD[0..15]
RST-OUTx
MCU-RSTx
AC08 / AC125
Decoupling
Caps
BOOTCFG-R
(Allows Nexus to drive BOOTCFG at reset)
RSTCFG
R17
GND
C45
0.1 UF
MCU RESET LED
560 OHM
5.0V_SR
MCU-RSTx
C44
0.1 UF
5.0V_SR
Rev
E0
RESET CONTROL
Sept 2007
MPC5516EVBUM/D
BOOTCFG-R
JCOMP
TMS
2
J24
RST-OUTx
Allows Nexus tool to monitor MCU reset state
1
GND
47PF
Do Not Fit
C66
2
(Allows Nexus PROBE to drive BOOTCFG at reset)
Must be open-drain output with ability to
drive sufficient current to overcome 10K
pullup / pulldown)
BOOTCFG-R
5,7,11,12 RST-OUTx
5
11,14 JCOMP
11,14 TMS
J31
47PF
Do Not Fit
C61
Jumper allows JTAG RESET to be routed via
buffers or to be directly connected to the MCU
RESETx bi-directional pin (for debug hardware
that can monitor the state of the target reset).
MCU-RSTx
3
(Direct to MCU-Reset pin)
3,5,11 MCU-RSTx
5
JTAG-RSTx
1
(To RESET-IN Buffer)
TDI
TDO
TCLK
JTAG-RSTx
11,14 TDI
11,14 TDO
11,14 TCLK
Place CAPS as close to
connector pins as
possible but do NOT fit
caps at board assembly.
MPC5516EVB User Manual Rev 1.0
TPV23
TPV19
TPV21
TPV18
TPV16
TPV15
2
4
6
8
10
12
14
GND
(VSS)
(VSS)
(VSS)
(N/C)
TMS
(VSS)
JCOMP
GND
G1
G2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
G3
G4
G5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
41
42
43
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
GND
(CLKOUT)
(Vend IO-3)
(EVTI)
VREF
(RDY)
(MDO[7])
(MDO[6])
(MDO[5])
(MDO[4])
(MDO[3])
(MDO[2])
(MDO[1])
(MDO[0])
(EVTO)
(MCK0)
(MSEO[1])
(MSEO[0])
V-DBUG
Page B-7
G1..G5 = MICTOR
Centre Ground Pins
39
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
P14
NEXUS Connector
HDR 2X7
P13
P12V_R
1
3
5
7
9
11
13
(Vendor I/O 0)
VENDOR-IO-2
JTAG-JRSTx
TDO
(Vendor I/O 4)
TCLK
TMS
TDI
JCOMP (TRST)
(Vendor I/O 1)
RST-OUTx (TIO3)
(Tool I/O 2)
(Tool I/O 1)
UBATT
UBATT
(Tool I/O 0)
VALTREF
EVTI
(RDY)
TDI
TDO
TCLK
EVTI
JTAG-JRSTx
V-DBUG
ONCE Connector
NEXUS Conenctor (MICTOR)
PF2
PF11
PF10
PF9
PF8
PF7
PF6
PF5
PF4
PF1
PF3
PE6
3.3V_SR
0 OHM
0 OHM
R51
Do Not Fit
R50
TPV22
TPV20
TPV17
Date:
Size
B
Title
(EVTI / RW)
5.0V_SR
3
1
PF[0..15]
R49
10K
RW
PE[0..15]
PF[0..15]
(RW for RAM)
PE[0..15]
7,11,12,14
7
4,7,11,12
Monday , September 10, 2007
Sheet
(MPC5510EVB)
6
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
2
J31B
Document Number
Drawing SCH-23130
PF0
EVTI
R36
10K
V-DBUG
(PE6 CLKOUT)
RW
V-DBUG
Nexus target sense voltage select
5.0V_SR
Rev
E0
ONCE AND NEXUS CONNECTORS
Sept 2007
0
1
0
1
0
0
1
1
X
0
1
1
ALE
1
GND
1
2
3
4
2
4
6
8
10
10K
RN9
P12
4,6,11,12 PE[0..15]
5,6,11,12 RST-OUTx
1
1
1
1
CLKOUT
0
MPC5516EVBUM/D
11,12,14 PH[0..15]
6 RW
6,11,12,14 PF[0..15]
TA
X
TS
X
Latch address when TS is low (and
CLKOUT rising edge)
De-Latch address when TA is low
(and CLKOUT rising edge)
(Address Latches when ALE is LOW)
11,12 PG[0..15]
1000PF
C65
PF[0..15]
PH[0..15]
RW
1
3
5
7
9
8
7
6
5
470PF
C6
1
8
15
22
2
3
4
5
6
7
9
10
11
12
13
16
GAL-TCK
GAL-TMS
GAL-TDI
GAL-TDO
GAL-TCK
GAL-TMS
GAL-TDI
GAL-TDO
PE6
31
32
1
2
3
6
7
8
9
10
14
TCK
TMS
TDI
TDO
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
U16
29
4
13
21
PE6 (CLKOUT) 30
RST-OUTx
PF15 (WE1)
PF14 (WE0)
PF13 (OE)
RW
PF11 (CS0)
PF10 (CS1)
PF8 (AD14)
PF9 (AD15)
PF1 (TA)
PF12 (TS)
GND
GND
GAL-VCC
RST-OUTx
PF15
PF14
PF13
RW
PF11
PF10
PF8
PF9
PF1
PF12
*
*
*
*
*
*
(AD24)
(AD25)
(AD26)
(AD27)
(AD28)
(AD29)
(AD30)
(AD31)
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
GAL-ALE
(AD16)
(AD17)
(AD18)
(AD19)
(AD20)
(AD21)
(AD22)
(AD23)
J22
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
1
5.0V_SR
GND
0.1 UF
0.1 UF
C7
C62
GAL
Power
Control
PE[0..15]
(PE6 CLKOUT)
GAL-VCC
J32
PG[0..15]
3.3V_SR
1
2
Compatible Buffers:
TI CY74FCT16373 / CY74FCT162373T
IDT IDT74FCT162373AT
MPC5516EVB User Manual Rev 1.0
45
39
34
28
13
14
16
17
19
20
22
23
2
3
5
6
8
9
11
12
31
42
GNDO
GNDO
GND
TAB
IOQ1
IOQ2
IOQ3
IOQ4
IOQ5
IOQ6
IOQ7
IOQ8
IOQ9
IOQ10
VCC
VCCO
VCCO
GND
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
VCC
14
GAL-ST
GAL-LT
TP-I/O7
TP-I/O6
TP-I/O5
ALE-SET
ALE-CLR
ADDR15
ADDR14
GAL-ALE
17
18
19
20
21
23
24
25
26
27
GND
(Alternative
Footprint)
GAL-VCC
28
ispGAL22V10AV-23LNN
TCK
TMS
TDI
TDO
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
GND
GND
GND
GND
2O1
2O2
2O3
2O4
2O5
2O6
2O7
2O8
1O1
1O2
1O3
1O4
1O5
1O6
1O7
1O8
VCC
VCC
SRAM-5V
74FCT162373ATPACT
GND
GND
GND
GND
1LE
2LE
1OE
2OE
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
VCC
VCC
U10
U15
4
10
15
21
48
25
1
24
36
35
33
32
30
29
27
26
47
46
44
43
41
40
38
37
7
18
2
20
12
11
33
26
25
24
23
22
19
18
17
16
15
28
27
5
GND
470PF
1000PF
C49
C48
SRAM-5V
10K
R33 10K
R32
CS-32
CS-16
(BE1)
(BE0)
(OE)
2
6
1
5
PH15 (BE3)
PH14 (BE2)
PF11 (CS0)
(CS1)
(CS0)
(CS1)
PF10
PF15
PF14
PF13
J35
3
4
CS-32
CS-16
Pullups on SRAM CS lines. Ensures
that when SRAM is disabled, and CS
jumpers removed from selet jumper,
no pullup signal on PF10 / 11
GND
GND
1
DS9
DS8
1
ADDR[14..30]
(GAL Latch and Status LED's)
TPV10
TPV11
TPV12
TPV13
TPV14
TPV9
2
R31 270 OHM
GAL-ST
2
R30 270 OHM
GAL-ALE
ADDR14
ADDR15
ALE-CLR
ALE-SET
TP-I/O5
TP-I/O6
TP-I/O7
GAL-LT
ADDR24
ADDR25
ADDR26
ADDR27
ADDR28
ADDR29
ADDR30
ADDR31
GND
0.1 UF
C46
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
0.1 UF
C47
Page B-8
(Alternative
Footprint)
GND
6
17
41
40
39
CS-32
RW
PF13 (OE)
PF14 (BE0)
PF15 (BE1)
12
34
44
43
42
27
26
25
24
21
20
19
18
5
4
3
2
1
12
34
6
17
41
40
39
44
43
42
27
26
25
24
21
20
19
18
5
4
3
2
1
12
34
6
17
41
40
39
44
43
42
27
26
25
24
21
20
19
18
5
4
3
2
1
ADDR29
ADDR28
ADDR27
ADDR26
ADDR25
ADDR24
ADDR23
ADDR22
ADDR21
ADDR20
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
GND
CS-32
RW
PF13 (OE)
PH14 (BE2)
PH15 (BE3)
ADDR29
ADDR28
ADDR27
ADDR26
ADDR25
ADDR24
ADDR23
ADDR22
ADDR21
ADDR20
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
GND
CS-16
RW
PF13 (OE)
PF14 (BE0)
PF15 (BE1)
ADDR30
ADDR29
ADDR28
ADDR27
ADDR26
ADDR25
ADDR24
ADDR23
ADDR22
ADDR21
ADDR20
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
NC_22
NC_23
NC_28
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VDD_11
VDD_33
NC_22
NC_23
NC_28
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VDD_11
VDD_33
NC_22
NC_23
NC_28
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VDD_11
VDD_33
IS61C6416AL-12TLI
GND_12
GND_34
CE
WE
OE
UB
LB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
U17
IS61C6416AL-12TLI
GND_12
GND_34
CE
WE
OE
UB
LB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
U14
IS61C6416AL-12TLI
GND_12
GND_34
CE
WE
OE
UB
LB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
U12
22
23
28
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
11
33
22
23
28
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
11
33
22
23
28
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
11
33
(D31)
(D30)
(D29)
(D28)
(D27)
(D26)
(D25)
(D24)
(D23)
(D22)
(D21)
(D20)
(D19)
(D18)
(D17)
(D16)
(D31)
(D30)
(D29)
(D28)
(D27)
(D26)
(D25)
(D24)
(D23)
(D22)
(D21)
(D20)
(D19)
(D18)
(D17)
(D16)
SRAM-5V
(D15)
(D14)
(D13)
(D12)
(D11)
(D10)
(D9)
(D8)
(D7)
(D6)
(D5)
(D4)
(D3)
(D2)
(D1)
(D0)
SRAM-5V
MSB
PF9
PF8
PF7
PF6
PF5
PF4
PF3
PF2
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PG15
PG14
PG13
PG12
PG11
PG10
PG9
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
LSB
MSB
PG15
PG14
PG13
PG12
PG11
PG10
PG9
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
LSB
Date:
Size
B
Title
470PF
1000PF
C50
C51
C64
C63
C60
C59
GND
1000PF
470PF
0.1 UF
0.1 UF
C70
C69
C67
C68
16-BIT Memory System:
WE/BE 32-BIT PORT WE/BE 16-BIT PORT
BE[0]
BE[0]
BE[1]
BE[1]
BE[2]
BE[0]
BE[3]
BE[1]
PJ[0..15]
11,12
Connected to bus
entry at left hand
side of sheet)
Sheet
(MPC5510EVB)
Monday , September 10, 2007
Document Number
Drawing SCH-23130
7
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
PJ[0..15]
PF[0..15]
PG[0..15]
Note the exception for 16-bit port using DATA[16..31]
Data Access
D[0..7]
D[8..15]
D[16..23]
D[24..31]
32-BIT Memory System (2*16-bit)
In 16-bit Data bus mode (DBM set to 1 in MCR), the
EIM can be configured to use DATA[0..15] or
DATA[16..31] by writing to D16_31 bit in MCR. The
EVB is configured for Data[16..31]
GND
1000PF
470PF
0.1 UF
0.1 UF
Local Decoupling for all 3 SRAM parts
GND
0.1 UF
0.1 UF
C55
C56
Rev
E0
EXTERNAL SRAM
Sept 2007
PD[0..15]
MPC5516EVBUM/D
Note - CANB Rx on initial MPC5516
Si is shared with BootCFG so it was
decided not to use this as one of
the default CAN modules
3,5,9,11,12 PD[0..15]
MPC5516EVB User Manual Rev 1.0
PD4
PD5
CANC
PD0
PD1
CANA
(CNC-TX)
(CNC-RX)
(CNA-TX)
(CNA-RX)
1
3
1
3
1
GND
R6
2
4
0 OHM
R5
0 OHM
2
4
J7
2
GND
4
5
CANC-RX
2
1
8
CANC-TX
CANC-RS
GND
4
5
CANA-RX
2
1
8
CANA-TX
CANA-RS
CAN-5V
C36
1000PF
7
6
3
CANH
CANL
VCC
7
6
3
GND
CANH
CANL
PCA82C250TD
GND
RXD
VREF
TXD
RS
U2
C35
0.1 UF
C28
1000PF
GND
VCC
PCA82C250TD
GND
RXD
VREF
TXD
RS
U1
C27
0.1 UF
CANC-CANH
CANC-CANL
Page B-9
GND
GND
CANA-CANH
CANA-CANL
Rs = 0 Ohms for High Speed Operation. Replace
with non zero resistor to enable slope
control.
GND
HDR 2X2
J4
J3
5.0V_SR
1
2
3
1
2
3
P4
P3
Date:
Size
B
Title
Sheet
(MPC5510EVB)
Monday , September 10, 2007
Document Number
Drawing SCH-23130
8
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
Rev
E0
CAN PHYSICAL INTERFACE
Sept 2007
PD[0..15]
MPC5516EVBUM/D
3,5,8,11,12 PD[0..15]
(RXD-A)
(TXD-B)
(RXD-B)
PD7
PD8
PD9
3
4
3
4
J11
2
6
1
5
2
6
1
5
SCIB-TX
LINB-TX
SCIB-RX
LINB-RX
SCIA-TX
LINA-TX
SCIA-RX
LINA-RX
Note - The SBC provides another 2 LIN
Physical interfaces which can be connected
by user to user connectors with jumper
wires
(TXD-A)
PD6
J10
1
5.0V_SR
1
5.0V_SR
GND
J5
2
R10
R9
C5
1000PF
GND
J6
C41
1.0UF
C42
1.0UF
5.0V_SR
J9
1
10K
2
10K
2
GND
LINB-TX
LINB-RX
MCZ33399
RXD
EN
WAKE
TXD
U3
MCZ33399
RXD
EN
WAKE
TXD
U4
R1OUT
R2OUT
T1IN
T2IN
C2+
C2-
C1+
C1-
U7
Page B-10
1
2
3
4
Enabled as long
as EN > 3.5V
GND
LINA-TX
LINA-RX
1
2
3
4
12
9
Enabled as long
as EN > 3.5V
SCIB-RX
SCIB-TX
SCIA-RX
SCIA-TX
4
5
RS232-4
RS232-5
11
10
1
3
RS232-1
RS232-3
GND
C37
1.0UF
RS232-VCC
16
VCC
MPC5516EVB User Manual Rev 1.0
GND
INH
VSUP
LIN
GND
8
7
6
5
8
7
6
5
GND
GND
R1IN
R2IN
T1OUT
T2OUT
V-
V+
MAX232ACSE+
INH
VSUP
LIN
GND
15
J2
C30
1000PF
1
J1
C29
1000PF
1
GND
C40
1.0UF
13
8
14
7
6
2
C43
1.0UF
D2
GND
D1
GF1A
1
R7 1.0K
2 2
GF1A
1
R8 1.0K
P12V
Date:
Size
B
Title
DB9
P6
DB9
P8
1
2
3
4
P7
LINB
1
2
3
4
LINA
Sheet
(MPC5510EVB)
Tuesday , September 11, 2007
Document Number
Drawing SCH-23130
9
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
GND
LINB-VSUP
LINB-LIN
P12V
GND
LINA-VSUP
LINA-LIN
Master Mode Pullup Enable
C32
0.1 UF
GND
C31
0.1 UF
2 2
M2
1
6
2
7
3
8
4
9
5
M1
M2
1
6
2
7
3
8
4
9
5
RS232 TERMINAL PORT
9-WAY D-TY PE (Female)
GND
GND
Master Mode Pullup Enable
RS232B-RX
RS232B-TX
RS232A-RX
RS232A-TX
Note - If a MAX232A device is
used, the 5 polorised 1uF caps
can be reduced to 0.1uF M1
P5
SCI / RS232
Rev
E0
SCI and LIN PHYSICAL INTERFACES
Sept 2007
PC[0..15]
1
2
3
4
GND
10K
RN4
PC8
PC9
PC7
R11
47K
8
7
6
5
R12 47K
8
7
6
5
1
3
5
7
1
3
5
7
J12
J18
2
2
4
6
2
4
6
8
2
4
6
8
FRB-JTXD
FRB-JTXEN
FRA-JTXD
FRA-JTXEN
FRB-JRXD
WAKE
TXD
TXEN
BGE
STBN
EN
TRXD0
TRXD1
U6
MODE
Normal
Rec Only
Go to Sleep
Sleep
TJA1080TS/N
FRB-WAKE 15
FRB-BGE
FRB-STBN
FRB-EN
5
6
8
9
3
GND
11
10
FRA-JRXD
WAKE
TXD
TXEN
BGE
STBN
EN
2
4
6
HDR 2X3
J16
TRXD0
TRXD1
U5
1
3
5
TJA1080TS/N
FRA-WAKE 15
5
6
8
9
3
GND
11
10
FRA-BGE
FRA-STBN
FRA-EN
VIO Selection Jumper
2
4
6
HDR 2X3
J14
J15
1
3
5
J13
1
3
5
3
1
P12V
GND
EN
1
0
1
0
GND
STBN
1
1
0
0
RXD
ERRN
RXEN
BP
BM
INH2
INH1
FR-VIO
FR-5V
FR-12V
RXD
ERRN
RXEN
BP
BM
INH2
INH1
4
Page B-11
TPV7
TPV8
FRB-BM
FRB-ERRN
FRB-RXEN
FRB-BP
18
17
7
13
12
1
FRB-INH2
FRB-INH1
TPV5
TPV6
DLW43SH
L2
C33
3
2
FRB-DATA-B
FRB-DATA-A
GND
C4
+
3
2
C2
+
DLW43SH
TPV3
TPV4
C38
FRA-ERRN
FRA-RXEN
FRA-BM 4
GND
C3
+
C1
+
L1
TPV1
TPV2
FRA-BP 1
FRA-INH2
FRA-INH1
C34
C39
1
2
7
13
12
18
17
1
2
FR-VIO
FR-5V
FR-12V
FR-12V
FR-5V
FR-VIO
0.1 UF
FR-VIO
10K
RN5
GND
1
2
3
4
FR-VIO
PC1
PC0
PC2
3.3V_SR
5.0V_SR
0.1 UF
MPC5516EVBUM/D
Note - Flexray is 2nd
Alternate function of
PortC Pins
11,12,13 PC[0..15]
PortC[0..15] is in the VDDE1 power domain which can
be selected between 3.3v and 5V. The power control
jumper allows selection of the appropriate I/O
voltage to use on the Flexray PHI
MPC5516EVB User Manual Rev 1.0
4
19
20
14
VIO
VCC
VBUF
VBAT
GND
16
4
19
20
14
0.1 UF
10UF
VIO
VCC
VBUF
VBAT
0.1 UF
10UF
GND
10UF
16
10UF
R1
47 OHM
4700PF
C22
R2
47 OHM
FRA-DATA-B
R3
47 OHM
4700PF
C25
R4
47 OHM
FRA-DATA-A
Date:
Size
B
Title
C21
10 PF
P1
P2
Monday , September 10, 2007
Sheet
(MPC5510EVB)
10
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
Crimped lead - 279-9522
Receptacle housing - 279-9156
1
2
Flexray B
Flexray A
Crimped lead - 279-9522
Receptacle housing - 279-9156
1
2
Document Number
Drawing SCH-23130
GND
C23
10 PF
C24 GND
10 PF
C26
10 PF
Rev
E0
FLEXRAY PHYSICAL INTERFACE
Sept 2007
MCU-RSTx
PB[0..15]
VDDA
VDD15
VDDE2
VDDR
TGT-RSTx
12
3
3
3
3
5,12
PG[0..15]
7,12
B
MPC5516EVBUM/D
PB2
PK0
PA8
VDDA
VDD15
3.3V_SR
PB13
VDD15
PA12
PB4
1
3
5
7
9
11
13
15
17
19
21
GND 23
25
27
29
31
33
GND 35
(NC) 37
39
41
43
45
GND 47
49
51
53
55
57
GND 59
61
63
65
67
69
GND 71
73
75
77
79
81
GND 83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
P9
PJ[0..15]
J
GND
G
F
B
K
PB12
2
PA13
4
3.3V_SR
6
VDDA
8
VDD15
10
PB3
12
PK1
14
VDD15
16
18 GND
PB0
20
PA11
22
PA9
24
PA7
26
PB1
28
30 GND
PA3
32
PA5
34
MCU-RSTx
36
PA0
38
PA2
40
42 GND
PH12
44
PJ13
46
PJ14
48
PJ15
50
VDDE2
52
54 GND
PH8
56
PH5
58
PH6
60
PH3
62
PJ8
64
66 GND
VDDE2
68
PH1
70
PH2
72
PG13
74
PG15
76
78 GND
PF15
80
VDDE2
82
PG9
84
PG11
86
PF11
88
90 GND
PG3
92
VDDE2
94
PG8
96
PF10
98
PH15
100
5.0V_SR
102
PG7
104
106 VDD15
PF6
108
PH14
110
VDDR
112
P12V
114
PG6
116
118 VDD15
RST-OUTx
120
MCU-RSTx
A
H
P12V
5.0V_SR
VDD15
3.3V_SR
PB[0..15]
1.5V_SR
F
D
J
C
E
B
GND
1
3
5
VDDE1 7
VDD15
9
GND 11
PB7
13
PC0
15
PC8
17
VDD15
19
PC11
21
GND 23
PB14
25
PC5
27
PC13
29
PC14
31
VDDE1
33
GND 35
PC6
37
PD0
39
PD2
41
VDDE1
43
PD3
45
GND 47
PD6
49
PD9
51
PD10
53
VDDE1
55
PD11
57
PE7
59
PE8
61
PD14
63
PE10
65
PE12
67
VDDE1
69
GND 71
PE13
73
PE2
75
PE3
77
PE15
79
VDDE3
81
GND 83
PJ0
85
VDD33
87
PE4
89
EVB-EXTAL
91
PJ4
93
GND 95
VPP
97
PE6
99
PJ3
101
PF2
103
VDD15
105
1.5V_SR
107
VDDSY N
109
PJ5
111
VDDE3
113
VDDE3
115
JCOMP
117
TMS
119
PB6
PB15
PC7
Page B-12
AMP Connector Part number 179031-5 (8mm high, 0.8mm pitch 120way)
Suitable Mating connector - AMP 5-179009-5 (9mm high) or 5-179010-5 (13mm high)
PF[0..15]
J
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
Conenctor 1
PF[0..15]
G
GND
PG[0..15]
F
PG1
PG4
VDD15
PG10
PF7
PF14
PG0
VDDE2
5.0V_SR
PJ7
PF13
PG2
PG5
VDD15
P12V
PF9
PG12
PG14
PF8
PF12
VDDE2
PH7
PH4
PJ9
VDDE2
PH0
PH9
VDDE2
PJ11
PJ12
PJ10
PA1
PH10
PH11
PH13
PA15
PA6
PB5
PA14
PA10
PA4
PG[0..15]
PJ[0..15]
RST-OUTx
TGT-RSTx
VDDR
(Jumpered)
VDDE2
(Jumpered)
VDD15
(Jumpered)
VDDA
(Jumpered)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
PB[0..15]
PB[0..15]
K
PK[0..1]
PK[0..1]
A
PA[0..15]
PA[0..15]
H
PH[0..15]
PH[0..15]
MCU-RSTx
CONNECTORS MUST BE PLACED IN
ACCORDANCE WITH PCB SPECIFICATION
6,7,12,14 PF[0..15]
PJ[0..15]
7,12
5,6,7,12 RST-OUTx
PK[0..1]
12
3,12,13 PA[0..15]
7,12,14 PH[0..15]
3,5,6
MPC5516EVB User Manual Rev 1.0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
PJ[0..15]
PF[0..15]
PE[0..15]
Date:
Size
B
Title
GND
2
4
6 GND
8
10
12
14
16
18 GND
20
22
24
26
28
30 GND
32
34
36
38
40
42 GND
44
46
48
50
52
54 GND
56
58
60
62
64
66 GND
68
70
72
74
76
78 GND
80
82 VDDE3
84
86
88
90 GND
92
94
96
98
100
102 GND
104
106
108
110
112
114
116
118
120
Conenctor 2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
P22
PB[0..15]
PC[0..15]
PD[0..15]
F
D
PE[0..15]
VDDE3
(Jumpered)
TMS
JCOMP
EVB-EXTAL
TDO
TCLK
VDDSY N
(Jumpered)
TDI
VPP
(Jumpered)
VDD33
(Jumpered)
VDDE1
(Jumpered)
PE[0..15]
TMS
JCOMP
EVB-EXTAL
VDDE3
TDO
TCLK
VDDSY N
TDI
VPP
VDD33
VDDE1
PC[0..15]
PD[0..15]
4,6,7,12
6,14
6,14
4
3
6,14
6,14
3
6,14
3
3
3
10,12,13
3,5,8,9,12
Monday , September 10, 2007
Sheet
(MPC5510EVB)
11
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
J
C
Document Number
Drawing SCH-23130
E
PF4
1.5V_SR
PF3
TDO
VDD15
TDI
VDD15
TCLK
PF5
PJ6
PJ1
PF1
PJ2
PF0
PE5
PD15
VDDE1
PE0
PE1
PE14
VDDE1
PD12
PD13
PE9
PE11
VDDE1
PD4
PD5
PD7
PD8
PB9
VDDE1
PC2
PC15
PD1
VDD15
PC12
PB8
PC1
PC9
VDD15
PC10
PB11
PC4
B
PB10
PC3
PC[0..15]
Rev
E0
DAUGHTERCARD CONNECTORS
Sept 2007
PortA / ADC
MPC5516EVBUM/D
PortE / SPI /
eMIOS / EIM
4,6,7,11 PE[0..15]
PortD / CAN /
SPI / SCI
3,5,8,9,11 PD[0..15]
Note - The LED Matrix is also
connected to PC[0..11]
PortC / eMIOS
10,11,13 PC[0..15]
PortB / ADC / SPI
11 PB[0..15]
3,11,13 PA[0..15]
MPC5516EVB User Manual Rev 1.0
PE0
PE2
PE4
PE6
PE8
PE10
PE12
PE14
GND
1
3
5
7
9
11
13
15
17
GND
(PCS-a2)
1
(PCS-A0)
3
(SOUT-A)
5
(CLKOUT)
7
(eMIOS24) 9
(eMIOS26) 11
(eMIOS28) 13
(eMIOS30) 15
17
GND
(CNTX-A)
(CNRX-B)
(CNTX-C)
(TXD-A)
(TXD-B)
(PCS_B2)
(PCS_B0)
(SOUT-B)
PE[0..15]
PD0
PD2
PD4
PD6
PD8
PD10
PD12
PD14
GND
(eMIOS0)
1
(eMIOS2)
3
(eMIOS4)
5
(eMIOS6)
7
(eMIOS8)
9
(eMIOS10) 11
(eMIOS12) 13
(eMIOS14) 15
17
PD[0..15]
PC0
PC2
PC4
PC6
PC8
PC10
PC12
PC14
1
3
5
7
9
11
13
15
17
(AN28)
1
(AN30)
3
(AN32)
5
(AN34)
7
(AN36)
9
(AN38) 11
(TXD_G) 13
(TXD_H) 15
17
PC[0..15]
PB0
PB2
PB4
PB6
PB8
PB10
PB12
PB14
GND
(AN00)
(AN02)
(AN04)
(AN06)
(AN08)
(AN10)
(AN12)
(AN14)
PB[0..15]
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PA[0..15]
P31
P15
P24
P30
P16
GND
(PCS-A1)
(SCK-A)
(SIN-A)
(---)
(eMIOS25)
(eMIOS27)
(eMIOS29)
(eMIOS31)
GND
(CNRX-A)
(CNTX-B)
(CNRX-C)
(RXD-A)
(RXD-B)
(PCS_B1)
(SCK-B)
(SIN-B)
GND
(eMIOS1)
(eMIOS3)
(eMIOS5)
(eMIOS7)
(eMIOS9)
(eMIOS11)
(eMIOS13)
(eMIOS15)
GND
(AN29)
(AN31)
(AN33)
(AN35)
(AN37)
(AN39)
(RXD_G)
(RXD_H)
GND
(AN01)
(AN03)
(AN05)
(AN07)
(AN09)
(AN11)
(AN13)
(AN15)
PE1
PE3
PE5
PE7
PE9
PE11
PE13
PE15
PD1
PD3
PD5
PD7
PD9
PD11
PD13
PD15
PC1
PC3
PC5
PC7
PC9
PC11
PC13
PC15
PB1
PB3
PB5
PB7
PB9
PB11
PB13
PB15
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
GND
(AD0)
(AD2)
(AD4)
(AD6)
(PCS-D4)
(PCD-D2)
(PCS-D0)
(SOUT-D)
GND
(AN27)
(AN25)
(AN23)
(AN21)
(AN19)
(AN17)
(PCS-D5)
(WE2)
GND
(AD16)
(AD18)
(AD20)
(AD22)
(AD24)
(AD26)
(AD28)
(AD30)
GND
(R/W)
(AD8)
(AD10)
(AD12)
(AD14)
(CS1)
(TS)
(WE0)
1
3
5
7
9
11
13
15
17
1
3
5
7
9
11
13
15
17
1
3
5
7
9
11
13
15
17
1
3
5
7
9
11
13
15
17
GND
(EXTAL32) 1
PK0
RST-OUTx
3
5
PJ0
PJ2
PJ4
PJ6
PJ8
PJ10
PJ12
PJ14
PH0
PH2
PH4
PH6
PH8
PH10
PH12
PH14
PG0
PG2
PG4
PG6
PG8
PG10
PG12
PG14
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
P33
P23
P29
P25
Page B-13
NOTE: All Connectors are 0.1" through-hole headers
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
P17
2
4
6
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
PH1
PH3
PH5
PH7
PH9
PH11
PH13
PH15
PG1
PG3
PG5
PG7
PG9
PG11
PG13
PG15
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
GND
Date:
Size
B
Title
(XTAL32) PK1
TGT-RSTx
GND
(AD1)
PJ1
(AD3)
PJ3
(AD5)
PJ5
(AD7)
PJ7
(PCS-D3) PJ9
(PCS-D1) PJ11
(SCK-D) PJ13
(SIN-D) PJ15
GND
(AN26)
(AN24)
(AN22)
(AN20)
(AN18)
(AN16)
(---)
(WE3)
GND
(AD17)
(AD19)
(AD21)
(AD23)
(AD25)
(AD27)
(AD29)
(AD31)
GND
(TA)
(AD9)
(AD11)
(AD13)
(AD15)
(CS0)
(OE)
(WE1)
PF[0..15]
PG[0..15]
PF[0..15]
PJ[0..15]
PH[0..15]
RST-OUTx
TGT-RSTx
PK[0..1]
5,6,7,11
5,11
11
7,11
7,11,14
7,11
6,7,11,14
Sheet
(MPC5510EVB)
Monday , September 10, 2007
Document Number
Drawing SCH-23130
12
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
(FROM MCU)
(TO MCU)
PortK / Reset
PK[0..1]
PortJ / EIM / SPI
PJ[0..15]
PortH / ADC /
SPI / EIM
PH[0..15]
PortG / EIM (AD)
PG[0..15]
PortF / EIM
Rev
E0
USER CONNECTORS
Sept 2007
MPC5516EVBUM/D
3,11,12 PA[0..15]
10,11,12 PC[0..15]
PA[0..15]
PC[0..15]
1
2
3
4
GND
1
3
J23
2
4
2
2
2
2
(AN0)
R21
10K
2
3.3V_SR
J8
3
1
5.0V_LR
R19
10K
(eMIOS3)
(eMIOS2)
(eMIOS1)
(eMIOS0)
PC5
PC3
PC2
PC1
PC0
RV1
2K 1
LED-OE-HIGH
LED-OE-LOW
GND
GND
(eMIOS5)
(UNUSED)
(UNUSED)
(eMIOS4)
PC9
PC8
PC7
PC6
PC4
(eMIOS9)
(eMIOS8)
(eMIOS7)
(eMIOS6)
PC11
PC10
470OHM
RN8
(UNUSED)
(UNUSED)
(eMIOS11)
(eMIOS10)
1
2
3
4
4
10
15
21
1
48
25
24
30
29
27
26
36
35
33
32
41
40
38
37
47
46
44
43
GND
GND
GND
GND
4Y 1
4Y 2
4Y 3
4Y 4
3Y 1
3Y 2
3Y 3
3Y 4
2Y 1
2Y 2
2Y 3
2Y 4
1Y 1
1Y 2
1Y 3
1Y 4
VCC
VCC
VCC
VCC
5.0V_SR
45
39
34
28
19
20
22
23
13
14
16
17
8
9
11
12
2
3
5
6
7
18
31
42
2
2
SW3
1
2
2
SW5
1
SW4
1
SW2
1
R1
R2
R3
R4
R5
R6
R7
LED-C5
Page B-14
2.2v forward voltage so R=180 Ohms
Buffers can sink / source approx max 50mA
so run led's at approx 6mA (30mA sink on
Columns)
LED-C4
R28 180 OHM
LED-RC5
LED-C3
LED-C2
LED-C1
12
11
2
9
4
5
6
R29 180 OHM
R24 180 OHM
R25 180 OHM
R20 180 OHM
GND
LED-RC4
LED-RC3
LED-RC2
LED-RC1
LED-R1
LED-R2
LED-R3
LED-R4
LED-R5
LED-R6
LED-R7
Local Decoupling
1000PF 470PF
0.1 UF
0.1 UF
C57
C54
C53
C58
DS3
1
2
3
4
LED 5x7
User Switches
USR-SW1
USR-SW2
USR-SW3
USR-SW4
OMRON B3WN-6002 Pushbutton Switch
5.0V_SR
GND
3.3V_SR
SN74LVC16244ADGGR
GND
GND
GND
GND
1OE
2OE
3OE
4OE
4A1
4A2
4A3
4A4
3A1
3A2
3A3
3A4
2A1
2A2
2A3
2A4
1A1
1A2
1A3
1A4
U13
8
7
6
5
(Note - This is run from linear 5.0v regulator to provide a stable input voltage)
PA0
DS7
DS6
DS5
DS4
LED's are SMD (1206) Yellow
1
1
1
1
LED Dot Matrix Display
P10
User LED's
AN0 Potentiometer
MPC5516EVB User Manual Rev 1.0
2
C1
C2
C3
C4
C5
1
3
10
7
8
10K
RN7
1
2
3
4
P11
8
7
6
5
GND
Date:
Size
B
Title
Sheet
(MPC5510EVB)
Tuesday , September 11, 2007
Document Number
Drawing SCH-23130
13
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
Rev
E0
User Peripherals Inc Prototyping
Sept 2007
TDI
TMS
TDO
TCLK
MPC5516EVBUM/D
6,11 JCOMP
6,11
6,11
6,11
6,11
7,11,12 PH[0..15]
6,7,11,12 PF[0..15]
(JCOMP / TRST)
PH[0..15]
PF[0..15]
MPC5516EVB User Manual Rev 1.0
1
2
3
4
1
2
3
4
10K
1
2
3
4
RN2
10K
RN1
10K
RN3
R27
10K
8
7
6
5
8
7
6
5
GND
8
7
6
5
2
V-DBUG
J26
J28
GND
3
1
SRAM runs from 5V
so EIM pullups are
5V rather than
level of VDDE
Page B-15
All RESET Pullup Resistors are shown on Reset Circuitry page
JCOMP
TDI
TMS
TDO
TCLK
(BWE0)
(BWE1)
(BWE2)
(BWE3)
PF14
PF15
PH14
PH15
JTAG PORT
(TA)
(TS)
(OE)
PF1
PF12
PF13
For Single Chip mode
operation, need to isolate
pullup resistors from pins
that are mux'd with single
chip functions
5.0V_SR
1
2
FM2
FID-040
100 Mil Mask
FM4
FID-040
100 Mil Mask
Date:
Size
B
Title
FM1
FID-040
100 Mil Mask
FM3
FID-040
100 Mil Mask
FM6
FID-040
100 Mil Mask
FM7
FID-040
100 Mil Mask
(MPC5510EVB)
Wednesday , September 12, 2007 Sheet
Document Number
Drawing SCH-23130
14
MPC5510 Evaluation Board
of
14
Freescale MCD Applications - East Kilbride
FM5
FID-040
100 Mil Mask
FM8
FID-040
100 Mil Mask
Rev
E0
TERMINATION RESISTORS
Sept 2007
Refdes
C1,C2,C3,C4
C5,C28,C29,C30,C36,C48,C51,C54,C64,C65,C70,C
84
C6,C49,C50,C57,C63,C69
C7,C27,C31,C32,C33,C34,C35,C38,C39,C44,C45,C
46,C47,C52,C53,C55,C56,C58,C59,C60,C62,C67,C6
8,C72,C73,C74,C75,C76,C77,C78,C79,C80,C81,C82
,C83
C8,C19
C9,C10,C11
C12
C13,C14,C15,C20
C16
C17,C18
C21,C23,C24,C26
C22,C25
C37,C40,C41,C42,C43
C61,C66
C71
DS1,DS4,DS5,DS6,DS7,DS8,DS9
DS2
DS3
DS10,DS11,DS12,DS13
D1,D2,D4
D3,D6,D7,D8
FB1,FB2,FB3
FM1,FM2,FM3,FM4,FM5,FM6,FM7,FM8
F1
MPC5516EVBUM/D
2
3
1
4
1
2
4
2
5
2
1
7
1
1
4
3
4
3
8
1
6
35
Qty
4
12
Appendix B - EVB Bill Of Materials
MPC5516EVB User Manual Rev 1.0
4.7uF
10UF
68UF
100uF
1000UF
3.3UF
10 PF
4700PF
1.0UF
47PF
2200PF
YELLOW LED
LED RED
LED 5x7
LED GREEN
GF1A
B130LB-13
BLM31AJ601SN1L
FID-040
Fuse Holder
470PF
0.1 UF
Value
10UF
1000PF
Page B-16
MURATA
VISHAY INTERTECHNOLOGY
AVX
PANASONIC
NICHICON
MURATA
KEMET
MURATA
TAIYO YUDEN
VENKEL COMPANY
SMEC
KINGBRIGHT
KINGBRIGHT
KINGBRIGHT
KINGBRIGHT
VISHAY INTERTECHNOLOGY
DIODES INC
MURATA
GENERIC
BUSSMANN
KEMET
KEMET
Manufacturer
PANASONIC
VENKEL COMPANY
GRM32ER71H475K
293D106X9010A2TE3
TPSE686K025R0125
EEEFC1V101AP
UVZ1H102MHD
GRM32DR71H335KA88L
C0805C100J5GAC
GRM2165C1H472JA01D
TMK316BJ105ML
C0805C0G500470JNE
MCCE222J2NOTF
APT3216SYC
APT3216SURCK
TA07-11GWA
K/APT-3216SGD
GF1A-E3
B130LB-13
BLM31AJ601SN1L
FID-040
MCHTC-15M
C0805C471J5GAC
C0805C104K5RAC
Part Number
EEE1CS100SR
C0805COG500-102JNE
Sept 2007
MPC5516EVBUM/D
2
2
2
5
2
1
1
1
9
1
2
1
1
1
2
1
8
PT1,PT2,PT3,PT4,PT5,PT6,PT7,PT8,PT9,PT10,PT1
1,PT12,PT13,PT14,PT15,PT16,PT17,PT18,PT19,PT
20
P1,P2
P3,P4
P5,P6
P7,P8,P10,P11,P26
P9,P22
P12
P13
P14
P15,P16,P17,P23,P24,P25,P29,P30,P31
P18
P21,P27
P28
P32
P33
Q1,Q2
Q3
RN1,RN2,RN3,RN4,RN5,RN6,RN7,RN9
L5
1
20
L4
J1,J2,J5,J6,J7,J8,J9,J17,J21,J22,J24,J25,J26,J27,J3
2,J39,J41,J42,J44,J45,J46
J3,J4,J20,J23
J10,J11,J12,J14,J16,J35
J13,J15
J18,P19,J19,J28,J29,J30,J31B,J31,J33,J34,J36,J37,
J38,J40
J43
L1,L2
L3,L6
1
1
2
2
4
6
2
14
21
MPC5516EVB User Manual Rev 1.0
HDR 1X2
HDR_1X3
DB9
1X4HDR
CON2X60
HDR_2X5
HDR 2X7
HDR_2X19_F
HDR 2X9
HDR_1X5_M
1053378-1
POWER_JACK
TB2
HDR_2X3
BCP52-16
BSH103
10K
HDR_1X1
100UH
68UH
HDR2X6
DLW43SH
47UF
HDR 2X2
HDR 2X3
HDR_2X4
HDR 3X1
HDR 1X2
Page B-17
MOLEX
SAMTEC
TYCO ELECTRONICS
SAMTEC
TYCO ELECTRONICS
SAMTEC
3M
TYCO ELECTRONICS
SAMTEC
TYCO ELECTRONICS
TYCO ELECTRONICS
SWITCHCRAFT
TYCO ELECTRONICS
SAMTEC
PHILIPS SEMICONDUCTOR
PHILIPS SEMICONDUCTOR
BOURNS
SAMTEC
MURATA
COOPER ELECTRONICS
TECHNOLOGIES
COOPER ELECTRONICS
TECHNOLOGIES
COOPER ELECTRONICS
TECHNOLOGIES
SAMTEC
SAMTEC
SAMTEC
SAMTEC
SAMTEC
SAMTEC
53047-0210
HTSW-103-07-SM-S
5747844-6
TSW-104-07-G-S
5179031-5
TSW-105-08-G-D
N2514-6002RB
2-5767004-2
TSW-109-07-S-D
5-146276-5
1053378-1
RAPC722X
1437671-1
TSW-103-07-S-D
BCP52-16
BSH103
CAT16-1002F4LF
HTSW-101-07-SM-S
DR74-101-R
DR125-680-R
TMM-106-01-G-D
DLW43SH101XK2
DR73-470-R
TMM-102-02-G-D
TMM-103-02-G-D
TMM-104-02-G-D
TMM-103-02-G-S
TMM-102-02-G-S
Sept 2007
RN8
RV1
R1,R2,R3,R4
R5,R6,R14,R15,R50,R51,R53
R7,R8,R37,R40
R9,R10,R13,R16,R19,R21,R27,R32,R33,R36,R49,R
52
R11,R12
R17,R18,R42,R47
R20,R24,R25,R28,R29
R22,R44
R23
R30,R31,R48
R34,R35
R38,R45
R41
R43
R46
SW1
SW2,SW3,SW4,SW5
SW6
TPV1,TPV2,TPV3,TPV4,TPV5,TPV6,TPV7,TPV8,TP
V9,TPV10,TPV11,TPV12,TPV13,TPV14,TPV15,TPV
16,TPV17,TPV18,TPV19,TPV20,TPV21,TPV22,TPV
23,TPV24
TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP9,TP10,TP1
1,TP12,TP13,TP14,TP15
U1,U2
U3,U4
U5,U6
U7
U8
U9
U10
MPC5516EVBUM/D
2
2
2
1
1
1
1
15
2
4
5
2
1
3
2
2
1
1
1
1
4
1
24
1
1
4
7
4
12
MPC5516EVB User Manual Rev 1.0
Page B-18
PCA82C250TD
MCZ33399
TJA1080TS/N
MAX232ACSE+
SN74LV125
MC74ACT08DG
74FCT162373ATPACT
TEST POINT
47K
560 OHM
180 OHM
1.2K
470 OHM
270 OHM
60.4OHM
100 OHM
68 OHM
220 OHM
1.80K
KS11R23CQD
B3WN-6002
G-107-0513
TEST POINT
470OHM
2K
47 OHM
0 OHM
1.0K
10K
PHILIPS SEMICONDUCTOR
FREESCALE SEMICONDUCTOR
PHILIPS SEMICONDUCTOR
MAXIM
TEXAS INSTRUMENTS
ON SEMICONDUCTOR
TEXAS INSTRUMENTS
NICOMATIC
BOURNS
YAGEO AMERICA
YAGEO AMERICA
KOA SPEER
BOURNS
SMEC
YAGEO AMERICA
VENKEL COMPANY
YAGEO AMERICA
YAGEO AMERICA
BOURNS
ITT CANNON
OMRON
CW INDUSTRIES
NA
CTS
BOURNS
YAGEO AMERICA
BOURNS
KOA SPEER
VENKEL COMPANY
PCA82C250TD
MCZ33399EF
TJA1080TS/N
MAX232ACSE+
SN74LV125AD
MC74ACT08DG
74FCT162373ATPACT
C12000B
CR0805-FX-4702ELF
232273465601L
232273461801L
RK73B2ATTD122J
CR0805-FX-4700ELF
RC73L2D271JTF
232273466049L
CR08058W1000FSNT
232273466809L
RC0805JR-07220RL
CR0805-FX-1801ELF
KS11R23CQD
B3WN-6002
G-107-0513
NA
742C083471JP
3310Y-001-202L
232273464709L
CR0805-J/-000ELF
RK73H2ATTD1001F
CR0805-8W-103JT
Sept 2007
U16
U18
U19
U20
U21
U22
Y1
1
1
1
1
1
1
1
MPC5516EVBUM/D
U11
U12,U14,U17
U13
U15
1
3
1
1
MPC5516EVB User Manual Rev 1.0
MC33905S
LM2937-5.0
LM2676S-ADJ
LM2676S-3.3
LM2676S-5.0
8MHz
Page B-19
ispGAL22V10AV-28LJC
MAX705CSA+
IS61C6416AL-12TLI
SN74LVC16244ADGGR
ispGAL22V10AV-23LNN
MAXIM
ISSI
TEXAS INSTRUMENTS
LATTICE SEMICONDUCTOR
CORPORATION
LATTICE SEMICONDUCTOR
CORPORATION
FREESCALE SEMICONDUCTOR
NATIONAL SEMICONDUCTOR
NATIONAL SEMICONDUCTOR
NATIONAL SEMICONDUCTOR
NATIONAL SEMICONDUCTOR
ECS INC. INTERNATIONAL
MC33905S
LM2937IMP-5.0/NOPB
LM2676S-ADJ/NOPB
LM2676S-3.3/NOPB
LM2676S-5.0/NOPB
ECS-3953C-080B
ISPGAL22V10AV-28LJC
MAX705CSA+
IS61C6416AL-12TLI
SN74LVC16244ADGGR
ISPGAL22V10AV-23LNNC
Sept 2007
SHEET
SHEET
SHEET
SHEET
2
3
4
5
MPC5516EVBUM/D
These schematics are provided for reference purposes only.
As such, Freescale does not make any warranty, implied or
otherwise, as to the suitability of circuit design or component
selection (type or value) used in these schematics for
hardware design using the Freescale MPC5510 family of
Microprocessors. Customers using any part of these
schematics as a basis for hardware design, do so at their own
risk and Freescale does not assume any liability for such a
hardware design.
Important Note:
Specific PCB LAYOUT notes are detailed in ITALICS
User notes are given throughtout the schematics.
- All unpopulated test points (vias) are denoted as TPVx
- All test points are denoted TPx
- All Switches are denoted SWx
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2
- All jumpers are denoted Jx. Jumpers are 2mm pitch
- All connectors are denoted Px. All connectors and headers are 2.54mm pitch unless otherwise stated
- All decoupling caps greater than 0.1uF are X7R unless otherwise stated
- All decoupling caps less than 0.1uF are COG unless otherwise stated
- Resistor networks are donated RNx. All resistor networks are SMD 1206 style package.
Notes:
MPC5510 144 PIN MCU (1of2) - I/O
MPC5510 144 PIN MCU (2of2) - Power
CLOCK AND PLL CIRCUITRY
EXPANSION CONNECTORS (DAUGHTERCARD)
Table Of Contents:
Date
04 Jan 07
15 Jan 07
16 Jan 07
29 Mar 07
12 Sep 07
Page B-20
Rev
0.1
0.2
0.3
B0
B1
119
120
1
2
1
2
3.5"
Page Title:
Size
B
Drawn by :
M. Stewart
Approv ed:
M. Stewart
Date: Wednesday , September 12, 2007
Sheet
1
SCH-23131 PDF: SPF-23131
Front Page Contents and Notes
of
5
144QFP Daughter Card for MPC5510EVB
Document Number
Drawing Title:
Designer:
M. Stewart
MCD Applications East Kilbride
Colv illes Road, Kelv in Industrial Estate, East Kilbride G75 0TG
Transportation & Standard Products Group
ADAPTER BOARD LAYOUT INSTRUCTIONS
Dimensions in INCHES
CONNECTOR 2 (P2)
CONNECTOR 1 (P1)
0.2"
119
120
Comments
Provisional release
Provisional release (post layout)
Provisional release (post layout fix). PCB RevA
Production Release
Cosmetic changes optimised for A4 - PCB RevB
Connectors
fitted to
UNDERSIDE of
PCB but viewed
and numbered
from TOP side
in this diagram
Designer
M. Stewart
M. Stewart
M. Stewart
M. Stewart
A. Robertson
Revision Information
MPC5510 144QFP MCU Daughter Card
Appendix C - 144QFP Daughtercard Schematics
MPC5516EVB User Manual Rev 1.0
Rev
B1
Sept 2007
TDO
TDI
TMS
TCLK
JCOMP
MPC5516EVBUM/D
5 MCU-RSTx
5
5
5
5
5
4 MCU-XTAL
4 MCU-EXTAL
5 PD[0..15]
5 PC[0..15]
5 PB[0..11]
4 MCU-EXTAL32
4 MCU-XTAL32
4,5 PA[0..15]
TP6
PD[0..15]
GND
R2
104
103
102
101
100
99
98
97
94
93
92
91
90
89
88
87
70
69
72
71
68
0 OHM
TEST
62
MCU-RSTx 10
TDO
TDI
TMS
TCLK
JCOMP
MCU-XTAL 74
MCU-EXTAL75
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PC[0..15]
122
121
120
117
116
115
114
113
112
111
110
109
108
107
106
105
134
133
132
131
130
129
128
127
126
125
124
123
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
9
8
7
6
5
4
3
2
143
142
140
139
138
137
136
135
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
MCU-EXTAL32
MCU-XTAL32
PB[0..11]
PA[0..15]
MPC5516EVB User Manual Rev 1.0
MPC5516 144 LQFP MCU
Part 1of2 - I/O Pins
MPC5516_SKT144
TEST
RESET
TDO
TDI
TMS
TCLK
JCOMP
XTAL
EXTAL
PD0 /CNTX_A
PD1 / CNRX_A
PD2 / CNRX_B / eMIOS[10]
PD3 / CNTX_B / eMIOS[11]
PD4 / CNTX_C / eMIOS[12]
PD5 / CNRX_C / eMIOS[13]
PD6 / TXD_A / eMIOS[14]
PD7 / RXD_A / eMIOS[15]
PD8 / TXD_B/ SCL_A
PD9 / RXD_B / SDA_A
PD10 / PCS_B[2] / CNTX_F / Z1_NMI
PD11 / PCS_B[1] / CNRX_F / Z0_NMI
PD12 / PCS_B[0] / eMIOS[9]
PD13 / SCK_B / eMIOS[8]
PD14 / SOUT_B/ eMIOS[7]
PD15 / SIN_B / eMIOS[6]
PC0 / EMIOS[0] / FR_A_TX_EN / AD[24]
PC1 / EMIOS[1] / FR_A_TX / AD[16]
PC2 / EMIOS[2] / FR_A_RX / TS
PC3 / EMIOS[3] / FR_DBG0
PC4 / EMIOS[4] / FR_DBG1
PC5 / EMIOS[5] / FR_DBG2
PC6 / EMIOS[6] / FR_DBG3
PC7 / EMIOS[7] / FR_B_RX
PC8 / EMIOS[8] / FR_B_TX / AD[15]
PC9 / EMIOS[9] / FR_B_TX_EN / AD[14]
PC10 / EMIOS[10] / PCS_C[5]
PC11 / EMIOS[11] / PCS_C[4]
PC12 / EMIOS[12] / PCS_C[3]
PC13 / EMIOS[13] / PCS_A[5]
PC14 / EMIOS[14] / PCS_A[4]
PC15 / EMIOS[15] / PCS_A[3]
PB0 / AN28 / eMIOS[16] / PCS_C[5]
PB1 /AN29 / eMIOS[17] / PCS_C[4]
PB2 / AN30 / eMIOS[18] / PCS_C[3]
PB3 / AN31 / PCS_C[2]
PB4 / AN32 / PCS_C[1]
PB5 / AN33 / PCS_C[0]
PB6 / AN34 / SCK_C
PB7 / AN35 / SOUT_C
PB8 / AN36 / SIN_C
PB9 / AN37 / CNTX_D / PCS_B[4]
PB10 / AN38 / CNRX_D / PCS_B[3]
PB11 / AN39 / eMIOS[19] / PCS_B[5]
PA0 / AN0
PA1 / AN1
PA2 / AN2
PA3 / AN3
PA4 / AN4
PA5 / AN5
PA6 / AN6
PA7 / AN7
PA8 / AN8
PA9 / AN9
PA10 / AN10
PA11 / AN11
PA12 / AN12
PA13 / AN13
PA14 / PA14 / EXTAL32
PA15 / AN15 / XTAL32
U1A
PE0
PE1
PE2
PE3
PE4
PE5
PE6
EVTI / RD_WR / PF0
EVTO / TA / PF1
MSEO / AD[8] / PF2
MCKO / AD[9] / PF3
MDO[0] / AD[10] / PF4
MDO[1] / AD[11] / PF5
MDO[2] / AD[12] / PF6
MDO[3] / AD[13] / PF7
MDO[4] / AD[14] / PF8
MDO[5] / AD[15] / PF9
MDO[6] / TXD_C / CS[1] / PF10
MDO[7] / RXD_C/ CS[0] / PF11
TXD_D / TS / PF12
RXD_R / OE / PF13
CNTX_D / BDIP / WE[0] / PF14
CNRX_D / TEA / WE[1] / PF15
eMIOS[5] / PCS_A[2] /
eMIOS[4] / PCS_A[1] /
eMIOS[3] / PCS_A[0] /
eMIOS[2] / SCK_A /
eMIOS[1] / SOUT_A /
eMIOS[0] / SIN_A /
CLKOUT /
Page B-21
SCL_A / eMIOS[20] / AN[27] / PH0
SDA_A / eMIOS[21] / AN[26] / PH1
eMIOS[22] / AN[25] / PH2
eMIOS[23] / AN[24] / PH3
MA[2] / TXD_E / AN[23] / PH4
MA[1] / RXD_E / AN[22] / PH5
TXD_F / AN[21] / PH6
RXD_F / AN[20] / PH7
MA[0] / CNTX_E / AN[19] / PH8
CNRX_E / AN[18] / PH9
CNRX_F / AN[17] / PH10
CNTX_F / AN[16] / PH11
eMIOS[16] / AD[16] / PG0
SIN_C / eMIOS[17] / AD[17] / PG1
SOUT_C / eMIOS[18] / AD[18] / PG2
SCK_C/ eMIOS[19] / AD[19] / PG3
PCS_C[0]/ eMIOS[20] / AD[20]/PG4
eMIOS[21] / AD[21] / PG5
eMIOS[22] / AD[22] / PG6
RXD_C / eMIOS[23] / AD[23] / PG7
PCS_A[4] / AD[24] / PG8
TXD_C / PCS_A[3] / AD[25] / PG9
PCS_A[2] / AD[26] / PG10
PCS_A[1] / AD[27] / PG11
PCS_A[0] / AD[28] / PG12
SCK_A / AD[29] / PG13
SOUT_A / AD[30] / PG14
SIN_A / AD[31] / PG15
NEXUS Port Controller
66
65
64
63
59
58
57
56
55
54
52
51
50
49
45
44
24
23
22
21
20
19
18
17
14
13
12
11
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
86
85
84
83
82
81
67
43
42
41
40
39
38
37
36
35
34
30
29
28
27
26
25
PE0
PE1
PE2
PE3
PE4
PE5
PH[0..11]
PG[0..15]
PF[0..15]
4,5
PH[0..11]
PG[0..15]
PF[0..15]
Wednesday , September 12, 2007
Date:
Sheet
2
SCH-23131 PDF: SPF-23131
Document Number
MCU Page 1/2 (I/O)
of
5
144QFP Daughter Card for MPC5510EVB
Rev
B1
MPC5510
144QFP MCU IO
Size
B
Page Title:
5
5
5
MCU-CLKOUT 4
PE[0..6]
Drawing Title:
MCU-CLKOUT
PE[0..6]
Sept 2007
VDDSY N
VDDA
2
2
VDDA
(5.0V)
+
VDDSY N
(3.3V)
MPC5516EVBUM/D
0.1UF
C26
VDD33
U1B
10UF
C25
144
141
1
2
VDD33
(3.3V)
2
1
VDD15
L4
AGND
L5
C15
L6
2
(From VDDSYN
Decoupling and
XTAL CCT Cps)
VSSSY N
AGND
BLM31AJ601SN1L
1
DO NOT FIT
ADC (5v)
BLM31AJ601SN1L
BLM31AJ601SN1L
VDDA
1
REFBYPC
73
VDDSYN
PLL (3.3v)
VSSSYN
76
(1.5V)
C7
1000PF
C53
0.47UF
+
R4
0 OHM
GND
L7
VSSSY N
BLM31AJ601SN1L
VDD15
2
1
77
VDD33
3.3v I/O
470PF
C52
0.47UF
C8
+
C9
0.47UF
C44
C45
1000PF 470PF
C10
0.47UF
+
+
MPC5516_SKT144
C43
1000PF
GND
C6
0.47UF
GND
Page B-22
GND Reference
Points
TP1
TP2
TP3
MPC5516
144QFP
POWER PINS
Route EXTAL / XTAL . XFC in
isolated plane (analogue
signals between VSSSYN and
VDDSYN layer)
Keep CLKOUT AWAY from analogue
signals (EXTAL, XTAL etc)
Layout Notes (Important):
R6
0 OHM
GND
(VSS33a)
+
R3
0 OHM
31
53
79
31-VDD
53-VDD
79-VDD
1.5v Logic
2
1
C29
1000PF
GND
C30
0.1UF
2
GND
GND Links
GND
I/O 3.3 OR 5v
AGND
GND
BLM31AJ601SN1L
1
L2
GROUND PINS
C49
470PF
C48
0.1UF
96
119
MPC5516EVB User Manual Rev 1.0
1
VSSA
2
1
78
VPP
Flash
Supply (5v)
46
VDDR
Regs(5v)
VSS-80
80
VSSE1-95
VSSE1-118
95
118
VSSE3-60
60
VSSE2-15
VSSE2-32
VSSE2-47
15
32
47
96-VDDE1
119-VDDE1
16
33
48
16-VDDE2
33-VDDE2
48-VDDE2
61
61-VDDE3
GND
C19
470PF
GND
VDDE3
GND
C12
1000PF
C22
470PF
C23
1000PF
VDDE2
C37
470PF
VDDE3
VDDE2
VDDE1
VPP
VDDR
2
2
2
2
2
Wednesday , September 12, 2007
Date:
Sheet
3
SCH-23131 PDF: SPF-23131
Document Number
MCU Page 2/2 (Power)
of
5
144QFP Daughter Card for MPC5510EVB
C18
0.1UF
(5V/3.3V)
C11
0.1UF
C27
0.1UF
C28
0.1UF
(5V/3.3V)
C36
0.1UF
Size
B
Page Title:
Drawing Title:
VDDE1
(5V/3.3V)
C41
1000PF
VPP
(5V)
C38
0.1UF
VDDR
(5V)
Rev
B1
MPC5510 176QFP MCU PWR
Sept 2007
FID6
FID5
FID7
FID3
FID8
FID4
MPC5516EVBUM/D
Connect XTAL jumper to GND when driving EXTAL from
Oscilaltor Module or External Source (PLL Bypass
Mode)
REMOVE XTAL jumper when driving EXTAL from
Oscilaltor Module or External Source (PLL Enabled)
Route EXTAL / XTAL in isolated
plane (analogue signals between
VSSSYN and VDDSYN layer)
Keep MCU-CLKOUT AWAY from
analoguesignals (EXTAL, XTAL etc)
Layout Notes (Important):
FID2
FID1
MPC5516EVB User Manual Rev 1.0
10PF
Y1
10PF
XTAL32
32.768KHz
EXTAL32
VSSSY N
Y2
33PF
33PF
R5 0 OHM
8MHz
J5
Page B-23
XTAL
Loop Controlled Pierce
Oscillator Circuit
C55
C54
EXTAL
1
GND
3
1
3
1
3
1
PA14
PA15
1
3
J3
J4
J1
J2
2
R7 33.0 OHM
PE[0..6]
PE[0..6]
MCU-EXTAL32
(MCU 32KHz EXTAL)
MCU-CLKOUT
2
2
2
MCU-XTAL
(MCU Crystal Output)
EVB-EXTAL
(FROM Expansion
Connectors)
MCU-EXTAL
(MCU Crystal Input)
MCU-XTAL32
(MCU 32KHz XTAL)
PA[0..15]
(TO Expansion Connectors)
2
(FROM MCU)
2
5
2
2
2,5
2
2
2,5
Wednesday , September 12, 2007
Date:
Sheet
4
SCH-23131 PDF: SPF-23131
Document Number
Clock Circuitry
of
5
144QFP Daughter Card for MPC5510EVB
Rev
B1
CLOCK CIRCUITRY
Size
B
Page Title:
Drawing Title:
MCU-XTAL
EVB-EXTAL
MCU-EXTAL
MCU-XTAL32
PA[0..15]
MCU-EXTAL32
MCU-CLKOUT
PE6
(TO Expansion Connectors)
Place resistor as close as
possible to MCU CLKOUT pin
32Khz Oscillator Circuit
GND
C24
C31
2
1
2
1
Sept 2007
PA[0..15]
PB[0..11]
VDDA
VDD15
VDDE2
2,4
2
3
3
3
2
PG[0..15]
PF[0..15]
MCU-RSTx
2
2
2
MCU-RSTx
PF[0..15]
PG[0..15]
RST-OUTx
TGT-RSTx
VDDR
(Jumpered)
MPC5516EVBUM/D
TP5
TP4
VDDR
LED GREEN
3
GND
1
D1
R1 560 OHM
VDDE2
(Jumpered)
VDD15
(Jumpered)
F
B
PB2
PK0
PA8
VDDA
VDD15
1
3
5
7
9
(NC) 11
13
15
17
19
21
GND 23
25
27
29
31
33
GND 35
(NC) 37
39
41
43
45
GND 47
49
51
53
55
57
GND 59
61
63
65
67
69
GND 71
73
75
77
79
81
GND 83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
J6
PG1
PG4
VDD15
PJ7
PF13
PG2
PG5
VDD15
(NC)
PF9
PG10
PF7
PF14
PG0
VDDE2
PG12
PG14
PF8
PF12
VDDE2
PH7
PH4
PJ9
VDDE2
PH0
PH9
VDDE2
PJ11
PJ12
PJ10
PA1
PH10
PH11
PH13
PA15
PA6
PB5
PA14
PA10
PA4
PB13
VDD15
PA12
PB4
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
PF[0..15]
PG[0..15]
GND
MCU-RSTx
G
K
B
PB12
2
PA13
4
6 (NC)
VDDA
8
VDD15
10
PB3
12
PK1
14
VDD15
16
18 GND
PB0
20
PA11
22
PA9
24
PA7
26
PB1
28
30 GND
PA3
32
PA5
34
MCU-RSTx
36
PA0
38
PA2
40
42 GND
PH12
44
PJ13
46
PJ14
48
PJ15
50
VDDE2
52
54 GND
PH8
56
PH5
58
PH6
60
PH3
62
PJ8
64
66 GND
VDDE2
68
PH1
70
PH2
72
PG13
74
PG15
76
78 GND
PF15
80
VDDE2
82
PG9
84
PG11
86
PF11
88
90 GND
PG3
92
VDDE2
94
PG8
96
PF10
98
PH15
100
(NC)
102
PG7
104
VDD15
106
PF6
108
PH14
110
VDDR
112
(NC)
114
PG6
116
118 VDD15
RST-OUTx
120
Connector 1
CON 2X60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
F
A
H
PF[0..15]
VDD15
PB[0..11]
D
F
C
E
B
GND
Page B-24
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
PF[0..15]
PE[0..6]
GND
2
4
6 GND
8
10
12
14
16
18 GND
20
22
24
26
28
30 GND
32
34
36
38
40
42 GND
44
46
48
50
52
54 GND
56
58
60
62
64
66 GND
68
70
72
74
76
78 GND
80
82
84
86
88
90 GND
92
94
96
98
100
102GND
104
106
108
110
112
114
116
118
120
Conenctor 2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
J7
PB[0..11]
PC[0..15]
PD[0..15]
CON 2X60
1
PB15 3
PC7
5
VDDE1 7
VDD15
9
GND 11
PB7
13
PC0
15
PC8
17
VDD15
19
PC11
21
GND 23
PB14
25
PC5
27
PC13
29
PC14
31
VDDE1
33
GND 35
PC6
37
PD0
39
PD2
41
VDDE1
43
PD3
45
GND 47
PD6
49
PD9
51
PD10
53
VDDE1
55
PD11
57
PE7
59
PE8
61
PD14
63
PE10
65
PE12
67
VDDE1
69
GND 71
PE13
73
PE2
75
PE3
77
PE15
79
VDDE3
81
GND 83
PJ0
85
VDD33
87
PE4
89
EVB-EXTAL
91
PJ4
93
GND 95
VPP
97
PE6
99
PJ3
101
PF2
103
VDD15
105
(NC)
107
VDDSY N
109
PJ5
111
VDDE3
113
VDDE3
115
JCOMP
117
TMS
119
PB6
CONNECTORS MUST BE PLACED IN ACCORDANCE WITH PCB SPECIFICATION
G
K
PB[0..11]
PB[0..11]
A
PA[0..15]
PA[0..15]
H
PH[0..11]
PH[0..11]
VDDA
(Jumpered)
Power LED
PH[0..11]
2
MPC5516EVB User Manual Rev 1.0
E
PF4
(NC)
PF3
TDO
VDD15
TDI
VDD15
TCLK
PJ6
PJ1
PF1
VPP
PF5
PE5
VDDE3
PJ2
PF0
PD15
VDDE1
PE0
PE1
PE14
VDDE1
PD12
PD13
PE9
PE11
VDDE1
PD4
PD5
PD7
PD8
PB9
VDDE1
PC2
PC15
PD1
VDD15
PC12
PB8
PC1
PC9
VDD15
PC10
PB11
PC4
B
PB10
PC3
C
F
D
2,4
2
2
4
3
2
2
3
2
3
3
3
2
2
Wednesday , September 12, 2007
Date:
Sheet
5
SCH-23131 PDF: SPF-23131
Daughter Card Connectors
Document Number
of
5
Rev
B1
DAUGHTERCARD
CONNECTORS
144QFP Daughter Card for MPC5510EVB
PE[0..6]
TMS
JCOMP
EVB-EXTAL
VDDE3
TDO
TCLK
VDDSY N
TDI
VPP
VDD33
VDDE1
PC[0..15]
PD[0..15]
Size
B
Page Title:
Drawing Title:
PE[0..6]
VDDE3
(Jumpered)
TMS
JCOMP
EVB-EXTAL
TDO
TCLK
VDDSY N
(Jumpered)
TDI
VPP
(Jumpered)
VDD33
(Jumpered)
VDDE1
(Jumpered)
PC[0..15]
Sept 2007
Refdes
C6,C7,C8,C9,C10
C11,C15,C18,C26,C27,C28,C30,C36,C38,C48
C12,C23,C29,C41,C43,C44,C53
C19,C22,C37,C45,C49,C52
C24,C31
C25
C54,C55
D1
FID1,FID2,FID3,FID4,FID5,FID6,FID7,FID8
J1,J2,J3,J4
J5
J6,J7
L2,L4,L5,L6,L7
R1
R2,R3,R4,R5,R6
MPC5516EVBUM/D
Qty
5
10
7
6
2
1
2
1
8
4
1
2
5
1
5
Value
0.47UF
0.1UF
1000PF
470PF
10PF
10UF
33PF
LED GREEN
FID-040
HDR 3X1
HDR 1X2
CON 2X60
BLM31AJ601SN1L
560 OHM
0 OHM
Appendix D - 144QFP Daughtercard Bill Of Materials
MPC5516EVB User Manual Rev 1.0
Page B-25
Manufacturer
AVX
MURATA
VENKEL COMPANY
PANASONIC
KEMET
VISHAY INTERTECHNOLOGY
VENKEL COMPANY
KINGBRIGHT
GENERIC
SAMTEC
SAMTEC
TYCO ELECTRONICS
MURATA
KOA SPEER
THYE MING TECH CO LTD
Part Number
TAJA474M025R
GRM188R71H104KA93D
C0805COG500-102JNE
ECJ1VC1H471J
C0603C100F5GAC
293D106X9010A2TE3
C0603C0G500-330JNE
K/APT-3216SGD
FID-040
TMM-103-02-G-S
TMM-102-02-G-S
5-5179009-5
BLM31AJ601SN1L
RK73H1JTTD5600F
CR-03JL7-0R
Sept 2007
SHEET
SHEET
SHEET
SHEET
2
3
4
5
MPC5516EVBUM/D
These schematics are provided for reference purposes only.
As such, Freescale does not make any warranty, implied or
otherwise, as to the suitability of circuit design or component
selection (type or value) used in these schematics for
hardware design using the Freescale MPC5510 family of
Microprocessors. Customers using any part of these
schematics as a basis for hardware design, do so at their own
risk and Freescale does not assume any liability for such a
hardware design.
Important Note:
Specific PCB LAYOUT notes are detailed in ITALICS
User notes are given throughtout the schematics.
- All unpopulated test points (vias) are denoted as TPVx
- All test points are denoted TPx
- All Switches are denoted SWx
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2
- All jumpers are denoted Jx. Jumpers are 2mm pitch
- All connectors are denoted Px. All connectors and headers are 2.54mm pitch unless otherwise stated
- All decoupling caps greater than 0.1uF are X7R unless otherwise stated
- All decoupling caps less than 0.1uF are COG unless otherwise stated
- Resistor networks are donated RNx. All resistor networks are SMD 1206 style package.
Notes:
MPC5510 176 PIN MCU (1of2) - I/O
MPC5510 176 PIN MCU (2of2) - Power
CLOCK AND PLL CIRCUITRY
EXPANSION CONNECTORS (DAUGHTERCARD)
Table Of Contents:
Date
13 Jun 07
08 Aug 07
15 Aug 07
20 Aug 07
12 Sept 07
Page B-26
Rev
0.1
B0
B1
B2
C0
119
120
1
2
1
2
3.5"
Page Title:
Size
B
Drawn by :
A. Robertson
Approv ed:
A. Robertson
Date: Wednesday , September 12, 2007
Sheet
1
SCH-23553 PDF: SPF-23553
Front Page Contents and Notes
of
5
176QFP Daughter Card for MPC5510EVB
Document Number
Drawing Title:
Designer:
A. Robertson
MCD Applications East Kilbride
Colv illes Road, Kelv in Industrial Estate, East Kilbride G75 0TG
Transportation & Standard Products Group
ADAPTER BOARD LAYOUT INSTRUCTIONS
Dimensions in INCHES
CONNECTOR 2 (P2)
CONNECTOR 1 (P1)
0.2"
119
120
Comments
Prototype release - PCB RevA
Correction to VDDE1 short
Production Release - PCB RevB (Not manufactured)
Correction to Clock Selection Jumpers
Production Release - PCB RevC
Connectors
fitted to
UNDERSIDE of
PCB but viewed
and numbered
from TOP side
in this diagram
Designer
A. Robertson
A. Robertson
A. Robertson
A. Robertson
A. Robertson
Revision Information
MPC5510 176QFP MCU Daughter Card
Appendix E - 176QFP Daughtercard Schematics
MPC5516EVB User Manual Rev 1.0
Rev
C0
Sept 2007
PB[0..15]
PC[0..15]
PD[0..15]
MCU-EXTAL32
MCU-XTAL32
MCU-XTAL
MCU-EXTAL
TDO
TDI
TMS
TCLK
JCOMP
MCU-RSTx
3,5
5
5
4
4
4
4
5
5
5
5
5
5
MPC5516EVBUM/D
PA[0..15]
5
128
127
126
125
124
123
122
121
118
117
116
115
114
113
110
107
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD[0..15]
TP100
146
145
144
141
140
139
138
137
136
135
134
133
132
131
130
129
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC[0..15]
TEST
R100 0 OHM
GND
86
85
88
87
84
90
91
78
MCU-RSTx 10
TDO
TDI
TMS
TCLK
JCOMP
MCU-XTAL
MCU-EXTAL
168
166
162
161
160
159
158
157
156
153
152
151
150
149
164
163
148
147
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB[0..15]
MCU-EXTAL32
MCU-XTAL32
9
8
7
6
5
4
3
2
175
174
172
171
170
169
167
165
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA[0..15]
MPC5516EVB User Manual Rev 1.0
MPC5516 176QFP
I/O Pins
MPC5516_SKT176
VSUP/TEST
RESET
TDO
TDI
TMS
TCK
JCOMP
XTAL
EXTAL/EXTCLK
PK0/EXTAL32
PK1/XTAL32
PD0/CNTX_A/PCS_D[3]
PD1/CNRX_A/PCS_D[4]
PD2/CNRX_B/eMIOS[10]/BOOTCFG
PD3/CNTX_B/eMIOS[11]
PD4/CNTX_C/eMIOS[12]
PD5/CNRX_C/eMIOS[13]
PD6/TXD_A/eMIOS[14]
PD7/RXD_A/eMIOS[15]
PD8/TXD_B/SCL_A
PD9/RXD_B/SDA_A
PD10/PCS_B[2]/CNTX_F/NMI0
PD11/PCS_B[1]/CNRX_F/NMI1
PD12/PCS_B[0]/eMIOS[9]
PD13/SCK_B/eMIOS[8]
PD14/SOUT_B/eMIOS[7]
PD15/SIN_B/eMIOS[6]
PC0/eMIOS[0]/FR_A_TX_EN
PC1/eMIOS[1]/FR_A_TX
PC2/eMIOS[2]/FR_A_RX
PC3/eMIOS[3]/FR_DBG0
PC4/eMIOS[4]/FR_DBG1
PC5/eMIOS[5]/FR_DBG2
PC6/eMIOS[6]/FR_DBG3
PC7/eMIOS[7]/FR_B_RX
PC8/eMIOS[8]/FR_B_TX
PC9/eMIOS[9]/FR_B_TX_EN
PC10/eMIOS[10]/PCS_C[5]
PC11/eMIOS[11]/PCS_C[4]
PC12/eMIOS[12]/PCS_C[3]
PC13/eMIOS[13]/PCS_A[5]
PC14/eMIOS[14]/PCS_A[4]
PC15/eMIOS[15]/PCS_A[3]
PB0/AN28/eMIOS[16]/PCS_C[5]
PB1/AN29/eMIOS[17]/PCS_C[4]
PB2/AN30/eMIOS[18]/PCS_C[3]
PB3/AN31/PCS_C[2]
PB4/AN32/PCS_C[1]
PB5/AN33/PCS_C[0]
PB6/AN34/SCK_C
PB7/AN35/SOUT_C
PB8/AN36/SIN_C
PB9/AN37/CNTX_D/PCS_B[4]
PB10/AN38/CNRX_D/PCS_B[3]
PB11/AN39/eMIOS[19]/PCS_B[5]
PB12/TXD_G/PCS_B[4]
PB13/RXD_G/PCS_B[3]
PB14/TXD_H
PB15/RXD_H
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
PA8/AN8
PA9/AN9
PA10/AN10
PA11/AN11
PA12/AN12
PA13/AN13
PA14 / PA14/EXTAL32
PA15 / AN15/XTAL32
U1A
NEXUS Port Controller
PG[0..15]
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
PH14
PH15
53
52
75
73
69
67
27
26
25
19
18
16
15
13
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
32
31
30
29
28
24
23
22
17
14
12
11
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
82
81
80
79
74
72
68
66
65
64
62
61
60
59
55
54
51
50
49
48
47
46
45
44
43
42
38
37
36
35
34
33
PF[0..15]
PE10
PE11
PE12
PE13
PE14
PE15
TPV2
TPV4
TPV7
TPV6
TPV5
Not available
on 176QFP
Not available
on 176QFP
PJ[4..15]
(PJ[0..3] not availble on 176QFP)
PH12
PH13
PH[0..15]
PE7
PE8
PE9
112
111
109
108
102
99
MCU-CLKOUT
PE0
PE1
PE2
PE3
PE4
PE5
106
103
101
100
98
97
83
Page B-27
PJ4
PJ5
PJ6
PJ7
PCS_D[4]/PJ8
PCS_D[3]/PJ9
PCS_D[2]/PJ10
PCS_D[1]/PJ11
PCS_D[0]/PJ12
SCK_D/PJ13
SOUT_D/PJ14
SIN_D/PJ15
PH14
PH15
SCL_A/eMIOS[20]/AN[27]/PH0
SDA_A/eMIOS[21]/AN[26]/PH1
CS[3]/eMIOS[22]/AN[25]/PH2
CS[2]/eMIOS[23]/AN[24]/PH3
MA[2]/TXD_E/AN[23]/PH4
MA[1]/RXD_E/AN[22]/PH5
TXD_F/AN[21]/PH6
RXD_F/AN[20]/PH7
MA[0]/CNTX_E/AN[19]/PH8
CNRX_E/AN[18]/PH9
CNRX_F/AN[17]/PH10
CNTX_F/AN[16]/PH11
eMIOS[16]/AD[16]/PG0
SIN_C/eMIOS[17]/AD[17]/PG1
SOUT_C/eMIOS[18]/AD[18]/PG2
SCK_C/eMIOS[19]/AD[19]/PG3
PCS_C[0]/eMIOS[20]/AD[20]/PG4
eMIOS[21]/AD[21]/PG5
eMIOS[22]/AD[22]/PG6
RXD_C/eMIOS[23]/AD[23]/PG7
PCS_A[4]/AD[24]/PG8
TXD_C/PCS_A[3]/AD[25]/PG9
PCS_A[2]/AD[26]/PG10
PCS_A[1]/AD[27]/PG11
PCS_A[0]/AD[28]/PG12
SCK_A/AD[29]/PG13
SOUT_A/AD[30]/PG14
SIN_A/AD[31]/PG15
EVTI/RD_WR/PF0
EVTO/MLBCLK/TA/PF1
MSEO/MLBSI/AD[8]/PF2
MCKO/MLBDI/AD[9]/PF3
MDO[0]/MLBSO/AD[10]/PF4
MDO[1]/MLBDO/AD[11]/PF5
MDO[2]/MLB_SLOT/AD[12]/PF6
MDO[3]/AD[13]/PF7
MDO[4]/AD[14]/PF8
MDO[5]/AD[15]/PF9
MDO[6]/TXD_C/CS[1]/PF10
MDO[7]/RXD_C/CS[0]/PF11
TXD_D/TS/PF12
RXD_D/OE/PF13
CNTX_D/BDIP/WE[0]/PF14
CNRX_D/TEA/WE[1]/PF15
PE10
PE11
PE12
PE13
PE14
PE15
MLBCLK/eMIOS[5]/PCS_A[2]/PE0
MLBSI/eMIOS[4]/PCS_A[1]/PE1
MLBDI/eMIOS[3]/PCS_A[0]/PE2
MLBSO/eMIOS[2]/SCK_A/PE3
MLBDO/eMIOS[1]/SOUT_A/PE4
MLB_SLOT/eMIOS[0]/SIN_A/PE5
CLKOUT/PE6
PE[0..15]
PJ[4..15]
PH[0..15]
PG[0..15]
PF[0..15]
Date:
5
Wednesday , September 12, 2007
Sheet
2
SCH-23553 PDF: SPF-23553
MCU Page 1/2 (I/O)
of
5
176QFP Daughter Card for MPC5510EVB
5
5
5
PJ0, PJ1. PJ2, PJ3
PH12, PH13
PE7, PE8, PE9
Rev
C0
MPC5510
176QFP MCU IO
Signals not available on 176 QFP
Document Number
Page Title:
Drawing Title:
Size
B
4,5
MCU-CLKOUT 4
PE[0..15]
Sept 2007
VDD33
VDDSYN
VDDA
5
5
5
MPC5516EVBUM/D
0.1UF
C100
VDD15
VDDSY N
VDDA
(3.3V)
(5.0V)
U1B
+ C101
10UF
VDD33
(3.3V)
BLM31AJ601SN1L
2,5
VDD15
L100
AGND
0.1UF
C102
AGND
(From VDDSYN
Decoupling and
XTAL CCT Cps)
VSSSY N
ADC (5v)
L103
2
BLM31AJ601SN1L
1
DO NOT FIT
L102
BLM31AJ601SN1L
1
1
2
176
VDDA/VRH
VSSA/VRL
173
REFBYPC
89
GND
+
R102
0 OHM
VSSSYN
L104
PLL
(3.3v)
VDDSYN
VSSSYN
R103
0 OHM
3.3v I/O
GND
(VSS33a)
0.47UF
C6
+
R101
0 OHM
1.5v Logic
+
+
+
(1.5V)
BLM31AJ601SN1L
93
VFLASH/VDD33
39
63
95
39-VDD
63-VDD
95-VDD/VDDF
VSS/VSSF-96
96
0.47UF
C43
C4
0.47UF
0.47UF
C2
C105
GND
56
GND
Regs
(5v)
GND Reference
Points
TP2
TP3
TP1
Page B-28
GROUND PINS
MPC5516 176QFP
POWER PINS
470PF
C121
1000PF
C114
470PF
GND
L101
21
41
58
71
77
I/O 3.3 OR 5v
2
GND Links
AGND
GND
BLM31AJ601SN1L
1
Flash
Supply
(5v)
GND
105
120
143
155
MPC5516EVB User Manual Rev 1.0
1
92
1
2
1
2
1
1000PF
1
VDDR
94
VPP
0.47UF
105-VDDE1
120-VDDE1
143-VDDE1
155-VDDE1
C127
470PF
VSSE1-104
VSSE1-119
VSSE1-142
VSSE1-154
C128
21-VDDE2
41-VDDE2
58-VDDE2
C122
104
119
142
154
1000PF
VSSE2-20
VSSE2-40
VSSE2-57
C3
20
40
57
C109 0.1UF
VSSE3-70
VSSE3-76
470PF
Sept 2007
GND
0.1UF
C119
0.1UF
C118
(5V/3.3V)
0.1UF
C110
0.1UF
C106
0.1UF
C104
(5V/3.3V)
0.1UF
C112
0.1UF
1000PF
C5
470PF
C115
470PF
C111
1000PF
C1
470PF
C103
470PF
C113
1000PF
C117
VDDE2
GND
VDDE3
GND
VDDE3
VDDE2
Wednesday , September 12, 2007
Date:
Sheet
3
SCH-23553 PDF: SPF-23553
MCU Page 2/2 (Power)
Document Number
Size
B
Page Title:
C124
0.1UF
470PF
1000PF
C123
C116
C7
0.1UF
VDDE1
VPP
VDDR
5
5
5
5
5
of
5
176QFP Daughter Card for MPC5510EVB
MPC5516_SKT176
VDDE1
(5V/3.3V)
GND
VPP
(5V)
C120
VDDR
(5V)
Rev
C0
MPC5510 176QFP MCU PWR
Drawing Title:
70
76
C126
71-VDDE3
77-VDDE3
C125 0.1UF
MPC5516EVBUM/D
REMOVE XTAL jumper when driving EXTAL from
Oscilaltor Module or External Source (PLL Enabled)
Connect XTAL jumper to GND when driving EXTAL from
Oscilaltor Module or External Source (PLL Bypass
Mode)
Route EXTAL / XTAL in isolated
plane (analogue signals between
VSSSYN and VDDSYN layer)
Keep MCU-CLKOUT AWAY from
analoguesignals (EXTAL, XTAL etc)
Layout Notes (Important):
MPC5516EVB User Manual Rev 1.0
10PF
Y1
10PF
XTAL32
32.768KHz
EXTAL32
VSSSYN
33PF
Y2
R1040 OHM
8MHz
1
3
GND
3
1
3
1
3
1
PK0
PK1
HDR 1X2
J5
Page B-29
XTAL
Loop Controlled Pierce
Oscillator Circuit
C129
C130 33PF
EXTAL
1
J3
J4
J1
J2
2
R2 33.0 OHM
PE[0..15]
2
2
2
2
(FROM MCU)
EVB-EXTAL
(FROM Expansion
Connectors)
MCU-EXTAL
(MCU Crystal Input)
MCU-XTAL32
(MCU 32KHz XTAL)
PK[0..1]
(TO Expansion
Connectors)
MCU-EXTAL32
(MCU 32KHz EXTAL)
MCU-CLKOUT
PE6
(TO Expansion Connectors)
Place resistor as close as
possible to MCU CLKOUT pin
32Khz Oscillator Circuit
GND
C108
C107
2
1
2
1
H DR 3X1
HD R 3X1
HD R 3X1
MCU-XTAL
(MCU Crystal Output)
HD R 3X1
2
5
2
2
5
2
2
2,5
Wednesday , September 12, 2007
Date:
Sheet
4
SCH-23553 PDF: SPF-23553
Document Number
Clock Circuitry
of
5
176QFP Daughter Card for MPC5510EVB
Size
B
Page Title:
Drawing Title:
MCU-XTAL
EVB-EXTAL
MCU-EXTAL
MCU-XTAL32
PK[0..1]
MCU-EXTAL32
MCU-CLKOUT
PE[0..15]
Rev
C0
CLOCK CIRCUITRY
Sept 2007
VDDA
VDD15
VDDE2
3
2,3
3
VDDE2
(Jumpered)
VDD15
(Jumpered)
VDDA
(Jumpered)
1
PF[0..15]
PH[0..15]
MCU-RSTx
2
2
2
1
3
5
7
9
(NC) 11
13
15
17
19
21
GND 23
25
27
29
31
33
GND 35
(NC) 37
39
41
43
45
GND 47
49
51
53
55
57
GND 59
61
63
65
67
69
GND 71
73
75
77
79
81
GND 83
85
87
89
91
93
95
97
99
101
103
105
(NC)107
109
111
113
115
117
119
MCU-RSTx
MCU-RSTx
GND
J
G
B
K
PB12
2
PA13
4
(NC)
6
VDDA
8
VDD15
10
PB3
12
PK1
14
VDD15
16
GND
18
PB0
20
PA11
22
PA9
24
PA7
26
PB1
28
GND
30
PA3
32
PA5
34
MCU-RSTx
36
PA0
38
PA2
40
GND
42
PH12
44
PJ13
46
PJ14
48
PJ15
50
VDDE2
52
GND
54
PH8
56
PH5
58
PH6
60
PH3
62
PJ8
64
GND
66
VDDE2
68
PH1
70
PH2
72
PG13
74
PG15
76
GND
78
PF15
80
VDDE2
82
PG9
84
PG11
86
PF11
88
GND
90
PG3
92
VDDE2
94
PG8
96
PF10
98
PH15
100
102 (NC)
PG7
104
VDD15
106
PF6
108
PH14
110
VDDR
112
114 (NC)
PG6
116
VDD15
118
RST-OUTx
120
F
A
H
PF[0..15]
PJ[4..15]
VDD15
PB[0..15]
F
D
J
C
E
B
GND
1
3
5
VDDE1 7
VDD15
9
GND 11
PB7
13
PC0
15
PC8
17
VDD15
19
PC11
21
GND 23
PB14
25
PC5
27
PC13
29
PC14
31
VDDE1
33
GND 35
PC6
37
PD0
39
PD2
41
VDDE1
43
PD3
45
GND 47
PD6
49
PD9
51
PD10
53
VDDE1
55
PD11
57
PE7
59
PE8
61
PD14
63
PE10
65
PE12
67
VDDE1
69
GND 71
PE13
73
PE2
75
PE3
77
PE15
79
VDDE3
81
GND 83
PJ0
85
VDD33
87
PE4
89
EVB-EXTAL
91
PJ4
93
GND 95
VPP
97
PE6
99
PJ3
101
PF2
103
VDD15
105
(NC)107
VDDSY N
109
PJ5
111
VDDE3
113
VDDE3
115
JCOMP
117
TMS
119
PB6
PB15
PC7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
PF[0..15]
PJ[4..15]
PE[0..15]
Page B-30
GND
2
4
6 GND
8
10
12
14
16
18 GND
20
22
24
26
28
30 GND
32
34
36
38
40
42 GND
44
46
48
50
52
54 GND
56
58
60
62
64
66 GND
68
70
72
74
76
78 GND
80
82 VDDE3
84
86
88
90 GND
92
94
96
98
100
102 GND
104
106
108
110
112
114 (NC)
116
118
120
Conenctor 2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
P101
PB[0..15]
PC[0..15]
PD[0..15]
CONNECTORS MUST BE PLACED IN ACCORDANCE WITH PCB SPECIFICATION
PH[0..15]
PJ[4..15]
PF[0..15]
J
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
Conenctor 1
PH[0..15]
G
GND
PF[0..15]
F
PG1
PG4
VDD15
PF9
PJ7
PF13
PG2
PG5
VDD15
PG10
PF7
PF14
PG0
VDDE2
PG12
PG14
PF8
PF12
VDDE2
PH7
PH4
PJ9
VDDE2
PH0
PH9
VDDE2
PJ11
PJ12
PJ10
PA1
PH10
PH11
PH13
PA15
PA6
PB5
PA14
PA10
PA4
PB13
VDD15
PA12
PB4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
P100
PG[0..15]
H
PB2
PK0
PA8
VDDA
VDD15
PG[0..15]
PJ[4..15]
MPC5516EVBUM/D
PG[0..15]
RST-OUTx
TPV1
PJ[4..15]
TGT-RSTx
VDDR
(Jumpered)
GND
TPV3
VDDR
LED GREEN
DS1
2
2
B
PB[0..15]
PB[0..15]
K
PK[0..1]
PK[0..1]
A
PA[0..15]
PA[0..15]
R1 560 OHM
2
3
PB[0..15]
Power LED
PK[0..1]
4
PA[0..15]
2,3
2
MPC5516EVB User Manual Rev 1.0
E
PF3
TDO
VDD15
PF4
TDI
VDD15
TCLK
PF5
PJ6
PJ1
PF1
PJ2
PF0
PE5
PD15
VDDE1
PE0
PE1
PE14
VDDE1
PD12
PD13
PE9
PE11
VDDE1
PD4
PD5
PD7
PD8
PB9
VDDE1
PC2
PC15
PD1
VDD15
PC12
PB8
PC1
PC9
VDD15
PC10
PB11
PC4
B
PB10
PC3
J
C
F
D
2,4
2
2
4
3
2
2
3
2
3
3
3
2
Wednesday , September 12, 2007
Date:
Sheet
5
SCH-23553 PDF: SPF-23553
Daughter Card Connectors
Document Number
of
5
Rev
C0
DAUGHTERCARD
CONNECTORS
176QFP Daughter Card for MPC5510EVB
PE[0..15]
TMS
JCOMP
EVB-EXTAL
VDDE3
TDO
TCLK
VDDSY N
TDI
VPP
VDD33
VDDE1
PC[0..15]
2
Size
B
Page Title:
Drawing Title:
PE[0..15]
VDDE3
(Jumpered)
TMS
JCOMP
EVB-EXTAL
TDO
TCLK
VDDSY N
(Jumpered)
TDI
VPP
(Jumpered)
VDD33
(Jumpered)
VDDE1
(Jumpered)
PC[0..15]
PD[0..15]
Sept 2007
Refdes
C1,C3,C5,C7,C114,C117,C127
C2,C4,C6,C43,C128
C100,C102,C104,C106,C109,C110,C112,C116,C118
,C119,C120,C123,C125
C101
C103,C105,C111,C113,C115,C121,C122,C124,C126
C107,C108
C129,C130
DS1
J1,J2,J3,J4
J5
L100,L101,L102,L103,L104
P100,P101
R1
R2
R100,R101,R102,R103,R104
TPV1,TPV2,TPV3,TPV4,TPV5,TPV6,TPV7,TP100
TP1,TP2,TP3
U1
Y1
Y2
MPC5516EVBUM/D
13
1
9
2
2
1
4
1
5
2
1
1
5
8
3
1
1
1
Qty
7
5
0.1UF
10UF
470PF
10PF
33PF
LED GREEN
HDR 3X1
HDR 1X2
BLM31AJ601SN1L
CON 2X60
560 OHM
33.0 OHM
0 OHM
TEST POINT
TP_2MMX1.3MM
MPC5516_SKT176
32.768KHz
8MHz
Value
1000PF
0.47UF
Appendix F - 176QFP Daughtercard Bill Of Materials
MPC5516EVB User Manual Rev 1.0
Page B-31
MURATA
VISHAY INTERTECHNOLOGY
PANASONIC
KEMET
VENKEL COMPANY
KINGBRIGHT
SAMTEC
SAMTEC
MURATA
TYCO ELECTRONICS
KOA SPEER
KOA SPEER
THYE MING TECH CO LTD
NA
N/A
Subassembly
VISHAY INTERTECHNOLOGY
C-MAC MICROTECHNOLOGY
Manufacturer
VENKEL COMPANY
AVX
GRM188R71H104KA93D
293D106X9010A2TE3
ECJ1VC1H471J
C0603C100F5GAC
C0603C0G500-330JNE
K/APT-3216SGD
TMM-103-02-G-S
TMM-102-02-G-S
BLM31AJ601SN1L
5-5179009-5
RK73H1JTTD5600F
RK73H1JTTD33R0F
CR-03JL7-0R
NA
N/A
210-77332, 344-00384
XT26TTA32K768
LF A140K
Part Number
C0805COG500-102JNE
TAJA474M025R
Sept 2007
SHEET
SHEET
SHEET
SHEET
2
3
4
5
MPC5516EVBUM/D
These schematics are provided for reference purposes only.
As such, Freescale does not make any warranty, implied or
otherwise, as to the suitability of circuit design or component
selection (type or value) used in these schematics for
hardware design using the Freescale MPC5510 family of
Microprocessors. Customers using any part of these
schematics as a basis for hardware design, do so at their own
risk and Freescale does not assume any liability for such a
hardware design.
Important Note:
Specific PCB LAYOUT notes are detailed in ITALICS
User notes are given throughtout the schematics.
- All unpopulated test points (vias) are denoted as TPVx
- All test points are denoted TPx
- All Switches are denoted SWx
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2
- All jumpers are denoted Jx. Jumpers are 2mm pitch
- All connectors are denoted Px. All connectors and headers are 2.54mm pitch unless otherwise stated
- All decoupling caps greater than 0.1uF are X7R unless otherwise stated
- All decoupling caps less than 0.1uF are COG unless otherwise stated
- Resistor networks are donated RNx. All resistor networks are SMD 1206 style package.
Notes:
MPC5510 208 PIN MCU (1of2) - I/O
MPC5510 208 PIN MCU (2of2) - Power
CLOCK AND PLL CIRCUITRY
EXPANSION CONNECTORS (DAUGHTERCARD)
Table Of Contents:
Date
03 Jan 07
09 Jan 07
29 Jan 07
12 Sept 07
Page B-32
Rev
0.1
0.2
0.3
B0
119
120
1
2
1
2
3.5"
Page Title:
Size
B
Drawn by :
M. Stewart
Approv ed:
M.Stewart
Date: Wednesday , September 12, 2007
Sheet
1
SCH-23132 PDF: SPF-23132
Front Page Contents and Notes
of
5
208BGA Daughter Card for MPC5510EVB
Document Number
Drawing Title:
Designer:
M. Stewart
MCD Applications East Kilbride
Colv illes Road, Kelv in Industrial Estate, East Kilbride G75 0TG
Transportation & Standard Products Group
ADAPTER BOARD LAYOUT INSTRUCTIONS
Dimensions in INCHES
CONNECTOR 2 (P2)
CONNECTOR 1 (P1)
0.2"
119
120
Comments
Provisional release
Provisional release (Post Layout)
Prototype Release - PCB RevA
Cosmetic changes optimised for A4 - PCB RevB
Connectors
fitted to
UNDERSIDE of
PCB but viewed
and numbered
from TOP side
in this diagram
Designer
M. Stewart
M. Stewart
M. Stewart
A. Robertson
Revision Information
MPC5510 208BGA MCU Daughter Card
Appendix G - 208BGA Daughtercard Schematics
MPC5516EVB User Manual Rev 1.0
Rev
B0
Sept 2007
PB[0..15]
PC[0..15]
PD[0..15]
MCU-EXTAL32
MCU-XTAL32
MCU-XTAL
MCU-EXTAL
TDO
TDI
TMS
TCLK
JCOMP
MCU-RSTx
5
5
5
4
4
4
4
5
5
5
5
5
5
MPC5516EVBUM/D
PA[0..15]
5
D15
D16
E14
E15
E16
F13
F14
F15
G13
F16
G14
G15
H14
H15
J14
K14
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD[0..15]
TP6
B11
C11
D11
A12
B12
C12
D12
A13
B13
C13
A14
B14
B16
C15
C16
D14
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC[0..15]
TEST
R2 0 OHM
GND
T14
R13
T15
R14
T13
P16
N16
R11
MCU-RSTx E4
TDO
TDI
TMS
TCLK
JCOMP
MCU-XTAL
MCU-EXTAL
A6
B6
C7
D7
A8
B8
C8
D8
A9
B9
C9
D9
A10
B10
A7
B7
C10
A11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB[0..15]
MCU-EXTAL32
MCU-XTAL32
E3
E2
E1
D3
D2
D1
C2
C1
A3
C4
D5
C5
B5
A5
D6
C6
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA[0..15]
MPC5516EVB User Manual Rev 1.0
MPC5516 208BGA
I/O Pins
MPC5516_SKT208
TEST
RESET
TDO
TDI
TMS
TCK
JCOMP
XTAL
EXTAL / EXTCLK
PK0 / XTAL32
PK1 / EXTAL32
PD0 /CNTX_A
PD1 / CNRX_A
PD2 / CNRX_B / eMIOS[10] / BOOTCFG
PD3 / CNTX_B / eMIOS[11]
PD4 / CNTX_C / eMIOS[12]
PD5 / CNRX_C / eMIOS[13]
PD6 / TXD_A / eMIOS[14]
PD7 / RXD_A / eMIOS[15]
PD8 / TXD_B/ SCL_A
PD9 / RXD_B / SDA_A
PD10 / PCS_B[2] / CNTX_F / Z1_NMI
PD11 / PCS_B[1] / CNRX_F / Z0_NMI
PD12 / PCS_B[0] / eMIOS[9]
PD13 / SCK_B / eMIOS[8]
PD14 / SOUT_B/ eMIOS[7]
PD15 / SIN_B / eMIOS[6]
PC0 / eMIOS[0] / FR_A_TX_EN
PC1 / eMIOS[1] / FR_A_TX
PC2 / eMIOS[2] / FR_A_RX
PC3 / eMIOS[3] / FR_DBG0
PC4 / eMIOS[4] / FR_DBG1
PC5 / eMIOS[5] / FR_DBG2
PC6 / eMIOS[6] / FR_DBG3
PC7 / eMIOS[7] / FR_B_RX
PC8 / eMIOS[8] / FR_B_TX
PC9 / eMIOS[9] / FR_B_TX_EN
PC10 / eMIOS[10] / PCS_C[5]
PC11 / eMIOS[11] / PCS_C[4]
PC12 / eMIOS[12] / PCS_C[3]
PC13 / eMIOS[13] / PCS_A[5]
PC14 / eMIOS[14] / PCS_A[4]
PC15 / eMIOS[15] / PCS_A[3]
PB0 / AN28 / eMIOS[16] / PCS_C[5]
PB1 /AN29 / eMIOS[17] / PCS_C[4]
PB2 / AN30 / eMIOS[18] / PCS_C[3]
PB3 / AN31 / PCS_C[2]
PB4 / AN32 / PCS_C[1]
PB5 / AN33 / PCS_C[0]
PB6 / AN34 / SCK_C
PB7 / AN35 / SOUT_C
PB8 / AN36 / SIN_C
PB9 / AN37 / CNTX_D / PCS_B[4]
PB10 / AN38 / CNRX_D / PCS_B[3]
PB11 / AN39 / eMIOS[19] / PCS_B[5]
PB12 / TXD_G / PCS_B[4]
PB13 / RXD_G / PCS_B[3]
PB14 / TXD_H
PB15 / RXD_H
PA0 / AN0
PA1 / AN1
PA2 / AN2
PA3 / AN3
PA4 / AN4
PA5 / AN5
PA6 / AN6
PA7 / AN7
PA8 / AN8
PA9 / AN9
PA10 / AN10
PA11 / AN11
PA12 / AN12
PA13 / AN13
PA14 / PA14 / EXTAL32
PA15 / AN15 / XTAL32
U1A
EVTI / RD_WR / PF0
EVTO / TA / PF1
MSEO / AD[8] / PF2
MCKO / AD[9] / PF3
MDO[0] / AD[10] / PF4
MDO[1] / AD[11] / PF5
MDO[2] / AD[12] / PF6
MDO[3] / AD[13] / PF7
MDO[4] / AD[14] / PF8
MDO[5] / AD[15] / PF9
MDO[6] / TXD_C / CS[1] / PF10
MDO[7] / RXD_C/ CS[0] / PF11
TXD_D / TS / PF12
RXD_D / OE / PF13
CNTX_D / BDIP / WE[0] / PF14
CNRX_D / TEA / WE[1] / PF15
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
eMIOS[5] / PCS_A[2] /
eMIOS[4] / PCS_A[1] /
eMIOS[3] / PCS_A[0] /
eMIOS[2] / SCK_A /
eMIOS[1] / SOUT_A /
eMIOS[0] / SIN_A /
CLKOUT /
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
/
/
/
/
/
/
/
/
N11
P11
N10
R10
P10
T9
P9
R8
K2
K1
J4
H3
H2
G4
G3
G1
L3
L2
L1
K4
K3
J3
J2
J1
H1
G2
F4
F3
F2
F1
T5
R5
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PJ[0..15]
PH[0..15]
PG[0..15]
P5
T4
R4
P4
T3
R3
T2
R1
P2
N3
N2
N1
M4
M3
M2
M1
PF[0..15]
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PE3
PE4
PE5
N12
P12
R12
T12
T10
R9
T8
P8
N8
T7
R7
P7
N7
R6
P6
N6
MCU-CLKOUT
PE[0..15]
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE0
PE1
PE2
K16
L14
L15
M13
N14
M15
P13
H13
H16
J13
J16
J15
K13
L13
L16
M14
Page B-33
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
SCL_A / eMIOS[20] / AN[27] / PH0
SDA_A / eMIOS[21] / AN[26] / PH1
eMIOS[22] / AN[25] / PH2
eMIOS[23] / AN[24] / PH3
MA[2] / TXD_E / AN[23] / PH4
MA[1] / RXD_E / AN[22] / PH5
TXD_F / AN[21] / PH6
RXD_F / AN[20] / PH7
MA[0] / CNTX_E / AN[19] / PH8
CNRX_E / AN[18] / PH9
CNRX_F / AN[17] / PH10
CNTX_F / AN[16] / PH11
PH12
PH13
WE[2] / PH14
WE[3] / PH15
eMIOS[16] / AD[16] / PG0
PCS_C[0] / eMIOS[17] / AD[17] / PG1
SCK_C / eMIOS[18] / AD[18] / PG2
SOUT_C / eMIOS[19] / AD[19] / PG3
SIN_C / eMIOS[20] / AD[20] / PG4
eMIOS[21] / AD[21] / PG5
eMIOS[22] / AD[22] / PG6
RXD_C / eMIOS[23] / AD[23] / PG7
PCS_A[4] / AD[24] / PG8
TXD_C / PCS_A[3] / AD[25] / PG9
PCS_A[2] / AD[26] / PG10
PCS_A[1] / AD[27] / PG11
PCS_A[0] / AD[28] / PG12
SCK_A / AD[29] / PG13
SOUT_A / AD[30] / PG14
SIN_A / AD[31] / PG15
NEXUS Port Controller
PJ[0..15]
PH[0..15]
PG[0..15]
PF[0..15]
Date:
Wednesday , September 12, 2007
Sheet
2
SCH-23132 PDF: SPF-23132
MCU Page 1/2 (I/O)
of
5
Rev
B0
MPC5510
208BGA MCU IO
208BGA Daughter Card for MPC5510EVB
5
5
5
5
Document Number
Page Title:
Drawing Title:
Size
B
4,5
MCU-CLKOUT 4
PE[0..15]
Sept 2007
VDDSY N
VDDA
5
5
VDDA
(5.0V)
+
VDDSY N
(3.3V)
MPC5516EVBUM/D
0.1UF
C26
VDD33
VDD33
(3.3V)
U1B
C25
10UF
A2
5
VDD15
2
1
(1.5V)
L4
AGND
L5
0.1UF
C15
AGND
L6
2
(From VDDSYN
Decoupling and
XTAL CCT Cps)
VSSSY N
0.01UF
C14
0.1UF
C13
L3
L1
BLM31AJ601SN1L
1
BLM31AJ601SN1L
VDD15
BLM31AJ601SN1L
BLM31AJ601SN1L
VDDA
VSSA
A4
1
2
B4
VRL
B1
REFBYPC
BLM31AJ601SN1L
2
1
ADC (5v)
BLM31AJ601SN1L
2
1
B3
VRH
R16
VDDSYN
GND
L7
PLL (3.3v)
VSSSYN
M16
1
2
VSSSY N
1000PF
C53
0.47UF
+
C7
R4
0 OHM
C8
470PF
C52
0.47UF
R6
0 OHM
C44
470PF
C10
0.47UF
+
C17
C20
1000PF 470PF
+
C2
0.47UF
+
T6
C30
0.1UF
C29
1000PF
GND
GND
GND Reference
Points
TP1
TP2
TP3
Page B-34
Route EXTAL / XTAL . XFC in isolated
plane (analogue signals between
VSSSYN and VDDSYN layer)
Keep MCU-CLKOUT AWAY from
analoguesignals (EXTAL, XTAL etc)
+
C21
1000PF
GND
C1
0.47UF
MPC5516 208BGA
POWER PINS
C40
C16
1000PF 470PF
+
+
+
+
C4
C3
0.47UF 0.47UF
C6
C5
0.47UF 0.47UF
C45
C43
1000PF 470PF
C9
0.47UF
Layout Notes (Important):
MPC5516_SKT208
GND
(VSS33a)
+
R3
0 OHM
1.5v Logic
N15
VFLASH / VDD33
3.3v I/O
A1
B2
A16
B15
T1
R2
T16
R15
A1-VDD
B2-VDD
A16-VDD
B15-VDD
T1-VDD
R2-VDD
T16-VDD
R15-VDD
5
1
MPC5516EVB User Manual Rev 1.0
1
C3
C14
D4
D13
VSS-C3
VSS-C14
VSS-D4
VSS-D13
VDDR
Regs(5v)
C49
470PF
I/O 3.3 OR 5v
L2
2
GND Links
AGND
GND
BLM31AJ601SN1L
1
GND
C48
0.1UF
GROUND PINS
VSS-G7
VSS-G8
VSS-G9
VSS-G10
G7
G8
G9
G10
1
P15
VSS-H7
VSS-H8
VSS-H9
VSS-H10
H7
H8
H9
H10
VSS-J7
VSS-J8
VSS-J9
VSS-J10
J7
J8
J9
J10
VSS-K7
VSS-K8
VSS-K9
VSS-K10
K7
K8
K9
K10
Flash
VPP
Supply (5v)
A15
D10
E13
G16
K15
A15-VDDE1
D10-VDDE1
E13-VDDE1
G16-VDDE1
K15-VDDE1
H4
L4
N5
P1
H4-VDDE2
L4-VDDE2
N5-VDDE2
P1-VDDE2
N9
T11
N9-VDDE3
T11-VDDE3
VSS-N4
VSS-N13
VSS-P3
VSS-P14
N4
N13
P3
P14
C37
470PF
C39
1000PF
C47
470PF
C51
0.1UF
C42
0.1UF
C46
0.1UF
C50
0.1UF
C22
1000PF
C12
470PF
C19
C11
0.1UF
C18
0.1UF
470PF
C32
C34
0.1UF
VDDE3
VDDE2
VDDE1
VPP
VDDR
5
5
5
5
5
Wednesday , September 12, 2007
Date:
Sheet
3
SCH-23132 PDF: SPF-23132
Document Number
MCU Page 2/2 (Power)
of
5
208BGA Daughter Card for MPC5510EVB
GND
VDDE3
GND
1000PF
C33
0.1UF
C35
(5V/3.3V)
470PF
0.1UF
1000PF
C23
C27
GND
0.1UF
C28
(5V/3.3V)
1000PF
C36
1000PF
C41
0.1UF
Size
B
Page Title:
Drawing Title:
GND
VDDE1
(5V/3.3V)
VDDE2
VPP
(5V)
C38
VDDR
(5V)
Rev
B0
MPC5510 208BGA MCU PWR
Sept 2007
FID6
FID5
FID7
FID3
FID8
FID4
MPC5516EVBUM/D
REMOVE XTAL jumper when driving EXTAL from
Oscilaltor Module or External Source (PLL Enabled)
Connect XTAL jumper to GND when driving EXTAL from
Oscilaltor Module or External Source (PLL Bypass
Mode)
Route EXTAL / XTAL in isolated
plane (analogue signals between
VSSSYN and VDDSYN layer)
Keep MCU-CLKOUT AWAY from
analoguesignals (EXTAL, XTAL etc)
Layout Notes (Important):
FID2
FID1
MPC5516EVB User Manual Rev 1.0
10PF
Y1
10PF
XTAL32
32.768KHz
EXTAL32
VSSSY N
Y2
33PF
33PF
R5 0 OHM
8MHz
XTAL
Page B-35
Loop Controlled Pierce
Oscillator Circuit
C55
C54
EXTAL
1
J5
GND
3
1
3
1
3
1
PK0
PK1
1
3
J3
J4
J1
J2
2
R7 33.0 OHM
PE[0..15]
2
2
2
2
MCU-XTAL
(MCU Crystal Output)
EVB-EXTAL
(FROM Expansion
Connectors)
MCU-EXTAL
(MCU Crystal Input)
MCU-XTAL32
(MCU 32KHz XTAL)
PK[0..1]
(TO Expansion
Connectors)
MCU-EXTAL32
(MCU 32KHz EXTAL)
MCU-CLKOUT
(FROM MCU)
PE6
(TO Expansion Connectors)
Place resistor as close as
possible to MCU CLKOUT pin
32Khz Oscillator Circuit
GND
C24
C31
2
1
2
1
2
2
2
5
5
2,5
Wednesday , September 12, 2007
Date:
Sheet
4
SCH-23132 PDF: SPF-23132
Document Number
Clock Circuitry
of
5
208BGA Daughter Card for MPC5510EVB
Size
B
Page Title:
Drawing Title:
MCU-XTAL
EVB-EXTAL
MCU-EXTAL
MCU-XTAL32
PK[0..1]
MCU-EXTAL32 2
MCU-CLKOUT 2
PE[0..15]
Rev
B0
CLOCK CIRCUITRY
Sept 2007
PB[0..15]
VDDA
VDD15
VDDE2
2
3
3
3
VDDE2
(Jumpered)
VDD15
(Jumpered)
VDDA
(Jumpered)
PG[0..15]
PF[0..15]
PH[0..15]
MCU-RSTx
2
2
2
2
MCU-RSTx
MCU-RSTx
B
PB12
PA13
K
GND
J
G
2
4
(NC)
6
VDDA
8
VDD15
10
PB3
12
PK1
14
VDD15
16
GND
18
PB0
20
PA11
22
PA9
24
PA7
26
PB1
28
GND
30
PA3
32
PA5
34
MCU-RSTx
36
PA0
38
PA2
40
GND
42
PH12
44
PJ13
46
PJ14
48
PJ15
50
VDDE2
52
GND
54
PH8
56
PH5
58
PH6
60
PH3
62
PJ8
64
GND
66
VDDE2
68
PH1
70
PH2
72
PG13
74
PG15
76
GND
78
PF15
80
VDDE2
82
PG9
84
PG11
86
PF11
88
GND
90
PG3
92
VDDE
2
94
PG8
96
PF10
98
PH15
100
102 (NC)
PG7
104
VDD15
106
PF6
108
PH14
110
VDDR
112
114 (NC)
PG6
116
VDD15
118
RST-OUTx
120
PB[0..15]
F
A
H
PF[0..15]
PJ[0..15]
VDD15
PB[0..15]
F
D
J
C
E
B
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
PF[0..15]
PJ[0..15]
PE[0..15]
Page B-36
GND
2
4
6 GND
8
10
12
14
16
18 GND
20
22
24
26
28
30 GND
32
34
36
38
40
42 GND
44
46
48
50
52
54 GND
56
58
60
62
64
66 GND
68
70
72
74
76
78 GND
80
82
84
86
88
90 GND
92
94
96
98
100
102 GND
104
106
108
110
112
114
116
118
120
Conenctor 2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
PB[0..15]
CON 2X60
1
3
5
VDDE1 7
VDD15
9
GND 11
PB7
13
PC0
15
PC8
17
VDD15
19
PC11
21
GND 23
PB14
25
PC5
27
PC13
29
PC14
31
VDDE1
33
GND 35
PC6
37
PD0
39
PD2
41
VDDE1
43
PD3
45
GND 47
PD6
49
PD9
51
PD10
53
VDDE1
55
PD11
57
PE7
59
PE8
61
PD14
63
PE10
65
PE12
67
VDDE1
69
GND 71
PE13
73
PE2
75
PE3
77
PE15
79
VDDE3
81
GND 83
PJ0
85
VDD33
87
PE4
89
EVB-EXTAL
91
PJ4
93
GND 95
VPP
97
PE6
99
PJ3
101
PF2
103
VDD15
105
(NC)
107
VDDSY N
109
PJ5
111
VDDE3
113
VDDE3
115
JCOMP
117
TMS
119
PB6
PB15
PC7
J7
PC[0..15]
PD[0..15]
CONNECTORS MUST BE PLACED IN ACCORDANCE WITH PCB SPECIFICATION
PH[0..15]
PJ[0..15]
PF[0..15]
J
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
Conenctor 1
PH[0..15]
G
GND
CON 2X60
PF[0..15]
F
PG1
PG4
VDD15
PF9
PJ7
PF13
PG2
PG5
VDD15
PG10
PF7
PF14
PG0
VDDE2
PG12
PG14
PF8
PF12
VDDE2
PH7
PH4
PJ9
VDDE2
PH0
PH9
VDDE2
PJ11
PJ12
PJ10
PA1
PH10
PH11
PH13
PA15
PA6
PB5
PA14
PA10
PA4
PB13
VDD15
PA12
PB4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
PG[0..15]
H
1
3
5
7
9
(NC) 11
13
15
17
19
21
GND 23
25
27
29
31
33
GND 35
(NC) 37
39
41
43
45
GND 47
49
51
53
55
57
GND 59
61
63
65
67
69
GND 71
73
75
77
79
81
GND 83
85
87
89
91
93
95
97
99
101
103
105
(NC)107
109
111
113
115
117
119
PG[0..15]
PJ[0..15]
RST-OUTx
TGT-RSTx
VDDR
(Jumpered)
MPC5516EVBUM/D
PJ[0..15]
TP5
TP4
VDDR
LED GREEN
PB2
PK0
PA8
VDDA
VDD15
J6
PB[0..15]
B
PB[0..15]
K
PK[0..1]
PK[0..1]
A
PA[0..15]
PA[0..15]
R1 560 OHM
2
3
GND
1
D1
2
PK[0..1]
4
Power LED
PA[0..15]
2
MPC5516EVB User Manual Rev 1.0
PF4
(NC)
PF3
TDO
VDD15
TDI
VDD15
TCLK
PF5
PJ6
PJ1
PF1
PE5
VDDE3
PJ2
PF0
PD15
VDDE1
PE0
PE1
PE14
VDDE1
PD12
PD13
PE9
PE11
VDDE1
PD4
PD5
PD7
PD8
PB9
VDDE1
PC2
PC15
PD1
VDD15
PC12
PB8
PC1
PC9
VDD15
PC10
PB11
PC4
B
PB10
PC3
E
C
J
D
F
Sheet
5
SCH-23132 PDF: SPF-23132
Wednesday , September 12, 2007
Date:
Daughter Card Connectors
Document Number
of
5
Rev
B0
DAUGHTERCARD
CONNECTORS
Size
B
Page Title:
2,4
2
2
4
3
2
2
3
2
3
3
3
2
2
208BGA Daughter Card for MPC5510EVB
PE[0..15]
TMS
JCOMP
EVB-EXTAL
VDDE3
TDO
TCLK
VDDSY N
TDI
VPP
VDD33
VDDE1
PC[0..15]
PD[0..15]
Drawing Title:
PE[0..15]
VDDE3
(Jumpered)
TMS
JCOMP
EVB-EXTAL
TDO
TCLK
VDDSY N
(Jumpered)
TDI
VPP
(Jumpered)
VDD33
(Jumpered)
VDDE1
(Jumpered)
PC[0..15]
Sept 2007
Refdes
C1,C2,C3,C4,C5,C6,C7,C8,C9,C10
C11,C13,C15,C18,C26,C27,C28,C30,C34,C35,C36,
C38,C42,C46,C48,C50
C12,C16,C20,C23,C33,C37,C43,C44,C47,C49,C52
C14
C17,C19,C21,C22,C29,C32,C39,C40,C41,C45,C51,
C53
C24,C31
C25
C54,C55
D1
FID1,FID2,FID3,FID4,FID5,FID6,FID7,FID8
J1,J2,J3,J4
J5
J6,J7
L1,L2,L3,L4,L5,L6,L7
R1
R2,R3,R4,R5,R6
R7
TP1,TP2,TP3
TP4,TP5,TP6
U1
Y1
Y2
MPC5516EVBUM/D
12
2
1
2
1
8
4
1
2
7
1
5
1
3
3
1
1
1
16
11
1
Qty
10
1000PF
10PF
10UF
33PF
LED GREEN
FID-040
HDR 3X1
HDR 1X2
CON 2X60
BLM31AJ601SN1L
560 OHM
0 OHM
33.0 OHM
TEST POINT
TEST POINT
MPC5516_SKT208
32.768KHz
8MHz
0.1UF
470PF
0.01UF
Value
0.47UF
Appendix H - 208BGA Daughtercard Bill Of Materials
MPC5516EVB User Manual Rev 1.0
Page B-37
VENKEL COMPANY
KEMET
VISHAY INTERTECHNOLOGY
VENKEL COMPANY
KINGBRIGHT
GENERIC
SAMTEC
SAMTEC
TYCO ELECTRONICS
MURATA
KOA SPEER
THYE MING TECH CO LTD
KOA SPEER
NICOMATIC
NA
Subassembly
VISHAY INTERTECHNOLOGY
C-MAC MICROTECHNOLOGY
MURATA
PANASONIC
VENKEL COMPANY
Manufacturer
AVX
C0805COG500-102JNE
C0603C100F5GAC
293D106X9010A2TE3
C0603C0G500-330JNE
K/APT-3216SGD
FID-040
TMM-103-02-G-S
TMM-102-02-G-S
5-5179009-5
BLM31AJ601SN1L
RK73H1JTTD5600F
CR-03JL7-0R
RK73H1JTTD33R0F
C12000B
NA
344-00364, 210-77299
XT26TTA32K768
LF A140K
GRM188R71H104KA93D
ECJ1VC1H471J
C0603X7R500-103KNE
Part Number
TAJA474M025R
Sept 2007