Download USER`S MANUAL

SERIES IP480 INDUSTRIAL I/O PACK
SIX 16-BIT COUNTER/TIMER MODULE
___________________________________________________________________________________________
Because this device does not normally implement debounce on
any of the counter/timer inputs (Trigger, Input, and Clock) and these
inputs have a wide bandwidth, it is very important that input signals
are kept clean and noise free to prevent potential errors. Well
defined TTL or CMOS signal levels are preferred. When driving
inputs, use of 50Ω generator outputs or a 50Ω series-coupled
resistor will improve results. If noisy field input signals and erratic
operation continues to occur, some consideration should be given to
external filtering or wave shaping of the input signals to prevent
these types of errors.
Refer to Table 3.1 and note that the base address for the IP module
I/O space (see your carrier board instructions) must be added to the
addresses shown to properly access the I/O space. Accesses are
generally performed on a 16-bit basis (D0..D15), but 8-bit D08 (EO)
accesses are possible in most cases.
3
Table 3.1: IP480 R/W Space Address (Hex) Memory Map
ODD
EVEN
Base
Base
MSB
LSB
Addr+
D15
D08 D07
D00 Addr+
00
Counter 1 Control Register (R/W)
(Not Used For 32-bit Counter)
01
02
Counter 2 Control Register (R/W)
(or 32-bit Counter 1 Control Register)
03
04
Counter 3 Control Register (R/W)
(Not Used For 32-bit Counter)
05
06
Counter 4 Control Register (R/W)
(or 32-bit Counter 2 Control Register)
07
08
Counter 5 Control Register (R/W)
(Not Used For 32-bit Counter)
09
0A
Counter 6 Control Register (R/W)
(or 32-bit Counter 3 Control Register)
0B
0C
Counter 1 Read Back Register (Read Only)
(or 32-bit Counter 1 Value MSW)
0D
0E
Counter 2 Read Back Register (Read Only)
(or 32-bit Counter 1 Value LSW)
0F
10
Counter 3 Read Back Register (Read Only)
(or 32-bit Counter 2 Value MSW)
11
12
Counter 4 Read Back Register (Read Only)
(or 32-bit Counter 2 Value LSW)
13
14
Counter 5 Read Back Register (Read Only)
(or 32-bit Counter 3 Value MSW)
15
16
Counter 6 Read Back Register (Read Only)
(or 32-bit Counter 3 Value LSW)
17
4
18
Counter 1 Constant Register (Write Only)
(or 32-bit Counter Constant 1 MSW)
19
4
1A
Counter 2 Constant Register (Write Only)
(or 32-bit Counter Constant 1 LSW)
1B
4
1C
Counter 3 Constant Register (Write Only)
(or 32-bit Counter Constant 2 MSW)
1D
4
1E
Counter 4 Constant Register (Write Only)
(or 32-bit Counter Constant 2 LSW)
1F
4
20
Counter 5 Constant Register (Write Only)
(or 32-bit Counter Constant 3 MSW)
21
4
22
Counter 6 Constant Register (Write Only)
(or 32-bit Counter Constant 3 LSW)
23
1
24
Not Used
Trigger Control
(Bits 15..06)
Register,
Bits 05..00 (Write)
25
1
26
Not Used
Software Reset
(Bits 15..01)
Register, Bit 00
(Write Only)
27
28
(32-bit Counter
1
Not Used
/Timers Only)
Readback Latch
(Bits 15..01)
Control Register
Bit 00 (Read/Write)
29
2A
Interrupt Pending/
1
Clear Register,
Not Used
Bits 13..08 (R/W)
(Bits 07..00)
2B
1
2C
Not Used
Interrupt Vector
(Bits 15..08)
Bits 07..00 (R/W)
2D
2E
2F
2
↓
↓
NOT USED
7E
7F
IP Logic Interface Connector (P1)
P1 of the IP module provides the logic interface to the mating
connector on the carrier board and its pin assignments are standard
for all IP modules according to the Industrial I/O Pack Specification
(see Table 2.2). This connector is a 50-pin female receptacle
header (AMP 173279-3 or equivalent) which mates to the male
connector of the carrier board (AMP 173280-3 or equivalent). This
provides excellent connection integrity and utilizes gold-plating in the
mating area. Threaded metric M2 screws and spacers are supplied
with the IP module to provide additional stability (see Drawing
4501-434 for assembly details). Field and logic side connectors are
keyed to avoid incorrect assembly.
Table 2.2: Standard Logic Interface Connections (P1)
Pin Description
Number
Pin Description
Number
GND
1
GND
26
CLK
2
+5V
27
Reset*
3
R/W*
28
D00
4
IDSEL*
29
D01
5
DMAReq0*
30
D02
6
MEMSEL*
31
D03
7
DMAReq1*
32
D04
8
IntSel*
33
D05
9
DMAck0*
34
D06
10
IOSEL*
35
D07
11
RESERVED
36
D08
12
A1
37
D09
13
DMAEnd*
38
D10
14
A2
39
D11
15
ERROR*
40
D12
16
A3
41
D13
17
INTReq0*
42
D14
18
A4
43
D15
19
INTReq1*
44
BS0*
20
A5
45
BS1*
21
STROBE*
46
-12V
22
A6
47
+12V
23
ACK*
48
+5V
24
RESERVED
49
GND
25
GND
50
An Asterisk (*) is used to indicate an active-low signal.
BOLD ITALIC Logic Lines are NOT USED by this IP Model.
3.0 PROGRAMMING INFORMATION
ADDRESS MAPS
This board is addressable in the Industrial Pack I/O space to
monitor and control the status and configuration of up to six 16-bit
counter/timers, or three 32-bit counter/timers. The I/O space may
be as large as 64, 16-bit words (128 bytes) using address lines
A1..A6, but the IP480 uses only a portion of this space.
-7-