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P89LPC9331/9341/9351 User manual
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NXP Semiconductors
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crystal oscillator or the watchdog oscillator selected by the WDCLK bit in the WDCON
register and XTALWD bit in the CLKCON register. (Note that switching of the clock
sources will not take effect immediately - see Section 16.3).
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The watchdog asserts the watchdog reset when the watchdog count underflows and the
watchdog reset is enabled. When the watchdog reset is enabled, writing to WDL or
WDCON must be followed by a feed sequence for the new values to take effect.
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Table 120. Watchdog timer configuration
WDTE WDSE FUNCTION
0
x
The watchdog reset is disabled. The timer can be used as an internal timer and
can be used to generate an interrupt. WDSE has no effect.
1
0
The watchdog reset is enabled. The user can set WDCLK to choose the clock
source.
1
1
The watchdog reset is enabled, along with additional safety features:
1. WDCLK is forced to 1 (using watchdog oscillator)
2. WDCON and WDL register can only be written once
3. WDRUN is forced to 1
PCLK
0
Watchdog
oscillator
1
0
÷32
1
crystal
oscillator
÷2
÷32
÷64
÷2
÷128
÷2
÷256
÷2
÷512
÷2
÷1024
÷2
÷2048
÷2
÷4096
Watchdog clock
after a Watchdog
feed sequence
TO WATCHDOG
DOWN COUNTER
(after one prescaler
count delay)
XTALWD
PRE2
PRE1
DECODE
PRE0
000
001
010
011
100
101
110
111
002aae092
Fig 53. Watchdog Prescaler
16.2 Feed sequence
The watchdog timer control register and the 8-bit down counter (See Figure 54) are not
directly loaded by the user. The user writes to the WDCON and the WDL SFRs. At the end
of a feed sequence, the values in the WDCON and WDL SFRs are loaded to the control
register and the 8-bit down counter. Before the feed sequence, any new values written to
these two SFRs will not take effect. To avoid a watchdog reset, the watchdog timer needs
to be fed (via a special sequence of software action called the feed sequence) prior to
reaching an underflow.
<Document ID>
User manual
© NXP B.V. 2009. All rights reserved.
Rev. 01.xx — 5 February 2009
125 of 172
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If a watchdog reset occurs, its behavior is similar to power on reset. Both POF and BOF
are cleared.