Download UTD - EE2110 Lab #3

EE 2310: Experiment #3
Digital Logic Chip Pin-Out Diagrams
00
1
2
04
3
4
5
6
9
10
8
12
13
11
73
107
J
12
CLK
4
K
13
CLR/
Q
10
9
8
5
6
3
4
1
2
Q
Q/
7
10 P
T
3
2
2
Q/
8
J
9
CLK
11
K
10
CLR/
12
11
2
3
D
4 CLK
1 PR/
CLR/
12
11
10
13
6
D
5
C
4
B
3
5
A
9
6
1
SN 74LS107
Dual JK FF
RCO
15
11
QD 12
QC 13
QB 14
QA
LOAD
CLR
SN 74LS163
Counter
Q/
Ground
(0V.)
1
2
3
4
5
6
Ground
(0 V) 7
8
10
9
8
74LS00, 04, 74, 107
SH/LD'
7
6
5
4
QD
QD
QC
QB
QA
D
C
B
A
16
15
14
13
12
11
10
9
SN 74LS195, 163
4
8
10
CLK
2
J
3
195
K
1
CLR
9
Notch
Power
(+5V.)
9
Q
SN 74LS195
Quad Latch
Notch
14
13
12
11
6
Q/
Power Pin-Outs
1
2
3
4
5
6
7
5
Q
SN 74LS74
Dual D FF
163
CLK
74
D
CLK
PR/
CLR/
SN 74LS04
Hex Inverter
SN 74LS00
Quad 2-input
NAND gate
1
13
Power
(+5V)
11
12
13
14
15