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Chapter 2: Platform Specification Utility (PsfUtility) Master PLBV4.6 Ports Master PLBV4.6 ports must use the naming conventions shown inTable 2-13. Table 2-13: Master PLBV4.6 Port Naming Conventions <M> Prefix for the master output. <PLB_M> Prefix for the master input. <BI> A bus identifier. Optional for peripherals with a single master PLBV46 port and required for peripherals with multiple master PLBV46 ports. For peripherals with multiple master PLBV46 ports, the <BI> strings must be unique for each bus interface. Trailing underline character '_' in the <BI> string are ignored. PLB v4.6 Master Outputs For interconnection to the PLB v4.6, masters must provide the following outputs: <BI>M_abort <BI>M_ABus <BI>M_UABus <BI>M_BE <BI>M_busLock <BI>M_lockErr <BI>M_MSize <BI>M_priority <BI>M_rdBurst <BI>M_request <BI>M_RNW <BI>M_size <BI>M_TAttribute <BI>M_type <BI>M_wrBurst <BI>M_wrDBus : : : : : : : : : : : : : : : : out out out out out out out out out out out out out out out out std_logic; std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic; std_logic; std_logic; std_logic_vector(0 std_logic; std_logic; std_logic; std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic; std_logic_vector(0 to C_<BI|MPLB>_AWIDTH-1); to C_<BI|MPLB>_AWIDTH-1); to C_<BI|MPLB>_DWIDTH/8-1); to 1); to 3); to 15); to 2); to C_<BI|MPLB>_DWIDTH-1); Examples: IPLBM_request : out std_logic; Bridge_M_request : out std_logic; O2Ob_M_request : out std_logic; PLB v4.6 Master Inputs For interconnection to the PLBV4.6, masters must provide the following inputs: <BI>MPLB_Clk <BI>MPLB_Rst <BI>PLB_MBusy <BI>PLB_MRdErr <BI>PLB_MWrErr <BI>PLB_MIRQ <BI>PLB_MWrBTerm <BI>PLB_MWrDAck <BI>PLB_MAddrAck <BI>PLB_MRdBTerm <BI>PLB_MRdDAck 36 : : : : : : : : : : : in in in in in in in in in in in std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; www.xilinx.com Embedded System Tools Reference Manual UG111 July 6, 2011