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Section Five
Programming Considerations
6. When the Valid auxiliary command is issued, the TLC assumes that the My Secondary Address
(MSA) message has been received, which causes:
•
The LA bit to be set and the TA bit to be cleared (LADS=TIDS=1) if LPAS was set, or the
TA bit to be set and the LA bit to be cleared (TADS=LIDS=1) if TPAS was set.
•
The GPIB DAC message to be sent true, and the GPIB handshake to be finished.
7. When the Non-Valid auxiliary command is issued, the TLC assumes that the Other Secondary
Address (OSA) message has been received, which causes:
•
The TLC Talker or Listener function to go to its idle state (TIDS=1 or LIDS=1) if the either
the TPAS or LPAS bit was set.
•
The GPIB DAC message to be sent true, and the handshake to be finished.
Until a GPIB Primary Command Group (PCG) message is received (that is, as long as the
subsequent messages are secondary addresses), the APT bit is set and a DAC holdoff is in effect
each time a GPIB secondary address is received. In this way, the GPIB CIC can address several
devices having the same primary address without repeating the primary address each time. If a PCG
message is received before a secondary address is received, the TPAS and LPAS bits are cleared.
Sending/Receiving Messages
When the GPIB port is a GPIB Talker or Listener, data (device-dependent messages) can be sent or
received.
To send data, wait until the port has been programmed or addressed to talk and the CDOR is empty.
When this occurs, the DO bit in the ISR1 is set, indicating that it is safe to write a byte to the CDOR.
The DO bit is set again once the byte has been received by all GPIB Listeners.
To receive data, wait until the port has been programmed or addressed to listen and the DIR is full.
When this occurs, the DI bit in the ISR1 is set indicating that the GPIB Talker has written a byte to
the DIR. Once that byte has been read, the DI bit will be set again when a new byte is received from
the GPIB Talker.
Determining when the CDOR is empty or the DIR is full can be done by polling the ISR1 until the
DO or DI status first appears or by allowing a program interrupt to occur on the respective event.
Remember, however, that the status bits and interrupt signals are cleared when the ISR1 is read, so
the absence of a true DO or DI status does not indicate that the CDOR is still full or that the DIR is
still empty.
© National Instruments Corporation
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GPIB-1014DP User Manual