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7.3. I/O Specication File
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7.2.6 Examples of using assign
tries to generate a consistent pad assignment that matches all pads of the
same name between the two LCA les. Assign produces up to ve output les, (four
.cst constraint les { one per chip) and a summary le, Rx.info (on DOS machines
Rx.inf). The constraint les are then used by apr (for XC3000 series FPGAs) or
ppr (for XC4000 series FPGAs) to force the pin assignments of the appropriate nets.
First, let us assume that the user already has generated the XNF les for his/her
design. In order to complete the design, the user must create unconstrained LCA les,
run assign and then create constrained LCA les.
Assign
7.2.7 Xilinx XC3000 Series Design
The Makefile in Fig. 7.3 shows the process of generating a XC3000 series design
and Fig. 7.2 shows an example of a constraint le. The constraint le consists of two
parts. The rst part locks all the IOBs, and the second part locks the CLBs, if the
-c option was used. In the rare event that apr can't complete the routing process,
unlocking the CLBs by commenting out the last line
Include x1clb.cst;
of the constraint le should help. Note that you must also create the routing chips
and place and route them before the nal design can be downloaded.
7.2.8 XC4000 Series Design
The design ow for XC4000 parts is very much like that of XC3000-series parts,
except you use ppr instead of apr; except that the current version (April 1994) of ppr
has no incremental placement and routing option. We shall update assign as soon
as the incremental place and route option is available with ppr.
The constraint les generated thus conform to the syntax expected by ppr, and also
have the same pre-extension name as the XNF le to be placed and routed. Figure 7.5
shows a Makefile for running assign. In Fig. 7.4, we have shown the constraint le
generated for a routing chip. Notice that there are X1 and X2 prexes to the normal
net names, indicating which user chip the nets come from. The same prexes are used
in XC3000-series routing chip constraint les.
7.3 I/O Specication File
There are two special les used by assign. These are xc3020.io and xc3042.io.
These les contain information about the physical pin locations on the chip (which is
84 pin PLCC package) and the usable pins. You should not change these les. The
commands contained in the les include:
; a semicolon in the first column of a line denotes a comment MAP
<pin# start: pin# end> -> ( start_x:start_y, end_x:end_y) IO
<startpin:endpin> <startpin:endpin> .... CIO <startpin:endpin>
<startpin:endpin> ...