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The Numbered Series
Lab 5
ple in section 9.2.6.1. The lines for internal net names and properties are still required in
the format of 9.2.6.1.
7) When you have entered your Verilog code, click on the name of your module in the Hierarchy pane and then in the Processes pane expand “Implement Design” and double click on
“Synthesize XST”. This will start the compilation. Correct any errors that the compilation
finds by appropriate editing and rerunning the synthesis.
8) When you have successfully run the synthesis, double click on the “Implement Design” entry itself. This will complete the process of mapping the design to the CPLD.
9) Implementation should include running Generate Program File. This step produces a
JEDEC industry standard file (with file extension “.jed”) describing how the device will be
programmed. At this point, the next step is to use the downloading cable in the lab to put
your program into a CPLD board. See section 10., particularly for download instructions
and Table 10.1 for connectivity information.
ENGN1630 Lab Manual Fall 2015
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