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MCX314As – M23
NOVA electronics Inc.
2.4.3 The Bit Pattern Interpolation
Y
This interpolation driving receives interpolation data that is
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created by upper-level CPU and transformed to bit patterns in a
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block of a predetermined size, and outputs interpolation pulses
consecutively at the specified drive speed.
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Every axis has 2 bit-data buffers for host CPU: one for + direction
and the other for - direction. When performing the bit pattern
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interpolation, the host CPU will write the designated interpolation
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data, for 2 or 3 axes, into MCX314As.
If a bit in the bit pattern data from CPU is “1” , MCX314As will
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output a pulse at the time unit; if it is “0”, MCX314As will not
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X
output any pulse at the time unit.
For example, if the user want to generate the X-Y profile (see Fig.
Fig. 2.32 Example for Bit Pattern Interpolation
2.32), the host CPU must write a set of pattern into those specific
registers ---- XPP: the + direction register for X axis, XPM: the − direction register for X axis, YPP and YPM: the + and −
directions registers. With in the time unit, MCX314As will check the registers once and decide to output a pulse or not
depending on the bit pattern.
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01000000 00000000 00011111 11011011 11110110 11111110 00000000 00000000 :XPP(X+direction)
01111111 11110101 00000000 00000000 00000000 00000000 00101011 11111111 :XPM(X-direction)
00000000 00000000 00000000 11111111 00000000 00001111 11111111 11010100 :YPP(Y+direction)
00001010 11111111 11111100 00000000 00111111 11000000 00000000 00000000 :YPM(Y-direction)
Fig. 2.33 shows the register configuration of the 1st axis and movements of bit data of bit pattern interpolation in this IC.
BP1P register and BP1M register are 16 bit-data buffers for bit pattern data form the host CPU. (IF the system uses 8-bit data bus,
the host CPU has to write the data by low byte and high byte.) The + direction data should be written into PB1P, and the −
direction data into PB1M. Once starting the bit pattern interpolation, the pulse outputting is in the order from D0.
SC=2
BP1P
Host CPU
REG2
0000100000000100
1 REG1
0001001000010000
0100000000100001
D0
0 D15
1001101001110101
1110101
ax1 -PP
SREG
The data will be written
by stacking command.
SC=2 REG2
0100000100001010
BP1M
Host CPU
0000011100001010
1 REG1
1000010000100000
D0
0 D15
0000000000001010
SREG
SC
0001010
ax1 -PM
SC: Stacking counter (RR0/D14,13)
BP1P: Data register (ax1 + direction)
BP1M: Data register (ax1 + direction)
SREG: 16 bit shift register
REG1: 16 bit buffer register 1
REG2: 16 bit buffer register 2
0- 3
Fig. 2.33 Register Configuration and Movements of Bit Patterns of Bit Pattern Interpolation (for ax1)
Stacking counter (SC) is a 2-bit counter. Its value is between 0 and 3, which can be read from D14,13 of register RR0. SC will
decide which register for the data from the host CPU. The initial value of SC is 0. So, when host CPU writes bit pattern data into
BP1P or BP1M, the data will be stored in SREG, and then, SC will count up to 1, and the next data from the host CPU will be
written into REG1. By this way, the REG2 becomes the register when SC=2. The host CPU is not able to write any bit pattern
data into MCX314As when SC=3.
When the bit pattern interpolation pulse is outputting, D0 in SREG will be shifted output first, and then in the order of D1, D…
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