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56F803
Evaluation Module User Manual
56F800
16-bit Digital Signal Controllers
DSP56F803EVMUM
Rev. 5
07/2005
freescale.com
TABLE OF CONTENTS
Preface vii
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Notation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
Chapter 1
Introduction
1.1
1.2
1.3
56F803EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
56F803EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
56F803EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Technical Summary
2.1
56F803. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3
RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4
Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6
Debug LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.7
Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.7.1
JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.7.2
Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8
External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.9
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.11 UNI-3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.12 Run/Stop Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.13 Motor Control PWM Signals and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.14 Motor Protection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.14.1
UNI-3 Motor Protection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.15 Back-EMF and Motor Phase Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Table of Contents, Rev. 5
Freescale Semiconductor
i
2.16 Quadrature Encoder/Hall-Effect Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.17 Zero-Crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.18 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19 Peripheral Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19.1
External Memory Control Signal Expansion Connector . . . . . . . . . . . . . . . . . . . . .
2.19.2
Encoder/Timer Channel Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19.3
Timer Channel Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19.4
Address Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19.5
Data Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19.6
A/D Port Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19.7
Serial Communications Port Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . .
2.19.8
Serial Peripheral Interface Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19.9
CAN Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19.10 PWM Port Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.20 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-17
2-17
2-18
2-19
2-20
2-20
2-21
2-21
2-22
2-23
2-23
2-24
2-24
2-25
2-25
Appendix A
56F803EVM Schematics
Appendix B
56F803EVM Bill of Material
DSP56F803EVM User Manual, Rev. 5
ii
Freescale Semiconductor
LIST OF FIGURES
1-1
Block Diagram of the 56F803EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2
56F803EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3
Connecting the 56F803EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1
Schematic Diagram of the External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . 2-4
2-2
Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-3
Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-4
Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-5
Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-6
Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-7
Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-8
Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-9
Run/Stop Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-10
PWM Group Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-11
DC Bus Over-Voltage and Over-Current Detection Schematic Diagram . . . . . . . . 2-15
2-12
Primary Back-EMF or Motor Phase Current Sense Signals . . . . . . . . . . . . . . . . . . 2-16
2-13
Zero-Crossing Encoder Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-14
CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
A-1
56F803 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A-2
Reset, Mode, Clock & IRQsL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A-3
Program & Data SRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
A-4
RS-232 and SCI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A-5
56F803 PWM LEDs and User LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A-6
UNI-3 Over-Voltage and Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
A-7
Zero-Crossing/ Encoder or Hall-Effect Selection . . . . . . . . . . . . . . . . . . . . . . . . A-8
A-8
High Speed CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
A-9
Port Timer D, Address, Data, A/D and Control Line Connectors . . . . . . . . . . . A-10
A-10
UNI-3 Interface and General Purpose Switches . . . . . . . . . . . . . . . . . . . . . . . . A-11
List of Figures, Rev. 5
Freescale Semiconductor
iii
A-11
Back-EMF and Phase Current Sense Analog Input Selectors . . . . . . . . . . . . . . A-12
A-12
Parallel JTAG Host/Target Interface and JTAG Connector . . . . . . . . . . . . . . . A-13
A-13
Power Supplies 3.3V and 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14
A-14
Bypass Capacitors and Spare Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
DSP56F803EVM User Manual, Rev. 5
iv
Freescale Semiconductor
LIST OF TABLES
1-1
56F803EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1
RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-2
Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-3
JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-4
Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5
Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-6
On-Board Host Target Interface Power Source Jumper Selection . . . . . . . . . . 2-10
2-7
UNI-3 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-8
CAN Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2-9
External Memory Control Signal Connector Description . . . . . . . . . . . . . . . . . 2-20
2-10
Timer Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2-11
Timer D Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2-12
External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-21
2-13
External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-22
2-14
A/D Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2-15
SCI Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2-16
SPI Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2-17
CAN Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2-18
PWM Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
List of Tables, Rev. 5
Freescale Semiconductor
v
DSP56F803EVM User Manual, Rev. 5
vi
Freescale Semiconductor
Preface
This reference manual describes in detail the hardware on the 56F803 Evaluation Module.
Audience
This document is intended for application developers who are creating software for
devices using the Freescale 56F803 part.
Organization
This manual is organized into two chapters and two appendixes.
•
Chapter 1, Introduction - provides an overview of the 56F803EVM and its
features.
•
Chapter 2, Technical Summary - describes in detail the 56F803EVM hardware.
•
Appendix A, 56F803EVM Schematics - contains the schematics of the
56F803EVM.
•
Appendix B, 56F803EVM Bill of Material - provides a list of the materials used
on the 56F803EVM board.
Suggested Reading
More documentation on the 56F803 and the 56F803EVM kit may be found at the URL:
http://www.freescale.com
Preface, Rev. 5
Freescale Semiconductor
vii
Notation Conventions
This document uses the following conventions:
Term or Value
Symbol
Examples
Active High Signals
(Logic One)
No special symbol
attached to the signal name
A0
CLKO
Active Low Signals
(Logic Zero)
Noted with an
overbar in text and in
most figures
WE
OE
Hexadecimal Values
Begin with a “$”
symbol
$0FF0
$80
Decimal Values
No special symbol
attached to the
number
10
34
Binary Values
Begin with the letter
“b” attached to the
number
b1010
b0011
Numbers
Considered positive
unless specifically
noted as a negative
value
5
-10
Bold
Reference sources,
paths, emphasis
...see:
Exceptions
In schematic drawings,
Active Low Signals may
be noted by a backslash:
/WE
Voltage is often shown
as positive: +3.3V
www.freescale.com...
DSP56F801EVM User Manual, Rev. 5
viii
Freescale Semiconductor
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined below for
reference.
A/D
Analog-to-Digital
CAN
Controller Area Network; serial communications peripheral and method
CiA
CAN in Automation, an international CAN user’s group that coordinates
standards for CAN communications protocols
EVM
Evaluation Module
GPIO
General Purpose Input and Output Port
IC
Integrated Circuit
JTAG
Joint Test Action Group, a bus protocol/interface used for test and debug
LQFP
Low-profile Quad Flat Pack
MPIO
Multi Purpose Input and Output Port; shares package pins with other
peripherals on the chip and can function as a GPIO
OnCETM
On-Chip Emulation, a debug bus and port created by Freescale to enable
designers to create a low-cost hardware interface for a professional
quality debug environment
PCB
Printed Circuit Board
PLL
Phase Locked Loop
PWM
Pulse Width Modulation
RAM
Random Access Memory
ROM
Read Only Memory
SCI
Serial Communications Interface
SPI
Serial Peripheral Interface Port
SRAM
Static Random Access Memory
Universal Asynchronous Receiver/Transmitter
UART
Preface, Rev. 5
Freescale Semiconductor
ix
References
The following sources were referenced to produce this manual:
[1] DSP56800 Family Manual, Freescale Semiconductor, DSP56800FM
[2] DSP56F801/803/805/807 User’s Manual, Freescale Semiconductor,
DSP56F801-7UM
[3] 56F803 Technical Data, Freescale Semiconductor, DSP56F803
[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,
Version 1.0, CAN in Automation
[5] CAN Specification 2.0B, BOSCH or CAN in Automation
DSP56F801EVM User Manual, Rev. 5
x
Freescale Semiconductor
Chapter 1
Introduction
The 56F803EVM is used to demonstrate the abilities of the 56F803 and to provide a hardware
tool allowing the development of applications that use the 56F803.
The 56F803EVM is an evaluation module board that includes a 56F803 part, peripheral
expansion connectors, external memory, RS-232 interface and a CAN interface. The expansion
connectors are for signal monitoring and user feature expandability.
The 56F803EVM is designed for the following purposes:
•
Allowing new users to become familiar with the features of the 56800 architecture. The
tools and examples provided with the 56F803EVM facilitate evaluation of the feature set
and the benefits of the family.
•
Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run
it, and debug it using a debugger via the JTAG/OnCETM port. The breakpoint features of
the OnCE port enable the user to easily specify complex break conditions and to execute
user-developed software at full-speed, until the break conditions are satisfied. The ability
to examine and modify all user accessible registers, memory and peripherals through the
OnCE port greatly facilitates the task of the developer.
•
Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the controller’s peripherals.
The OnCE port's unobtrusive design means that all of the memory on the board and on the
chip are available to the user.
Introduction, Rev. 5
Freescale Semiconductor
1-1
1.1 56F803EVM Architecture
The 56F803EVM facilitates the evaluation of various features present in the 56F803 part. The
56F803EVM can be used to develop real-time software and hardware products based on the
56F803. The 56F803EVM provides the features necessary for a user to write and debug
software, demonstrate the functionality of that software and interface with the customer's
application-specific device(s). The 56F803EVM is flexible enough to allow a user to fully
exploit the 56F803's features to optimize the performance of their product, as shown in
Figure 1-1.
56F803
RESET
LOGIC
MODE / IRQ
LOGIC
XTAL/EXTAL
Low Freq
Crystal
SCI
RS-232
Interface
RESET
MODE / IRQ
DSub
9-Pin
CAN Interface
Program
Memory
64Kx16-bit
Address,
Data &
Control
SPI
CAN
Data Memory
64Kx16-bit
Peripheral
Expansion
Connector(s)
TIMER
PWM LEDs
Over V Sense
GPIO
Over I Sense
Memory
Expansion
Connector(s)
JTAG
Connector
Debug LEDs
Zero Crossing
Detect
JTAG / OnCE
PWM
UNI-3
A/D
DSub
25-Pin
Parallel
JTAG Interface
3.3 V & GND
Power Supply
3.3V, 5V &
3.3VA
Figure 1-1. Block Diagram of the 56F803EVM
DSP56F803EVM User Manual, Rev. 5
1-2
Freescale Semiconductor 56F803EVM Configuration Jumpers
1.2 56F803EVM Configuration Jumpers
Ten jumper groups, (JG1-JG10), shown in Figure 1-2, are used to configure various
features on the 56F803EVM board. Table 1-1 describes the default jumper group settings.
9 87
1
JG10
123
JG6
3 2 1
789
JG7
7 8 9
3
JG9
JG3
J3
J9
J2
J4
J8
JG7
3 2 1
1 2 3
JG1
1
JG6
2
JG10
P1
JG1
7 8 9
DSP56F803EVM
J10
1
Y1
1
JG3
JG9
1
1
U1
PWM LEDs
7
8
U15
USER LED
JG4
JTAG
S/N
JG5
JG4
S1
JG2 JG8
RUN/STOP
S2
LED3
JG5
P4 IRQA
S3
S4
IRQB
RESET
U6
J1
U7
P2
P3
JG4
JG2
JG8
Figure 1-2. 56F803EVM Jumper Reference
Table 1-1. 56F803EVM Default Jumper Options
Jumper
Group
Comment
Jumpers
Connections
JG1
UNI-3 serial selected
1–2, 3–4, 5–6 & 7–8
JG2
Enable on-board Parallel JTAG Command Converter Interface
NC
JG3
Use on-board crystal for oscillator input
1–2
JG4
Selects device’s Mode 0, BOOT From FLASH, operation upon exit from
reset
1–2
JG5
Enable external SRAM
1–2
JG6
UNI-3 3-Phase Current Source Selected
2–3, 5–6 & 8–9
JG7
Encoder Input Selected
2–3, 5–6 & 8–9
JG8
On-board Parallel JTAG Command Converter powered by Host System
1-2
JG9
Use on-board crystal for oscillator input
1–2
JG10
Leave CAN bus un-terminated
NC
Introduction, Rev. 5
Freescale Semiconductor
1-3
1.3 56F803EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external +12V
DC power supply to the 56F803EVM board.
Parallel Extension
Cable
56F803EVM
PC-compatible
Computer
P2
Connect cable
to Parallel/Printer port
P3
External with 2.1mm,
+12V receptacle
Power connector
Figure 1-3. Connecting the 56F803EVM Cables
Perform the following steps to connect the 56F803EVM cables:
1. Connect the parallel extension cable to the Parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P2, shown in Figure 1-3, on the
56F803EVM board. This provides the connection which allows the host computer to
control the board.
3. Make sure that the external +12V DC, 4.0A power supply is not plugged into a +120V AC
power source.
4. Connect the 2.1mm output power plug from the external power supply into P3, shown in
Figure 1-3, on the 56F803EVM board.
5. Apply power to the external power supply. The green Power-On LED will illuminate
when power is correctly applied.
DSP56F803EVM User Manual, Rev. 5
1-4
Freescale Semiconductor Chapter 2
Technical Summary
The 56F803EVM is designed as a versatile controller development card for developing real-time
software and hardware products to support a new generation of applications in digital and
wireless messaging, servo and motor control, digital answering machines, feature phones,
modems, and digital cameras. The power of the 16-bit 56F803 controller, combined with the
on-board 64K u16-bit external program Static RAM (SRAM), 64K u16-bit external data
SRAM, CAN interface, Hall-Effect/Quadrature Encoder interface, motor zero crossing logic,
motor bus over-current logic, motor bus over-voltage logic and parallel JTAG interface, makes
the 56F803EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F803 processor.
The main features of the 56F803EVM include:
•
56F803 16-bit +3.3V controller operating at 80MHz [U1]
•
External fast Static RAM (FSRAM) memory [U2], configured as:
— 64Ku16-bit of Program memory with 0 wait states at 70MHz
— 64Ku16-bit of Data memory with 0 wait states at 70MHz
•
8.00MHz crystal oscillator for device frequency generation [Y1]
•
Optional external oscillator frequency input connector [JG3 and JG9]
•
Joint Test Action Group (JTAG) port interface connector for an external debug Host
Target Interface [J1]
•
On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port
cable [P2]
•
RS-232 interface for easy connection to a host processor [U3 and P4]
•
CAN interface for high speed, 1.0Mbps, communications [U15 and J3]
•
CAN bypass and bus termination [J13 and JG10]
•
Connector to allow the user to connect his own SCI / GPIO-compatible peripheral [J12]
•
Connector to allow the user to connect his own SPI / MPIO-compatible peripheral [J6]
•
Connector to allow the user to connect his own PWM / GPIO-compatible peripheral [J4]
•
Connector to allow the user to connect his own CAN physical layer peripheral [J5]
•
Connector to allow the user to connect his own Timer / MPIO-compatible peripheral [J10]
Technical Summary, Rev. 5
Freescale Semiconductor
2-1
•
Connector to allow the user to connect to the device’s A/D Port [J9]
•
56F803’s external memory expansion connectors [J7, J8 and J11]
•
On-board power regulation from an external +12V DC-supplied power input [P3]
•
Light Emitting Diode (LED) power indicator [LED1]
•
Six on-board PWM monitoring LEDs [LED2-LED7]
•
On-board real-time user debugging LED [LED8]
•
UNI-3 Motor interface [P1]
— Encoder/Hall-Effect interface
— Over-Voltage sensing [U14]
— Over-Current sensing [U14]
— DC Bus Voltage sensing [U13]
— DC Bus Current sensing [U13]
— Back-EMF sensing
— Temperature sensing
— Zero Crossing detection
— Pulse Width Modulation
— Power Factor Correction (PFC) sensing
•
Manual RESET push-button [S4]
•
Manual interrupt push-button for IRQA [S2]
•
Manual interrupt push-button for IRQB [S3]
•
General purpose toggle switch for RUN/STOP control(AN7) [S1]
2.1 56F803
The 56F803EVM uses a Freescale DSP56F803BU80 part, designated as U1 on the board and in
the schematics. This part will operate at a maximum speed of 80MHz. A full description of the
56F803, including functionality and user information, is provided in the following documents:
•
56F803 Technical Data, (DSP56F803): Provides features list and specifications including
signal descriptions, DC power requirements, AC timing requirements and available
packaging.
DSP56F803EVM User Manual, Rev. 5
2-2
Freescale Semiconductor 56F803
•
DSP56F801/803/805/807 User’s Manual, (DSP56F801-7UM): Provides an overview
description of the controller and detailed information about the on-chip components
including the memory and I/O maps, peripheral functionality, and control/status register
descriptions for each subsystem.
•
DSP56800 Family Manual, (DSP56800FM): Provides a detailed description of the core
processor including internal status and control registers and a detailed description of the
family instruction set.
These manuals contain detailed information about chip functionality and operation and can be
found at this URL:
http://www.freescale.com
Technical Summary, Rev. 5
Freescale Semiconductor
2-3
2.2 Program and Data Memory
The 56F803EVM uses one bank of 128Ku16-bit Fast Static RAM (GSI GS72116, labeled U2)
for external memory expansion; see the FSRAM schematic diagram in Figure 2-1. This physical
memory bank is split into two logical memory banks of 64Kx16-bits: one for Program memory
and the other for Data memory. By using the device’s program strobe, PS, signal line along with
the memory chip’s A0 signal line, half of the memory chip is selected when Program memory
accesses are requested and the other half of the memory chip is selected when Data memory
accesses are requested. This memory bank will operate with zero wait-state accesses while the
56F803 is running at 70MHz. However, when running at 80MHz, the memory bank operates
with four wait-state accesses. This memory bank can be disabled by removing the jumper at JG5.
56F803
GS72116
A0-A15
A1-A16
PS
A0
D0-D15
D0-D15
RD
RD
WR
WR
+3.3V
Jumper Removed:
Disable SRAM
JG5
1
2
Connect Pin 1-2:
Enable SRAM
CS
Figure 2-1. Schematic Diagram of the External Memory Interface
DSP56F803EVM User Manual, Rev. 5
2-4
Freescale Semiconductor RS-232 Serial Communications
2.3 RS-232 Serial Communications
The 56F803EVM provides an RS-232 interface by the use of an RS-232 level converter,
(Analog Devices ADM3311EARS, designated as U3); refer to the RS-232 schematic
diagram in Figure 2-2. The RS-232 level converter transitions the SCI UART’s +3.3V
signal levels to RS-232 compatible signal levels and connects to the host’s serial port via
connector P4. Flow control is not provided, but could be implemented using uncommitted
GPIO signals. The pin-out of connector P4 is listed in Table 2-1.
RS-232
Level Interface
56F803
RS-232
DB9
1
6
TXD0
T1in
RXD0
R1out
T1out
2
R1in
3
7
8
x
4
9
5
P4
Figure 2-2. Schematic Diagram of the RS-232 Interface
Table 2-1. RS-232 Serial Connector Description
P4
Pin #
Signal
Pin #
Signal
1
Jumper to 6 & 4
6
Jumper to 1 & 4
2
TXD
7
Jumper to 8
3
RXD
8
Jumper to 7
4
Jumper to 1 & 6
9
N/C
5
GND
Technical Summary, Rev. 5
Freescale Semiconductor
2-5
2.4 Clock Source
The 56F803EVM uses an 8.00MHz crystal, Y1, connected to its External Crystal Inputs, EXTAL
and XTAL. The 56F803 uses its internal PLL to multiply the input frequency by 10 to achieve its
80MHz maximum operating frequency. An external oscillator source can be connected to the
controller by using the oscillator bypass connectors, JG3 and JG9; see Figure 2-3.
EXTERNAL
OSCILLATOR
HEADERS
JG3
3
2
1
56F803
EXTAL
8.00MHz
1
2
JG9
XTAL
Figure 2-3. Schematic Diagram of the Clock Interface
2.5 Operating Mode
The 56F803EVM provides a boot-up MODE selection jumper, JG4. This jumper is used to select
the operating mode of the controller as it exits RESET. Refer to the DSP56F801-7 User’s Manual
for a complete description of the chip’s operating modes. Table 2-2 shows the two operation
modes available on the 56F803.
Table 2-2. Operating Mode Selection
Operating Mode
JG4
0
1–2
3
No Jumper
Comment
Bootstrap from internal memory (GND)
Bootstrap from external memory (+3.3V)
DSP56F803EVM User Manual, Rev. 5
2-6
Freescale Semiconductor Debug Support
2.6 Debug LED
An on-board Light-Emitting Diode, (LED), is provided to allow real-time debugging for user
programs. This LED allows the programmer to monitor program execution without having to
stop the program during debugging; refer to Figure 2-4. LED8 is controlled by the MOSI signal
line. Setting MOSI to a Logic One value will turn on the LED.
+3.3V
56F803
LED 8
MOSI
BUFFER
GREEN LED
Figure 2-4. Schematic Diagram of the Debug LED Interface
2.7 Debug Support
The 56F803EVM provides an on-board Parallel JTAG Host Target Interface and a JTAG
interface connector for external Host Target Interface support. Two interface connectors are
provided to support each of these debugging approaches. These two connectors are designated
the JTAG connector and the Host Parallel Interface Connector.
2.7.1 JTAG Connector
The JTAG connector on the 56F803EVM allows the connection of an external Host Target
Interface for downloading programs and working with the 56F803’s registers. This connector is
used to communicate with an external Host Target Interface which passes information and data
back and forth with a host processor running a debugger program. Table 2-3 shows the pin-out
for this connector.
Technical Summary, Rev. 5
Freescale Semiconductor
2-7
Table 2-3. JTAG Connector Description
J1
Pin #
Signal
Pin #
Signal
1
TDI
2
GND
3
TDO
4
GND
5
TCK
6
GND
7
NC
8
KEY
9
RESET
10
TMS
11
+3.3V
12
NC
13
NC
14
TRST
When this connector is used with an external Host Target Interface, the parallel JTAG
interface should be disabled by placing a jumper in jumper block JG2. Reference
Table 2-4 for this jumper’s selection options.
Table 2-4. Parallel JTAG Interface Disable Jumper Selection
JG2
Comment
No jumper
On-board Parallel JTAG Interface Enabled
1–2
Disable on-board Parallel JTAG Interface
2.7.2 Parallel JTAG Interface Connector
The Parallel JTAG Interface Connector, P2, allows the 56F803 to communicate with a
Parallel Printer Port on a Windows PC; see Figure 2-5. By using this connector, the user
can download programs and work with the 56F803’s registers. Table 2-5 shows the
pin-out for this connector. When using the parallel JTAG interface, the jumper at JG2
should be removed; refer to Table 2-4. A jumper, JG8, is provided to allow the on-board
Host Target Interface to be powered by the Target board instead of the Host system, as
shown in Table 2-6.
DSP56F803EVM User Manual, Rev. 5
2-8
Freescale Semiconductor Debug Support
PARALLEL JTAG
INTERFACE LOGIC
DB-25
PORT_TDI
56F803
TDI
PORT_TDO
TDO
PORT_TRST
TRST
PORT_TMS
TMS
PORT_TCK
TCK
PORT_RESET
RESET
Figure 2-5. Block Diagram of the Parallel JTAG Interface
Table 2-5. Parallel JTAG Interface Connector Description
P2
Pin #
Signal
Pin #
Signal
1
NC
14
NC
2
PORT_RESET
15
PORT_IDENT
3
PORT_TMS
16
NC
4
PORT_TCK
17
NC
5
PORT_TDI
18
GND
6
PORT_TRST
19
GND
7
NC
20
GND
8
PORT_IDENT
21
GND
9
PORT_VCC
22
GND
10
NC
23
GND
11
PORT_TDO
24
GND
12
NC
25
GND
13
PORT_CONNECT
Technical Summary, Rev. 5
Freescale Semiconductor
2-9
Table 2-6. On-Board Host Target Interface Power Source Jumper Selection
JG8
Comment
1–2
Host supplied power
2–3
Target supplied power
2.8 External Interrupts
Two on-board push-button switches are provided for external interrupt generation, as
shown in Figure 2-9. S2 allows the user to generate a hardware interrupt for signal line
IRQA.; S3 allows the user to generate a hardware interrupt for signal line IRQB. These
two switches allow the user to generate interrupts for his user-specific programs.
+3.3V
56F803
IRQA
IRQA
+3.3V
IRQB
IRQB
Figure 2-6. Schematic Diagram of the User Interrupt Interface
DSP56F803EVM User Manual, Rev. 5
2-10
Freescale Semiconductor Power Supply
2.9 Reset
Logic is provided in the 56F803 to generate a clean power-on RESET signal. Additional,
reset logic is provided to support the RESET signals from the JTAG connector, the
Parallel JTAG Interface and the user RESET push-button; see Figure 2-7.
+3.3V
RESET
PUSHBUTTON
MANUAL RESET
RESET
P_RESET
Figure 2-7. Schematic Diagram of the RESET Interface
2.10 Power Supply
The main power input, +12V DC at 4.0A, to the 56F803EVM is through a 2.1mm coax
power jack. A 4.0A power supply is provided with the 56F803EVM; however, less than
500mA is required by the EVM. The remaining current is available for user motor control
applications. The 56F803EVM provides +3.3V DC voltage regulation for the device,
memory, RS-232, CAN, parallel JTAG interface and supporting logic; refer to Figure 2-8.
Power applied to the 56F803EVM is indicated with a Power-On LED, referenced as
LED1.
+12V DC
+5.0V
Regulator
+5.0V DC
+3.3V
Regulator
+3.3V DC
56F803
56F803EVM
PARTS
Figure 2-8. Schematic Diagram of the Power Supply
Technical Summary, Rev. 5
Freescale Semiconductor
2-11
2.11 UNI-3 Interface
Motor control signals from a family of motor driver boards can be connected to the EVM board
via the UNI-3 connector/interface. The UNI-3 connector/interface contains all of the signals
needed to drive and control the motor drive boards. These signals are connected to differing
groups of the device’s input and output ports: A/D, TIMER and PWM. Refer to Table 2-7 for the
pin out of the UNI-3 connector.
Table 2-7. UNI-3 Connector Description
P1
Pin #
Signal
Pin #
Signal
1
PWM_AT
2
Shield
3
PWM_AB
4
Shield
5
PWM_BT
6
Shield
7
PWM_BB
8
Shield
9
PWM_CT
10
Shield
11
PWM_CB
12
GND
13
GND
14
+5.0V DC
15
+5.0V DC
16
Analog +3.3V DC
17
Analog GND
18
Analog GND
19
Analog +15V DC
20
Analog -15V DC
21
Motor DC Bus Voltage
Sense
22
Motor DC Bus Current
Sense
23
Motor Phase A Current
Sense
24
Motor Phase B Current
Sense
25
Motor Phase C Current
Sense
26
Motor Drive Temperature
Sense
27
NC
28
Shield
29
Motor Drive Brake Control
30
Serial COM
31
PFC PWM
32
PFC Inhibit
33
PFC Zero Cross
34
Zero Cross A
DSP56F803EVM User Manual, Rev. 5
2-12
Freescale Semiconductor Run/Stop Switch
Table 2-7. UNI-3 Connector Description (Continued)
P1
Pin #
Signal
Pin #
Signal
35
Zero Cross B
36
Zero Cross C
37
Shield
38
Back-EMF Phase A Sense
39
Back-EMF Phase B Sense
40
Back-EMF Phase C Sense
2.12 Run/Stop Switch
A Run/Stop toggle switch is connected to GPIO signal AN7, as shown in Figure 2-9. An optional
series resistor is provided which, when removed, allows the user to utilize the AN7 signal for
other purposes.
56F803
+3.3V
RUN/STOP SWITCH
AN7
Figure 2-9. Run/Stop Switch
Technical Summary, Rev. 5
Freescale Semiconductor
2-13
2.13 Motor Control PWM Signals and LEDs
The 56F803 has a dedicated PWM unit. The unit contains six PWM, three Phase Current sense
and four Fault input lines. The PWM lines are connected to the UNI-3 interface connector and to
a set of six PWM LEDs via inverting buffers. The buffers are used to isolate and drive the
controller’s PWM outputs to the PWM LEDs. The PWM LEDs indicate the status of PWM group
signals, refer to Figure 2-12. The PWM group signals are routed out to headers and are available
for use by the end user.
56F803
UNI-3
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
+3.3V
YELLOW LED
LED 2
PWM_AT / 0
LED 3
PWM_AB / 1
LED 4
PWM_BT / 2
GREEN LED
YELLOW LED
GREEN LED
LED 5
BUFFER
PWM_BB / 3
YELLOW LED
LED 6
PWM_CT / 4
GREEN LED
LED 7
PWM_CB / 5
Figure 2-10. PWM Group Interface and LEDs
2.14 Motor Protection Logic
The 56F803EVM contains a UNI-3 connector that interfaces with various motor drive boards.
The controller can sense error conditions generated by the motor power stage boards via signals
on the UNI-3 connector. The motor driver board’s Motor Supply DC Bus Voltage, Current and
Motor Phase Currents are sensed on the power stage board. The conditioned signals are
transferred to the device board via the UNI-3 connector. These analog input signals are compared
to limits set by trimpots. If the input analog signals are greater than the limit set by the trimpot, a
digital-compatible, +3.3V DC, fault signal is generated.
DSP56F803EVM User Manual, Rev. 5
2-14
Freescale Semiconductor Motor Protection Logic
2.14.1 UNI-3 Motor Protection Logic
The UNI-3 DC Bus Over-Voltage signal is connected to the controller’s PWM group’s fault
input, FAULT0. The UNI-3 DC Bus Over-Current signal is connected to the device’s PWM
group’s fault input, FAULT1. Additionally, the UNI-3 DC Bus Over-Voltage and Over-Current
analog signals are connected to two A/D inputs, AN0 and AN1, respectively. Figure 2-11
contains the diagram of the DC Bus Over-Voltage and DC Bus Over-Current circuit for the
UNI-3 interface.
DC BUS VOLTAGE SENSE
V_sense_DCB
+3.3V
+5.0V
+5.0V
+
–
FAULT0
LM393
DC BUS CURRENT SENSE
I_sense_DCB
+3.3V
+5.0V
+5.0V
+
–
FAULT1
LM393
Figure 2-11. DC Bus Over-Voltage and Over-Current Detection Schematic Diagram
Technical Summary, Rev. 5
Freescale Semiconductor
2-15
2.15 Back-EMF and Motor Phase Current Sensing
The UNI-3 connector supplies Back-EMF and Motor Phase Current signals from the three
phases of a motor attached to a motor drive unit. The Back-EMF signals on the UNI-3
connectors are derived from a resistor divider network contained in the motor drive unit.
These resistors divide down the attached motor’s Back-EMF voltages to a 0 to +3.3V
level. In certain instances, the Back-EMF signals can exceed this maximum range. The
Motor Phase Current signals are derived from current sense resistors. Both of these signal
groups are then routed to a group of header pins that allow the end user to select which
signal group the device’s A/D will monitor. Refer to Figure 2-12 for the design of a single
channel.
JG6
BACK_EMF_A
1
PHASE_A_I_SENSE
3
2
AN2
Figure 2-12. Primary Back-EMF or Motor Phase Current Sense Signals
DSP56F803EVM User Manual, Rev. 5
2-16
Freescale Semiconductor Zero-Crossing Detection
2.16 Quadrature Encoder/Hall-Effect Interface
The 56F803EVM board contains a Quadrature Encoder/Hall-Effect interface connected to the
device’s Quad Encoder input port. The circuit is designed to accept +3.0V to +5.0V encoder or
Hall-Effect sensor inputs. Input noise filtering is supplied on the input path for the Quadrature
Encoder/Hall-Effect interface, along with additional noise rejection circuitry inside the
controller. Figure 2-13 shows the encoder interface.
2.17 Zero-Crossing Detection
An attached UNI-3 motor drive board contains logic that can send out pulses when the phase
voltage of an attached 3-phase motor drops to zero. The motor drive board circuits generate a 0 to
+3.3V DC pulse via voltage comparators. The resulting pulse signals are sent to a set of jumper
blocks shared with the Encoder/Hall-Effect interface. The jumper blocks allow the selection of
Zero-Crossing signals or Quadrature Encoder/Hall-Effect signals. When in operation, the
controller will only monitor one set of signals, either the Encoder/Hall-Effect or the
Zero-Crossing. Figure 2-13 shows the Zero-Crossing and Encoder/Hall circuits.
ZERO_X_A
56F803
ZERO_X_B
JG7
1
ZERO_X_C
2
PHASEA
5
PHASEB
8
INDEX
3
+5.0V
FILTER
4
J2
6
1
2
3
4
5
6
PIN 1:
PIN 2:
PIN 3:
PIN 4:
PIN 5:
PIN 6:
FILTER
FILTER
7
9
+5.0V
GROUND
PHASE A
PHASE B
INDEX
HOME
FILTER
HOME
Figure 2-13. Zero-Crossing Encoder Interface
Technical Summary, Rev. 5
Freescale Semiconductor
2-17
2.18 CAN Interface
The 56F803EVM board contains a CAN physical-layer interface chip that is attached to the
MSCAN_RX and MSCAN_TX pins on the 56F803. The EVM board uses a Philips,
PCA82C250, high speed, 1Mbps, physical layer interface chip. Due to the +5.0V operating
voltage of the CAN chip, a pull-up to +5.0V is required to level shift the Transmit Data output
line from the 56F803. A primary, J3, and a daisy-chain, J13, CAN connector are provided to
allow easy daisy-chaining of CAN devices. Refer to Figure 2-14 for a connection diagram and to
Table 2-8 for the CAN signals.
CAN CONNECTOR
X
56F803
+5.0V
X
X
U15
MSCAN_TX
MSCAN_RX
1
4
8
TXD
VCC 3
VREF 5
RXD
CANH 7
CANL 6
SLOPE
GND
2
J3
1
3
5
7
9
2
4
6
8
10
X
X
X
X
JG10
1
120
2
PCA82C250T
CAN TERMINATION
X
X
X
J13
1
3
5
7
9
2
4
6
8
10
X
X
X
X
DAISY-CHAIN
CAN CONNECTOR
Figure 2-14. CAN Interface
DSP56F803EVM User Manual, Rev. 5
2-18
Freescale Semiconductor Peripheral Connectors
Table 2-8. CAN Header Description
J3 and J13
Pin #
Signal
Pin #
Signal
1
NC
2
NC
3
CANL
4
CANH
5
GND
6
NC
7
NC
8
NC
9
NC
10
NC
2.19 Peripheral Connectors
The EVM board contains a group of Peripheral Expansion Connectors used to gain access
to the resources of the 56F803. The following signal groups have Expansion Connectors:
•
External Memory Control
•
Encoder/Timer Channel
•
Timer Channel
•
Address Bus
•
Data Bus
•
A/D Input Port
•
Serial Communications Port
•
Serial Peripheral Interface Port
•
CAN Port
•
PWM Port
Technical Summary, Rev. 5
Freescale Semiconductor
2-19
2.19.1 External Memory Control Signal Expansion Connector
The External Memory Control Signal connector contains the device’s external memory control
signal lines. See Table 2-9 for the names of these signals.
Table 2-9. External Memory Control Signal Connector Description
J8
Pin #
Signal
Pin #
Signal
1
RD
2
IRQA
3
WR
4
IRQB
5
PS
6
RESET
7
DS
8
NC
9
CLKO
10
DE
11
GND
12
+3.3V
2.19.2 Encoder/Timer Channel Expansion Connector
The Encoder/Timer Channel port is an MPIO port attached to the Timer expansion connector.
The port can act as a Quadrature Decoder interface port or as a general purpose Timer port. Refer
to Table 2-10 for the signals attached to the connector.
Table 2-10. Timer Connector Description
J2
Pin #
Signal
1
+5.0V
2
GND
3
PhaseA
4
PhaseB
5
INDEX
6
HOME
DSP56F803EVM User Manual, Rev. 5
2-20
Freescale Semiconductor Peripheral Connectors
2.19.3 Timer Channel Expansion Connector
The Timer Channel port is a GPIO timer port attached to the Timer D expansion connector. See
Table 2-11 for the signals attached to the connector.
Table 2-11. Timer D Connector Description
J10
Pin #
Signal
1
TD1
2
TD2
3
GND
4
+3.3V
2.19.4 Address Bus Expansion Connector
The 16-bit Address bus connector contains the controller’s external memory address signal lines.
The upper 8 bits, A8 - A15, can also be used as Port A GPIO lines. See Table 2-12 for the
Address bus connector information.
Table 2-12. External Memory Address Bus Connector Description
J7
Pin #
Signal
Pin #
Signal
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
A9
11
A10
12
A11
13
A12
14
A13
15
A14
16
A15
17
GND
18
+3.3V
Technical Summary, Rev. 5
Freescale Semiconductor
2-21
2.19.5 Data Bus Expansion Connector
The 16-bit Data bus connector contains the controller’s external memory data signal lines. Refer
to Table 2-13 for the Data bus connector information.
Table 2-13. External Memory Address Bus Connector Description
J11
Pin #
Signal
Pin #
Signal
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
D9
11
D10
12
D11
13
D12
14
D13
15
D14
16
D15
17
GND
18
+3.3V
DSP56F803EVM User Manual, Rev. 5
2-22
Freescale Semiconductor Peripheral Connectors
2.19.6 A/D Port Expansion Connector
The 8-channel Analog-to-Digital conversion port is attached to this connector. See Table 2-14 for
connection information.
Table 2-14. A/D Connector Description
J9
Pin #
Signal
1
AN0
2
AN1
3
AN2
4
AN3
5
AN4
6
AN5
7
AN6
8
AN7
9
GNDA
10
+3.3VA
2.19.7 Serial Communications Port Expansion Connector
The Serial Communications Port, SCI, is attached to this connector. Refer to Table 2-15 for
connection information.
Table 2-15. SCI Connector Description
J12
Pin #
Signal
1
TXD
2
RXD
3
GND
Technical Summary, Rev. 5
Freescale Semiconductor
2-23
2.19.8 Serial Peripheral Interface Expansion Connector
The Serial Peripheral Interface, SPI, is attached to this connector. See Table 2-16 for connection
information.
Table 2-16. SPI Connector Description
J6
Pin #
Signal
Pin #
Signal
1
SCLK
2
MOSI
3
MISO
4
SS
5
GND
6
+3.3V
2.19.9 CAN Expansion Connector
The CAN port is attached to this connector. Refer to Table 2-17 for connection information.
Table 2-17. CAN Connector Description
J5
Pin #
Signal
1
MSCAN_TX
2
MSCAN_RX
3
GND
DSP56F803EVM User Manual, Rev. 5
2-24
Freescale Semiconductor Test Points
2.19.10 PWM Port Expansion Connector
The PWM port is attached to this connector. Refer to Table 2-18 for connection information.
Table 2-18. PWM Port Connector Description
J4
Pin #
Signal
Pin #
Signal
1
ISA0
2
ISA1
3
ISA2
4
FAULT0
5
FAULT1
6
FAULT2
7
PWM0
8
PWM1
9
PWM2
10
PWM3
11
PWM4
12
PWM5
13
GND
14
+3.3V
2.20 Test Points
The 56F803EVM board has nine test points: Five near the breadboard, (+3.3V, GND, +3.3VA,
AGND and +5.0V), and four near the UNI-3 connector, (-15VA, GND, +15VA and GND).
Technical Summary, Rev. 5
Freescale Semiconductor
2-25
DSP56F803EVM User Manual, Rev. 5
2-26
Freescale Semiconductor Appendix A
56F803EVM Schematics
56F803EVM Schematics, Rev. 5
Freescale Semiconductor
Appendix A-1
DSP56F803EVM User Manual, Rev. 5
Appendix A-2
Freescale Semiconductor A
B
C
D
5
5
D[0..15]
A[0..15]
CLKO
XTAL
EXTAL
/DE
/RESET
EXTBOOT
/IRQA
/IRQB
/WR
/RD
/PS
/DS
4
4
9
28
63
67
93
81
57
58
80
33
79
78
31
32
29
30
24
25
89
90
91
94
95
96
97
98
99
100
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
21
22
26
27
U1
VSS
VSS
VSS
VSS
VSS
TCK
TMS
TDI
TDO
TRST
VDD
VDD
VDD
VDD
VDD
VCAPC
VCAPC
VDDA
VDDA
VSSA
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
VRH
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
ISA0
ISA1
ISA2
FAULTA0
FAULTA1
FAULTA2
MSCAN_TX
MSCAN_RX
TXD0/PE0
RXD0/PE1
TD1
TD2
PHASEA0/TA0
PHASEB0/TA1
INDEX0/TA2
HOME0/TA3
MOSI/PE5
MISO/PE6
SCLK/PE4
SS/PE7
DSP56F803BU80
CLK0
XTAL
EXTAL
DE
TCS
RESET
EXTBOOT
IRQA
IRQB
WR
RD
PS
RS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6/PE2
A7/PE3
A8/A0
A9/A1
A10/A2
A11/A3
A12/A4
A13/A5
A14/A6
A15/A7
8
23
61
66
92
39
88
60
62
59
49
50
51
52
53
54
55
56
48
70
71
72
73
74
75
40
41
42
43
45
47
44
46
76
77
82
83
64
65
68
69
86
85
87
84
34
35
36
37
38
3
C1
2.2uF
50VDC
+3.3V
+3.3VA
+
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
IS0
IS1
IS2
FAULT0
FAULT1
FAULT2
PHASEA
PHASEB
INDEX
HOME
+
CAN
RS-232
PFC PWM
PFC ZERO CROSSING
PHASE CURRENT SENSE
Date:
2
Monday, June 22, 1998
D o c u ment
N u mber
D S P 5 6 8 0 3 P r o cessor
C2
2.2uF
50VDC
START / STOP
DC BUS OVERVOLTAGE
DC BUS OVERCURRENT
PHASE A CURRENT BACK EMF PHASE A
PHASE B CURRENT BACK EMF PHASE B
PHASE C CURRENT BACK EMF PHASE C
DRIVE TEMPERATURE
1
1
1
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D S P 5 6 8 0 3 EVM.DSN
PULSE WIDTH MODULATION
Size
B
2
ENCODER / HALL EFFECT INPUT
DC BUS OVERVOLTAGE FAULT
DC BUS OVERCURRENT FAULT
Title
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
JTAG
USER LED 0
BRAKE CONTROL
PFC INHIBIT
serial_com
MSCAN_TX
MSCAN_RX
TXD
RXD
TD1
TD2
MOSI
MISO
SCLK
/SS
TCK
TMS
TDI
TDO
/TRST
Figure A-1. 56F803 Processor
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
3
1.3
R e v.
A
B
C
D
56F803EVM Schematics, Rev. 5
Freescale Semiconductor
Appendix A-3
A
B
C
D
5
5
8.00MHz
Y1
S4
1
2
JG9
3
2
Date:
3
2
1
2
1
2
1
/IRQB
/IRQA
E X T B OOT
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DSP56803EVM.DSN
Monday, July 10, 2000
Document
N u m ber
JG4
R20
10K
+3.3V
C39
0.1uF
R18
10K
+3.3V
C36
0.1uF
R16
10K
+3.3V
Wireless Subscriber Division
S3
IRQB PUSHBUTTON
S2
IRQA PUSHBUTTON
2
BOOT MODE JUMPER
EXT BOOT
NC
INT BOOT
1 - 2
R E S ET, MODES, CLOCK, IRQS
/RESET
XTAL
E X T AL
3
Figure A-2. Reset, Mode, Clock & IRQsL
4
A
Size
Title
RESET PUSHBUTTON
10M
R17
1
JG3
OSC BYPASS
4
1.3
Rev.
A
B
C
D
DSP56F803EVM User Manual, Rev. 5
Appendix A-4
Freescale Semiconductor A
B
C
D
NC
SRAM DISABLE
5
1 - 2
SRAM ENABLE
4
4
2
A
Size
Title
JG5
2
1
R21
10K
R66
10K
/RD
/WR
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
R67
10K
41
17
6
39
40
5
4
3
2
1
44
43
42
27
26
25
24
21
20
19
18
22
U2
Date:
3
12
34
11
33
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
+3.3V
D[0..15]
2
1
3
1
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MD:OE314
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DSP56803EVM.DSN
Monday, June 22, 1998
Document
N u m ber
VSS
VSS
VDD
VDD
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
GS72116TP-12
OE
WE
CE
LB
UB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
P R OGRAM and DATA SRAM MEMORY
+3.3V
A[0..15]
/PS
64Kx16-bit Program and 64Kx16-bit Data Memory
3
Figure A-3. Program & Data SRAM Memory
SRAM ENABLE JUMPER
OPTION
JUMPER
5
1.3
Rev.
A
B
C
D
56F803EVM Schematics, Rev. 5
Freescale Semiconductor
Appendix A-5
A
B
C
D
1K
1K
1K
1K
R24
R25
R26
R27
R28
T2IN
T3IN
R4IN
R5IN
/EN
5
1K
R23
R3IN
1K
1K
R22
RXD
TXD
R2IN
5
C43
R68
1K
A
Size
Title
1
1
1
1
/EN
TP81
TP82
TP83
TP85
T2IN
T3IN
23
5
10
11
12
13
14
7
8
9
6
1
4
2
3
SD
EN
V-
C1-
GND
C3-
C3+
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
T3OUT
ADM3311EARS
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
T1IN
T2IN
T3IN
C1+
V+
C2-
C2+
VCC
U3
19
18
17
16
15
22
21
20
24
27
26
28
25
C42
R2IN
R3IN
R4IN
R5IN
Date:
3
TP79
TP80
C44
0.1uF
2
1
6
2
7
3
8
4
9
5
DB9S
P4
3: RXD
2: TXD
SCI
RS-232
CONNECTOR
2
1
4
1
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MD:OE314
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Designer: Development Tools
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Wireless Subscriber Division
DSP56803EVM.DSN
Monday, June 22, 1998
Document
N u m ber
1
1
0.1uF
RS-232 AND SCI CONNECTORS
0.1uF
C41
+3.3V
0.1uF
C40
3
Figure A-4. RS-232 and SCI Connectors
4
0.1uF
4
1.3
Rev.
A
B
C
D
DSP56F803EVM User Manual, Rev. 5
Appendix A-6
Freescale Semiconductor A
B
C
D
5
5
MOSI
USER LED
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
13
9
3
12
8
4
A
Size
2
11
5
74AC04
U10E
74AC04
U10C
74AC04
U10A
R35
10
6
2
270
Date:
3
270
270
270
270
270
270
GREEN LED
LED7
LED6
LED5
LED4
LED3
LED2
+3.3V
GREEN LED
YELLOW LED
GREEN LED
YELLOW LED
GREEN LED
YELLOW LED
+3.3V
2
1
5
1
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MD:OE314
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Wireless Subscriber Division
LED8
DSP56803EVM.DSN
Monday, June 22, 1998
Document
N u m ber
R34
R33
R32
R31
R30
R29
LEDS
PWM STATE
2
USER LED
DSP56803 PWM LEDS AND USER LED
74AC04
Title
1
U12A
74AC04
U10F
74AC04
U10D
74AC04
U10B
1
3
Figure A-5. 56F803 PWM LEDs and User LED
4
4
1.3
Rev.
A
B
C
D
56F803EVM Schematics, Rev. 5
A
B
C
5
V_S_DCB
16K
AN1
4
16K
R41
16K
+5.0V
10K
R45
C46
0.1uF
R42
16K
+5.0V
10K
R40
C45
0.1uF
R37
2
3
R38
-
+
6
5
-
+
LM393A
7
U14B
1M
+5.0V
R43
1
LM393A
U14A
+5.0V
1M
DSP PWM
FAULT0
FAULT SENSE 0
3
R44
5.1K
+3.3V
FAULT1
B
Size
Title
2
Date:
(512)895-3230
2
D e s i g n er: Development Tools
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D S P 5 6 8 0 3 EVM.DSN
Monday, June 22, 1998
D o c u ment
N u mber
1
Wireless Subscriber Division
U N I - 3 O V E R V O L T A G E A N D C U RRENT SENSE
FAULT SENSE 1
DSP PWM
UNI-3 OVER-CURRENT
FAULT DETECTION
R39
5.1K
+3.3V
UNI-3 OVER-VOLTAGE
FAULT DETECTION
3
Figure A-6. UNI-3 Over-Voltage and Current Sense
I_S_DCB
CURRENT SENSE
AN0
R36
VOLTAGE SENSE
4
8
4
D
5
8
4
Freescale Semiconductor
Appendix A-7
1.3
R e v.
A
B
C
D
DSP56F803EVM User Manual, Rev. 5
Appendix A-8
Freescale Semiconductor A
B
C
D
1
2
3
4
5
6
PIN
PIN
PIN
PIN
PIN
PIN
1:
2:
3:
4:
5:
6:
5
+5.0V
GROUND
PHASE A
PHASE B
INDEX
HOME
ENCODER /
HALL
EFFECT
CONNECTOR
J2
ZERO_X_C
ZERO_X_B
ZERO_X_A
C52
470pF
24
+
4
R57
C48
2.2uF
50VDC
4
A
Size
Title
24
R52
1K
R53
24
R50
C51
470pF
R54
24
24
R47
C50
470pF
R51
24
24
C49
470pF
R48
24
Date:
(512)895-3230
DSP56803EVM.DSN
3
Monday, June 22, 1998
Document
N u m ber
2
5
9
7
8
JG7C
6
4
JG7B
3
1
JG7A
6 5 0 1 William Cannon Drive West
2
Designer: Development Tools
HOME
INDEX
PHASEB
PHASEA
7
1
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1
C O N N E CT
1-2: ZERO CROSSING
INFORMATION
2-3: ENCODER / HALL
EFFECT INFORMATION
Wireless Subscriber Division
2
ZERO CROSSING, ENCODER, HALL EFFECT SELECTION
+5.0V
R49
1K
+5.0V
R46
1K
+5.0V
3
Figure A-7. Zero-Crossing/ Encoder or Hall-Effect Selection
R56
R55
1K
+5.0V
C47
0.1uF
+5.0V
UNI-3: ZERO CROSSING
5
1.3
Rev.
A
B
C
D
56F803EVM Schematics, Rev. 5
Freescale Semiconductor
Appendix A-9
A
B
C
D
5
MSCAN_TX
MSCAN_RX
5
R58
1K
+5.0V
8
1
4
GND
CANH
CANL
VCC
VREF
PCA82C250T
SLOPE
TXD
RXD
U15
4
2
7
6
3
5
4
J3
2
4
6
8
10
Date:
3
CANL
1
2
JG10
1
3
5
7
9
J13
2
4
6
8
10
2
1
CANH
8
1
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R61
120
1/4W
DSP56803EVM.DSN
Wednesday, July 05, 2000
Document
N u m ber
CANL
CANH
2
DAISY-CHAIN
CAN BUS CONNECTOR
Figure A-8. High Speed CAN Interface
A
Size
Title
1
3
5
7
9
CAN BUS CONNECTOR
HIGH SPEED CAN INTERFACE
TP86
CANH
CANL
1
+5.0V
3
1.3
Rev.
A
B
C
D
DSP56F803EVM User Manual, Rev. 5
A
B
C
D
SCLK
MISO
TD1
TD2
/RD
/WR
/PS
/DS
CLKO
MSCAN_TX
MSCAN_RX
1
2
3
J5
2
4
6
8
10
12
+3.3V
/DE
5
+3.3V
1
3
5
2
4
6
+3.3V
MOSI
/SS
4
4
IS0
IS2
FAULT1
PWM0
PWM2
PWM4
RXD
TXD
+3.3V
1
3
5
7
9
J9
2
4
6
8
10
J12
3
SCI
RAW SIGNALS
AN0
AN2
AN4
AN6
2
4
6
8
10
12
14
IS1
FAULT0
FAULT2
PWM1
PWM3
PWM5
AN1
AN3
AN5
AN7
+3.3VA
DSP A/D PORT
1
3
5
7
9
11
13
J4
PWM PORT
3
B
Size
Title
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
+3.3V
A1
A3
A5
A7
A9
A11
A13
A15
A[0..15]
D0
D2
D4
D6
D8
D10
D12
D14
2
4
6
8
10
12
14
16
18
+3.3V
D1
D3
D5
D7
D9
D11
D13
D15
(512)895-3230
FAX: (512)895-4556
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1
3
5
7
9
11
13
15
17
J11
DATA BUS CONNECTOR 0-15
Date:
D S P 5 6 8 0 3 EVM.DSN
2
Monday, June 22, 1998
D o c u ment
N u mber
D e s i g n er: Development Tools
1
Sheet
9
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MD:OE314
D[0..15]
PORT PA:0-7 SHARE ADDRESS BUS PINS A:8-15
A0
A2
A4
A6
A8
A10
A12
A14
J7
ADDRESS BUS CONNECTOR 0-15
1
P O R T T I M E R D , A D D R E S S , D A T A , A / D A N D C O N T R O L LINES CONNECTORS
D[0..15]
A[0..15]
2
Figure A-9. Port Timer D, Address, Data, A/D and Control Line Connectors
J6
SPI PORT
1
2
3
4
J10
TIMER CHANNEL D
1
3
5
7
9
11
J8
/IRQA
/IRQB
/RESET
RAW CAN
SIGNAL
CONNECTOR
CONTROL LINES
5
1
2
3
Appendix A-10
Freescale Semiconductor 1.3
R e v.
A
B
C
D
56F803EVM Schematics, Rev. 5
A
B
C
D
5
/SS
SCLK
BK_EMF_B
COM JUMPER
PFC INHIBIT JUMPER
UNI-3 SERIAL
PHASE B BACK EMF
ZERO_X_B
MOTOR DRIVE BRAKE CONTROL
MOTOR PHASE A CURRENT SENSE
MOTOR PHASE C CURRENT SENSE
PFC_PWM
PFC_ZERO_CROSS
UNI_3_+15
V_S_DCB
+5.0V_UNI3
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
4
1
3
5
7
JG1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
+5.0V_UNI3
+3.3VA
SERIAL_COM
PFC_INHIBIT
SERIAL_COM
PFC_INHIBIT
UNI_3_-15
I_S_DCB
TD1
TD2
PHASE A BACK EMF
PHASE C BACK EMF
3
B
Size
Title
2
Date:
TP9
2
-15VA
TP7
GND
GND
10K
R1
+3.3VA
1K
R9
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SW SPST
S1
RUN/STOP
D S P 5 6 8 0 3 EVM.DSN
Monday, June 22, 1998
D o c u ment
N u mber
+15VA
TP8
TP6
1
RUN / STOP SWITCH
UNI_3_-15
UNI_3_+15
TEST POINTS
U N I - 3 I N T E R F A C E A N D G P E N E R A L P URPOSE SWITCHES
PFC PWM JUMPER
PFC ZERO CROSSING JUMPER
ZERO_X_A
ZERO_X_C
BK_EMF_A
BK_EMF_C
AN1
U3_PHB_IS MOTOR PHASE B CURRENT SENSE
AN5
MOTOR DRIVE TEMPERATURE SENSE
3
Figure A-10. UNI-3 Interface and General Purpose Switches
PFC_PWM
PFC_ZERO_CROSS
MISO
AN0
U3_PHA_IS
U3_PHC_IS
PWM_AT
PWM_AB
PWM_BT
PWM_BB
PWM_CT
PWM_CB
P1
UNI-3 CONNECTOR
4
1
1
5
1
1
Freescale Semiconductor
Appendix A-11
1.3
R e v.
A
B
C
D
DSP56F803EVM User Manual, Rev. 5
Appendix A-12
Freescale Semiconductor A
B
C
D
5
5
3
6
U3_PHB_IS
A
8
AN4
AN3
AN2
(512)895-3230
FAX: (512)895-4556
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6 5 0 1 William Cannon Drive West
Date:
DSP56803EVM.DSN
3
Monday, June 22, 1998
Document
N u m ber
2
Designer: Development Tools
1
Sheet
1
11 of
MD:OE314
Wireless Subscriber Division
2
Figure A-11. Back-EMF and Phase Current Sense Analog Input Selectors
4
9
U3_PHC_IS
3
BACK-EMF AND PHASE CURRENT SENSE ANALOG INPUT SELECTORS
7
BK_EMF_C
Size
5
JG6C
4
BK_EMF_B
Title
2
JG6B
1
U3_PHA_IS
JG6A
BK_EMF_A
4
14
1.3
Rev.
A
B
C
D
56F803EVM Schematics, Rev. 5
Freescale Semiconductor
Appendix A-13
A
B
C
D
5
P_RESET
5
R8
10K
13
12
11
10
9
8
7
6
5
4
3
2
1
5.1K
Q1
2N2222/TO
5.1K
R5
+3.3V
/RESET
PORT_CONNECT
PORT_TDO
PORT_VCC
/PORT_TRST
PORT_TDI
PORT_TCK
PORT_TMS
PORT_RESET
DSP /RESET
DB25M
P2
4
51
R4
51
R3
R63
5.1K
JG8
1G
2G
2Y1
2Y2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
MC74HC244DW
VCC
GND
2A1
2A2
2Y3
2Y4
1A1
1A2
1A3
1A4
U6
1
19
9
7
15
17
18
16
14
12
R62
5.1K
1
R65
5.1K
TP46
R64
5.1K
TDO
/TRST
3
5.1K
R60
5.1K
R6
+3.3V
DSP /JTAG-RESET
On-Board
Host Target Interface
Power Source
+3.3V
C3
0.1uF
20
10
11
13
5
3
2
4
6
8
Parallel JTAG Interface
3
+3.3V
B
Size
Title
R2
5.1K
20
1
19
GND
2Y1
2Y2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
+3.3V
MC74HC244DW
VCC
1G
2G
2A1
2A2
2Y3
2Y4
1A1
1A2
1A3
1A4
U7
/RESET
TDI
TDO
TCK
10
9
7
15
17
18
16
14
12
+3.3V
1
TP47
2
4
6
8
10
12
14
KEY
TMS
(512)895-3230
Date:
D S P 5 6 8 0 3 EVM.DSN
2
Monday, June 22, 1998
D o c u ment
N u mber
D e s i g n er: Development Tools
1
Sheet
FAX: (512)895-4556
Austin, TX, 78735-8598
6 5 0 1 William Cannon Drive West
1 2 of 14
MD:OE314
/TRST
1
Wireless Subscriber Division
1
3
5
7
9
11
13
J1
JTAG Connector
TDO
/TRST
P_RESET
TMS
TCK
TDI
P A R A L L E L J T A G H O S T T A R G E T I N T E R F A C E AND JTAG CONNECTOR
On-Board
Host Target
Interface
Disable
2
1
JG2
11
13
5
3
2
4
6
8
2
Figure A-12. Parallel JTAG Host/Target Interface and JTAG Connector
R7
25
24
23
22
21
20
19
18
17
16
15
14
PORT_IDENT
4
1
2
3
1.3
R e v.
A
B
C
D
DSP56F803EVM User Manual, Rev. 5
A
5
1
C7
0.1uF
FM4001
D2
4
+3.3VA
+3.3V
+5.0V
TP5
+5.0V
TP1
+3.3V
TP3
+3.3VA
TP4
GNDA
TP2
GND
+3.3VA
+
C4
470uF
16VDC
C5
0.1uF
VOUT
VOUT
MC33269DT_5.0
GND
VIN
+5.0V
4
2
2
3
3
MC33269
1
4
3.3V AND 5.0V
REGULATOR
1
3
U8
FM4001
D1
3
1
3
VOUT
VOUT
4
2
B
Size
Title
MC33269DT_3.3
GND
VIN
U9
FM4001
D3
+5.0V_UNI3
+
+
C6
47uF
10VDC
2
C8
47uF
10VDC
+3.3V
Date:
2
1
1
1 3 of 14
MD:OE314
Sheet
FAX: (512)895-4556
D e s i g n er: Development Tools
(512)895-3230
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6 5 0 1 William Cannon Drive West
Wireless Subscriber Division
D S P 5 6 8 0 3 EVM.DSN
Monday, June 22, 1998
D o c u ment
N u mber
POWER GOOD LED
LED1
GREEN LED
470
R10
+5.0V
P O W E R S U P P L I E S + 3 . 3 V A N D +5.0V
FERRITE BEAD
L3
FERRITE BEAD
L1
Figure A-13. Power Supplies 3.3V and 5.0V
4
NEAR THE BREADBOARD AREA
FERRITE BEAD
L4
FERRITE BEAD
1
B
+3.3V
L2
P3
2
1
C
INPUT 12V DC
EXTERNAL POWER IN
3
1
D
1
5
1
Appendix A-14
Freescale Semiconductor 1.3
R e v.
A
B
C
D
56F803EVM Schematics, Rev. 5
Freescale Semiconductor
Appendix A-15
A
B
C
D
C11
4
1
R12
5.1K
R11
5.1K
5
5
74AC04
U12C
74AC04
6
1
TP55
TP52
C23
0.1uF
C22
+3.3VA
A/D CONNECTOR
0.1uF
+3.3V
11
9
C24
74AC04
U12E
74AC04
U12D
0.1uF
+3.3V
4
10
8
C25
1
1
1.0uF
50VDC
+3.3V
C14
TP56
TP53
0.1uF
+3.3VA
ADM3311E
C13
0.1uF
4
C26
0.1uF
+5.0V
LM393
C15
R59
5.1K
0.1uF
+5.0V
13
UNI-3
+5.0 VOLT
74AC04
U12F
12
3
C27
1
TP54
0.01uF
+3.3V
74HC244
0.1uF
C16
+3.3VA
UNI-3
+3.3 VA
3
0.1uF
C18
+3.3V
B
Size
Title
C30
C31
0.1uF
+3.3V
DATA BUS
CONNECTOR
C19
0.1uF
+5.0V
CAN
INTERFACE
Date:
2
C32
0.01uF
+3.3V
74AC04
C21
C33
(512)895-3230
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Sheet
FAX: (512)895-4556
Austin, TX, 78735-8598
6 5 0 1 William Cannon Drive West
1 4 of 14
MD:OE314
0.01uF
+3.3V
74AC04
0.1uF
+3.3V
TIMER D
HEADER
1
Wireless Subscriber Division
D S P 5 6 8 0 3 EVM.DSN
Monday, June 22, 1998
D o c u ment
N u mber
C20
0.1uF
+3.3V
CONTROL
HEADER
B Y P A S S C A P A C I T O R S A N D S P A R E G ATES
0.1uF
+3.3V
ADDRESS BUS
CONNECTOR
0.1uF
C17
+3.3V
GS72116
2
Figure A-14. Bypass Capacitors and Spare Gates
R14
5.1K
R13
5.1K
0.1uF
C12
DSP56F803
0.1uF
+3.3V
U12B
0.1uF
0.1uF
PWM
HEADER
C10
C9
3
5
1.3
R e v.
A
B
C
D
DSP56F803EVM User Manual, Rev. 5
Appendix A-16
Freescale Semiconductor Appendix B
56F803EVM Bill of Material
Qty
Description
Ref. Designators
Vendor Part #s
Integrated Circuits
1
DSP56F803BU80
U1
Freescale, DSP56F803BU80
1
GS72116TP-12
U2
GSI, GS72116TP-12
1
ADM3311EARS
U3
Analog Devices, ADM3311EARS
2
MC74HC244DW
U6, U7
ON Semiconductor, MC74HC244DW
1
MC33269DT-5.0
U8
ON Semiconductor, MC33269DT-5.0
1
MC33269DT-3.3
U9
ON Semiconductor, MC33269DT-3.3
2
74AC04SC
1
LM393
U14
National Semiconductor, LM393
1
PCA82C250T
U15
Philips Semiconductor, PCA82C250T
U10, U12
Fairchild, 74AC04SC
Resistors
4
16K :
R36, R37, R41, R42
SMEC RC73L2A16KOHMJT
2
1M :
R43, R38
SMEC RC73L2A1MOHMJT
16
5.1K :
R2, R5 - R7, R11 - R14, R39,
R44, R59, R60, R62 - R65
SMEC RC73L2A5.1KOHMJT
8
10K :
R1, R8, R16, R18, R20, R21,
R66, R67
SMEC RC73L2A10KOHMJT
2
51 :
R3, R4
SMEC RC73L2A51OHMJT
1
470 :
R10
SMEC RC73L2A470OHMJT
1
10M :
R17
SMEC RC73L2A10MOHMJT
14
1K :
R9, R22 - R28, R46, R49, R52,
R55, R58, R68
SMEC RC73L2A1KOHMJT
56F803EVM Bill of Material, Rev. 5
Freescale Semiconductor
Appendix B-1
Qty
Description
Ref. Designators
Vendor Part #s
Resistors (Continued)
7
270 :
R29 - R35
SMEC RC73L2A270OHMJT
8
24 :
R47, R48, R50, R51, R53, R54,
R56, R57
SMEC RC73L2A24OHMJT
1
120 :, 1/4W
R61
YAGEO CFR 120QBK
Potentioneters
2
10K :
R40, R45
BC/MEPCOPAL ST4B103CT
Inductors
4
1.0mH
L1 - L4
Fair-Rite 2743015112
LEDs
5
Green LED
LED1, LED3, LED5, LED7,
LED8
Hewlett-Packard HSMG-C650
3
Yellow LED
LED2, LED4, LED6
Hewlett-Packard HSMY-C650
Diode
3
FM4001
D1, D2, D3
Vishay DL4001DICT
Capacitors
3
2.2PF, 50V DC
C1, C2, C48
TTI UWX1H2R2MCR2GB
32
0.1PF
C3, C5, C7, C9 - C24, C26,
C30, C31, C35, C36,
C39 - C47
SMEC MCCE104K2NR-T1
3
0.01PF
C27, C32, C33
SMEC MCCE103K2NR-T1
1
470PF, 16V DC
C4
PANASONIC ECE-V1CA471P
2
47PF, 10V DC
C6, C8
PANASONIC ECE-V1AA470P
1
1.0PF, 50V DC
C25
TTI UWT1H010MCR1GB
4
470pF
C49 - C52
SMEC MCCE471J2NO-T1
Jumpers
4
3 u 1 Bergstick
JG3, JG8, J5, J12
SAMTEC TSW-103-07-S-S
1
4 u 2 Bergstick
JG1
SAMTEC TSW-104-07-S-D
5
1 u 2 Bergstick
JG2, JG4, JG5, JG9, JG10
SAMTEC TSW-102-07-S-S
DSP56F803EVM User Manual, Rev. 5
Appendix B-2
Freescale Semiconductor
Qty
Description
Ref. Designators
Vendor Part #s
Jumpers (Continued)
2
3 x 3 Bergstick
JG6, JG7
SAMTEC TSW-103-07-S-T
3
5 x 2 Bergstick
J3, J9, J13
SAMTEC TSW-105-07-S-D
1
4 x 1 Bergstick
J10
SAMTEC TSW-104-07-S-S
1
3 x 2 Bergstick
J6
SAMTEC TSW-103-07-S-D
2
9 x 2 Bergstick
J7, J11
SAMTEC TSW-109-07-S-D
2
7 x 2 Bergstick
J1, J4
SAMTEC TSW-107-07-S-D
1
6 x 1 MTA
J2
AMP MTA 640456-6
1
6 x 2 Bergstick
J8
SAMTEC TSW-106-07-S-D
Test Points
9
1 u 1 Bergstick
TP1, TP2, TP3, TP4, TP5, TP6,
TP7, TP8, TP9
Samtec TSW-101-07-S-S
Crystals
1
8.00MHz Crystal
Y1
ECS-80-18-5P
Connectors
1
20 x 2 Shrouded
P1
3M 2540-6002UB
1
DB25M Connector
P2
AMPHENOL 617-C025P-AJ121
1
2.1mm coax
Power Connector
P3
Switch Craft RAPC-722
1
DE9F Connector
P4
AMPHENOL 617-C009S-AJ120
Switches
1
SPDT Toggle
3
SPST Pushbutton
S1
S2, S3, S4
C&K GT11MSCKE
Panasonic EVQ-QS205K
Transistors
1
2N2222A
Q1
ZETEX FMMT2222ACT
Miscellaneous
11
Shunt
6
Rubber Feet
SH1–SH11
RF1–RF6
Samtec SNT-100-BL-T
3M SJ5018BLKC
56F803EVM Bill of Material, Rev. 5
Freescale Semiconductor
Appendix B-3
DSP56F803EVM User Manual, Rev. 5
Appendix B-4
Freescale Semiconductor
INDEX
Symbols
Connector
A/D 23
Address bus 21
CAN 24
Data bus 22
Encoder/Timer Channel 20
External Memory Control 20
PWM 25
SCI 23
SPI 24
Timer Channel 21
Connectors
Peripheral Expansion 19
Controller Area Network
CAN ix
+12VDC power supply 4
Numerics
4.0Amp power supply 11
56F803 Technical Data x
64Kx16-bit of data memory 1
64Kx16-bit of program memory 1
8.00MHz crystal oscillator 1
A
A/D ix
A/D Port 2
Analog-to Digital
A/D ix
D
Data memory 4
Development Card 1
DSP56800 Family Manual x
DSP56F801/803/805/807 User’s Manual x
B
Back-EMF
signals 16
voltages 16
E
C
CAN ix
bus termination 1
bypass 1
interface 1
CAN in Automation
CiA ix
CAN interface 1
CAN physical layer peripheral 1
CAN Specification 2.0B x
CiA ix
CiA Draft Recommendation DR-303-1, Cabling and
Connector Pin Assignment x
Encoder/Hall-Effect
circuits 17
Encoder/Timer Channel 20
Evaluation Module
EVM ix
EVM ix
External Memory Control Signal 20
external memory expansion connectors 2
External Memory Interface
Schematic Diagram 4
external oscillator frequency input 1
Index, Rev. 5
Freescale Semiconductor
Index - 1
F
M
FSRAM 1, 4
General Purpose Input and Output Port
GPIO ix
GPIO ix, 1, 13, 21
GPIO-compatible peripheral 1
MOSI 7
motor bus
over-current 1
over-voltage 1
MPIO ix
MPIO-compatible peripheral 1
Multi Purpose Input and Output Port
MPIO ix
H
O
Hall-Effect/Quadrature Encoder interface 1
Host Parallel Interface Connector 7
Host Target Interface 1, 7
external 7
On-board power regulation 2
OnCE ix
OnCE(TM) 1
On-Chip Emulation
OnCE ix
G
I
IC ix
Integrated Circuit
IC ix
J
Joint Test Action Group
JTAG ix
JTAG ix, 1
connector 7
JTAG port interface 1
Jumper Group 3
JG1 3
JG10 3
JG2 3
JG3 3
JG4 3
JG5 3
JG6 3
JG7 3
JG8 3
JG9 3
P
PCB ix
Phase Locked Loop
PLL ix
PLL ix
Printed Circuit Board
PCB ix
Program memory 4
Pulse Width Modulation
PWM ix
PWM ix
Group Interface and LEDs 14
group signals 14
LEDs 14
outputs 14
signals 14
PWM-compatible peripheral 1
Q
Quad Encoder 17
Quadrature Encoder/Hall-Effect 17
L
Logic
motor bus over-current 1
motor bus over-voltage 1
motor zero crossing 1
Low-Profile Quad Flat Pack
LQFP ix
LQFP ix
DSP56F803EVM User Manual, Rev. 5
Index - 2
Freescale Semiconductor
R
Z
RAM ix
Random Access Memory
RAM ix
Read Only Memory
ROM ix
real-time debugging 7
ROM ix
RS-232
cable connection 4
interface 5
Schematic Diagram 5
RS-232 interface 1
Zero-Crossing
circuits 17
S
SCI ix
Serial Communications Port 23
SCI-compatible peripheral 1
Serial Communications Interface
SCI ix
Serial Peripheral Interface Port
SPI ix
SPI ix
Serial Peripheral Interface 24
SPI-compatible peripheral 1
SRAM ix
external data 1
external program 1
Static Random Access Memory
SRAM ix
T
test points 25
Timer Channel 21
Timer compatible peripheral 1
U
UART ix
UNI-3
interface connector 14, 16
Motor interface 2
UNI-3 connector/interface 12
Universal Asynchronous Receiver/Transmitter
UART ix
Index, Rev. 5
Freescale Semiconductor
Index - 3
DSP56F803EVM User Manual, Rev. 5
Index - 4
Freescale Semiconductor
How to Reach Us:
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© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56F803EVMUM
Rev. 5
07/2005