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C868
On-Chip Peripheral Components
Sample Time tS :
During this time the internal capacitor array is connected to the selected analog input
channel and is loaded with the analog voltage to be converted. The analog voltage is
internally fed to a voltage comparator. With beginning of the sample phase the ADBSY
bit in SFR ADCON0 is set.
Conversion Time tCO :
During the conversion time the analog voltage is converted into a 8-bit digital value using
the successive approximation technique with a binary-weighted capacitor network. At
the end of the conversion time the ADBSY bit is reset and the IADC bit in SFR IRCON1
is set indicating an A/D converter interrupt condition.
Write Result Time tWR :
At the result phase the conversion result is written into the ADDATH registers.
A/D Conversion Timing in Relation to Processor Cycles
Depending on the application, typically there are three methods to handle the A/D
conversion in the C868.
Software delay
Using the software method, the machine cycles of the A/D conversion are counted and
the program executes a software delay (e.g. NOPs) before reading the A/D conversion
result in the write result cycle. This is the fastest method to get the result of an A/D
conversion.
Polling ADBSY bit
Using the software method, the ADBSY bit is polled and the program waits until
ADBSY=0. Attention : a polling JB instruction which is two machine cycles long, possibly
may not recognize the ADBSY=0 condition during the write result cycle in the continuous
conversion mode.
A/D conversion interrupt
Using the software or hardware methods, after the start of an A/D conversion the A/D
converter interrupt is enabled. The result of the A/D conversion is read in the interrupt
service routine. If other C868 interrupts are enabled, the interrupt latency must be
regarded. Therefore, this software method is the slowest method to get the result of an
A/D conversion.
C868
User’s Manual
4-122
V 1.0, 2003-01