Download MIPS R10000 Microprocessor User`s Manual

Introduction to the R10000 Processor
27
LL/SC
Load Linked and Store Conditional instructions are used together to implement a
memory semaphore. Each LL/SC sequence has three sections:
1.
The LL loads a word from memory.
2.
A short sequence of instructions checks or modifies this word. This sequence
must not contain any of the events listed below, or the Store Conditional will
fail:
3.
•
exception
•
execution of ERET
•
load instruction
•
store instruction
•
SYNC instruction
•
CACHE instruction
•
PREF instruction
•
external intervention exclusive or invalidate to the secondary cache
block containing the linked address
The SC stores a new value into the memory word, unless the new value has
been modified. If the word has not been modified, the store succeeds and a 1
is stored in the destination register. Otherwise the Store Conditional fails,
memory is not modified, and a 0 is loaded into the destination register. Since
the instruction format has only a single field to select a data register (rt), this
destination register is the same as the register which was stored.
Load Linked and Store Conditional instructions (LL, LLD, SC, and SCD) do not
implicitly perform SYNC operations in the R10000 processor.
MIPS R10000 Microprocessor User's Manual
Version 2.0 of October 10, 1996