Download M5249C3 User`s Manual - Freescale Semiconductor

M5249C3 Reference Board
User’s Manual
Document Number: M5249C3UM
Rev. 1
07/2006
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125
[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 26668334
[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
[email protected]
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© Freescale Semiconductor, Inc. 2006. All rights reserved.
M5249C3UM
Rev. 1
07/2006
WARNING
This board generates, uses, and can radiate radio frequency energy and, if
not installed properly, may cause interference to radio communications. As
temporarily permitted by regulation, it has not been tested for compliance
with the limits for class a computing devices pursuant to Subpart J of Part 15
of FCC rules, which are designed to provide reasonable protection against
such interference. Operation of this product in a residential area is likely to
cause interference, in which case the user, at his/her own expense, will be
required to correct the interference.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
iii
M5249C3 User’s Manual, Rev. 1
iv
Freescale Semiconductor
Chapter 1
M5249C3 Board
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
General Hardware Description ...................................................................................................... 1-1
System Memory ............................................................................................................................ 1-2
Serial Communication Channels ................................................................................................... 1-3
Parallel I/O Ports ........................................................................................................................... 1-3
Programmable Timer/Counter ....................................................................................................... 1-3
Ethernet Controller ........................................................................................................................ 1-3
System Configuration .................................................................................................................... 1-3
Installation and Setup .................................................................................................................... 1-4
1.8.1
Unpacking ..................................................................................................................... 1-5
1.8.2
Preparing the Board for Use ......................................................................................... 1-5
1.8.3
Providing Power to the Board ...................................................................................... 1-5
1.8.4
Selecting Terminal Baud Rate ...................................................................................... 1-5
1.8.5
The Terminal Character Format ................................................................................... 1-6
1.8.6
Connecting the Terminal .............................................................................................. 1-6
1.8.7
Using a Personal Computer as a Terminal ................................................................... 1-6
1.9 System Power-up and Initial Operation ........................................................................................ 1-8
1.10 M5249C3 Jumper Setup ................................................................................................................ 1-9
1.11 Using The BDM Port .................................................................................................................. 1-10
Chapter 2
Using the Monitor/Debug Firmware
2.1
2.2
2.3
2.4
2.5
What Is dBUG? ............................................................................................................................. 2-1
Operational Procedure ................................................................................................................... 2-2
2.2.1
System Power-up .......................................................................................................... 2-2
2.2.2
System Initialization ..................................................................................................... 2-3
Command Line Usage ................................................................................................................... 2-4
Commands ..................................................................................................................................... 2-5
TRAP #15 Functions ................................................................................................................... 2-38
2.5.1
OUT_CHAR ............................................................................................................... 2-38
2.5.2
IN_CHAR ................................................................................................................... 2-38
2.5.3
CHAR_PRESENT ...................................................................................................... 2-39
2.5.4
EXIT_TO_dBUG ....................................................................................................... 2-39
Chapter 3
Hardware Description and Reconfiguration
3.1
The Processor and Support Logic ................................................................................................. 3-1
3.1.1
Processor ....................................................................................................................... 3-1
3.1.2
Reset Logic ................................................................................................................... 3-1
3.1.3
HIZ Signal .................................................................................................................... 3-2
Book Title, Rev. X
Freescale Semiconductor
v
3.2
3.3
3.1.4
Clock Circuitry ............................................................................................................. 3-2
3.1.5
Watchdog Timer ........................................................................................................... 3-2
3.1.6
Interrupt Sources .......................................................................................................... 3-2
3.1.7
Internal SRAM ............................................................................................................. 3-3
3.1.8
The MCF5249 Registers and Memory Map ................................................................. 3-3
3.1.9
Reset Vector Mapping .................................................................................................. 3-4
3.1.10 TA Generation .............................................................................................................. 3-5
3.1.11 Wait State Generator ..................................................................................................... 3-5
3.1.12 SDRAM ........................................................................................................................ 3-5
3.1.13 Flash ROM ................................................................................................................... 3-5
3.1.14 JP12 Jumper and the User’s Program ........................................................................... 3-6
Serial Communication Channels ................................................................................................... 3-6
3.2.1
MCF5249 UARTs ......................................................................................................... 3-6
3.2.2
QSPI Module ................................................................................................................ 3-6
3.2.3
General Purpose I/O Pins ............................................................................................. 3-7
3.2.4
Ethernet Controller ....................................................................................................... 3-7
3.2.5
Audio Module ............................................................................................................... 3-8
3.2.6
I2C Module ................................................................................................................... 3-8
3.2.7
Analog to Digital Converter (ADC) Module ................................................................ 3-8
3.2.8
Flash Memory Card/IDE Interface Module ................................................................. 3-9
Connectors and Expansion Bus ..................................................................................................... 3-9
3.3.1
Expansion Connectors - J4 and J5 ................................................................................ 3-9
3.3.2
The Debug Connector J2 ............................................................................................ 3-11
Appendix A
Configuring dBUG for Network Downloads
A.1 Required Network Parameters ...................................................................................................... A-1
A.2 Configuring dBUG Network Parameters ...................................................................................... A-1
A.3 Troubleshooting Network Problems ............................................................................................. A-2
Appendix B
PAL Equations
Appendix C
Schematics
Appendix D
Evaluation Board BOM
Book Title, Rev. X
vi
Freescale Semiconductor
Chapter 1
M5249C3 Board
The M5249C3 is a versatile single board computer based on the MCF5249 ColdFire® processor. It may
be used as a powerful microprocessor-based controller in a variety of applications. It serves as a complete
microcomputer system for reference design, development/evaluation, training and educational use. The
user need only connect an RS-232 compatible terminal (or a personal computer with terminal emulation
software) and a power supply to have a fully functional system.
This board can be connected to external peripherals supplied by the user to expand memory and I/O
capabilities via the Expansion Bus connectors J4 & J5 (see schematic diagram). Buffers may be required
to compensate for bus loading if external peripherals are connected to the system.
1.1
General Hardware Description
The M5249C3 board provides SDRAM, Flash ROM, an Ethernet interface (10/100BaseT), and RS-232 in
addition to the built-in I/O functions of the MCF5249 device for programming and evaluating the
attributes of the microprocessor. The MCF5249 device is a member of the ColdFire® family of processors.
It is a 32-bit processor with a 24-bit address bus and 16 lines of data. The processor has eight 32-bit data
registers, eight 32-bit address registers, a 32-bit program counter, and a 16-bit status register.
The MCF5249 processor has a System Integration Module referred to as the SIM. This module
incorporates many of the functions needed for system design. These include programmable chip-select
logic, system protection logic, general purpose I/O and interrupt controller logic. The chip-select logic can
select up to four memory banks and peripherals in addition to two banks of DRAMs. The chip-select logic
also allows the insertion of a programmable number of wait-states to allow slower memory or memory
mapped peripherals to be used (refer to MCF5249 User's Manual for detailed information about the chip
selects). Two of the four chip selects are used to access devices in the system. One chip select (CS0) is
used to access the Flash ROM and the other (CS1) is used to access the Ethernet controller (U4 on the
schematics).The DRAM controller is used to control one SDRAM device providing 8MB of SDRAM
memory configured as 4MBx16 words. All other functions of the SIM are available to the user.
Figure 1-1 shows the M5249C3 block diagram.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
1-1
M5249C3 Board
(1) DB-9
ColdFire®
(1) RS232
drivers
Debug
Module
26-pin debug connector
MCF5249
OSC.
QSPI
UARTS
11.2896 MHz
(1) RS232
drivers
Addr
[24:1]
(1) DB-9
Data
[31:16]
SDRAM
Expansion Connector#2
Expansion Connector#1
16bit 3.3V
25MHz
Oscillator
.
QSPI
CS0
CS1
Flash
16 bit,3.3v
2MB
SMSC LAN91C111
10/100 Mb/sec
.
RJ45 Connector
Figure 1-1. M5249C3 Block Diagram
1.2
System Memory
One on-board Flash ROM (U6) is used in the system. The Am29LV160DB-XX device contains 16Mbits
of non-volatile storage (1 MByte x 16) giving a total of 2MBytes of Flash memory. The lower 256 KBytes
are used to store the M5249C3 dBUG debugger/monitor firmware.
The MCF5249 processor has 96KBytes of internal SRAM organized as 1 bank of 64Kbytes and 1 bank of
32KBytes. The SRAM can be used for either data or instruction space.
M5249C3 User’s Manual, Rev. 1
1-2
Freescale Semiconductor
M5249C3 Board
There is one SDRAM (U7) device on the PCB. The system ships with 1x 4M x 16 of SDRAM totalling
8MBytes of volatile memory.
The internal cache of the MCF5249 is non-blocking. The instruction cache is 8 KBytes with a 16-byte line
size. The ROM Monitor currently does not utilize the cache, but programs downloaded with the ROM
Monitor can initialise and use the cache.
1.3
Serial Communication Channels
The MCF5249 processor has 2 built-in UARTs (UART0 and UART1) with independent baud rate
generators. The signals of both channels pass through external Driver/Receivers to make the channels
RS-232 compatible. An RS-232 serial cable with DB9 connectors is included with the board. The signals
of both channels are available on the 120 pin expansion connector (J5). UART0 channel is the
“TERMINAL” channel used by dBUG for communication with an external terminal/PC. The
“TERMINAL” baud rate defaults to 19200.
1.4
Parallel I/O Ports
The MCF5249 offers 47-lines of general-purpose I/O of which 11 are dedicated inputs and 10 are
dedicated outputs. Eight of the GPIO lines are also available as edge sensitive interrupt inputs.
1.5
Programmable Timer/Counter
The MCF5249 has two built-in general purpose timers/counters and a software watchdog timer. All timers
are available to the user. The signals for each timer are available on the 120 pin expansion connector (J5).
1.6
Ethernet Controller
The M5249C3 PCB has an Ethernet controller (SMSC LAN91C111 U4) operating at 10M bits/sec or
100Mbits/sec. The dBUG ROM monitor is programmed to allow a user to download files over a network
to memory in different formats. The compiler formats currently supported are S-Record, COFF, ELF, or
Image (raw binary). Refer to Appenix A for details on how to configure the board for network download.
1.7
System Configuration
The M5249C3 board requires the following items for minimum system configuration:
• The M5249C3 board (provided).
• Power supply, +7V to 14V DC with minimum of 1.0 Amp.
• RS232C compatible terminal or a PC with terminal emulation software.
• RS232 Communication cable (provided).
Refer to Section 2.2.2, “System Initialization,” for initial system setup.
Figure 1-2 displays the minimum system configuration.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
1-3
M5249C3 Board
dBUG>
+7.0 to +14VDC
Input Power
R S- 232 T erm inal
O r PC
Figure 1-2. Minimum System Configuration
1.8
Installation and Setup
The following sections describe all the steps needed to prepare the board for operation. Please read the
following sections carefully before using the board. When you are preparing the board for the first time,
be sure to check that all jumpers are in the default locations. Default jumper markings are documented on
the master jumper table and printed on the underside of the board (see Table 1-2). After the board is
M5249C3 User’s Manual, Rev. 1
1-4
Freescale Semiconductor
M5249C3 Board
functional in its default mode, the Ethernet interface may be used by following the instructions provided
in Appendix A, “Configuring dBUG for Network Downloads.”
1.8.1
Unpacking
Unpack the computer board from its shipping box. Save the box for storing or reshipping. Refer to the
following list and verify that all the items are present. You should have received:
• M5249C3 Single Board Computer
• M5249C3 User's Manual (this document)
• One RS232 communication cable
• One BDM (Background Debug Mode) “wiggler” cable
• MCF5249UM ColdFire Integrated Microprocessor User Manual
• ColdFire® Programmers Reference Manual
• A selection of Third Party Developer Tools and Literature
NOTE
Avoid touching the MOS devices. Static discharge can and will damage
these devices.
Once you have verified that all the items are present, remove the board from its protective jacket and
anti-static bag. Check the board for any visible damage. Ensure that there are no broken, damaged, or
missing parts. If you have not received all the items listed above or they are damaged, please contact Rapid
PCB immediately; for contact details please see the front of this manual.
1.8.2
Preparing the Board for Use
The board, as shipped, is ready to be connected to a terminal and power supply without any need for
modification. Figure 1-4 shows the position of the jumpers and connectors.
1.8.3
Providing Power to the Board
The board accepts three means of power supply connection, either P1, P2 or J11. Connector P1 is a 2.1mm
power jack, P2 a lever actuated connector and J11 is a PC disk drive type power connector. The board
accepts +7V to +14V DC at 1.0 Amp via either of the connectors.
Table 1-1. Power Supply Connections on P2
Contact Number
1.8.4
Voltage
1
+7V to +14V DC
2
Ground
Selecting Terminal Baud Rate
The serial channel UART0 of the MCF5249 is used for serial communication and has a built in timer. This
timer is used by the dBUG ROM monitor to generate the baud rate used to communicate with a serial
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
1-5
M5249C3 Board
terminal. A number of baud rates can be programmed. On power-up or manual RESET, the dBUG ROM
monitor firmware configures the channel for 19200 baud. Once the dBUG ROM monitor is running, a SET
command may be issued to select any baud rate supported by the ROM monitor. Refer to Chapter 2,
“Using the Monitor/Debug Firmware,” for the discussion of this command.
1.8.5
The Terminal Character Format
The character format of the communication channel is fixed at power-up or RESET. The default character
format is 8 bits per character, no parity and one stop bit with no flow control. It is neccessary to ensure
that the terminal or PC is set to this format.
1.8.6
Connecting the Terminal
The board is now ready to be connected to a PC/terminal. Use the RS232 serial cable to connect the
PC/terminal to the M5249C3 PCB. The cable has a 9-pin female D-sub terminal connector at one end and
a 9-pin male D-sub connector at the other end. Connect the 9-pin male connector to connector P3 on the
M5249C3 board. Connect the 9-pin female connector to one of the available serial communication
channels normally referred to as COM1 (COM2, etc.) on the PC running terminal emulation software. The
connector on the PC/terminal may be either male 25-pin or 9-pin. It may be neccessary to obtain a
25pin-to-9pin adapter to make this connection. If an adapter is required, refer to Figure 1-3 which shows
the pin assignment for the 9-pin connector on the board.
1.8.7
Using a Personal Computer as a Terminal
A personal computer may be used as a terminal provided a terminal emulation software package is
available. Examples of this software are PROCOMM, KERMIT, QMODEM, Windows 95/98/2000 Hyper
Terminal or similar packages. The board should then be connected as described in Section 1.8.6,
“Connecting the Terminal.”
Once the connection to the PC is made, power may be applied to the PC and the terminal emulation
software can be run. In terminal mode, it is neccessary to select the baud rate and character format for the
channel. Most terminal emulation software packages provide a command known as "Alt-p" (press the p
key while pressing the Alt key) to choose the baud rate and character format. The character format should
be 8 bits, no parity, one stop bit. (See Section 1.8.5, “The Terminal Character Format”) The baud rate
should be set to 19200. Power can now be applied to the board.
5
1
9
6
Figure 1-3. Pin assignment for female (Terminal) connector
Pin assignments are as follows.
1. Data Carrier Detect, Output (shorted to pins 4 and 6).
2. Receive Data, Output from board (receive refers to terminal side).
M5249C3 User’s Manual, Rev. 1
1-6
Freescale Semiconductor
M5249C3 Board
3.
4.
5.
6.
7.
8.
9.
Transmit Data, Input to board (transmit refers to terminal side).
Data Terminal Ready, Input (shorted to pin 1 and 6).
Signal Ground.
Data Set Ready, Output (shorted to pins 1 and 4).
Request to Send, Input.
Clear to send, Output.
Not connected.
Figure 1-4 on the next page shows the jumper locations for the board.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
1-7
M5249C3 Board
Figure 1-4. Jumper Locations
1.9
System Power-up and Initial Operation
When all of the cables are connected to the board, power may be applied. The dBUG ROM Monitor
initialises the board and then displays a power-up message on the terminal, which includes the amount of
memory present on the board.
Hard Reset
DRAM Size: 8M
M5249C3 User’s Manual, Rev. 1
1-8
Freescale Semiconductor
M5249C3 Board
Copyright 1995-2002 Motorola, Inc. All Rights Reserved.
ColdFire MCF5249 EVS Firmware v2e.1a.xx (Build XXX on XXX
xx:xx:xx)
Enter 'help' for help.
XX 20XX
dBUG>
The board is now ready for operation under the control of the debugger as described in Chapter 2, “Using
the Monitor/Debug Firmware.” If you do not get the above response, perform the following checks:
1. Make sure that the power supply is properly configured for polarity, voltage level and current
capability (~1A) and is connected to the board.
2. Check that the terminal and board are set for the same character format and baud.
3. Press the RESET button to insure that the board has been initialized properly.
If you still are not receiving the proper response, your board may have been damaged. Contact Rapid PCB
for further instructions; please see the beginning of this manual for contact details.
1.10
M5249C3 Jumper Setup
Jumper settings are as follows:
NOTE
‘*’ is used to indicate that default setting.
‘**’ is used to indicate mandatory setting for proper operation.
Table 1-2. Jumper Settings
Jumper Setting
JP1
Function
* 1-2
Audio DAC AK4360VF U1 De-emphasis on
2-3
Audio DAC AK4360VF U1 De-emphasis off
* 1-2
Audio DAC AK4360VF U1 Boost -high pass correction on
2-3
Audio DAC AK4360VF U1 Boost - high pass correction off
*1-2
Audio DAC AK4360VF U1 Clock sample rate = 384fs
2-3
Audio DAC AK4360VF U1 Clock sample rate = 256fs
*1-2
Audio DAC AK4360VF U1 Audio format I2S 16/18/20 bit
2-3
Audio DAC AK4360VF U1 Audio format 16-bit LSB justified
JP5
1-2
Not connected - I2C channel 0 pull-up SDA0, MCF5249 U2
JP6
1-2
Not connected - I2C channel 0 pull-up SCL0, MCF5249 U2
JP7
*1-2
BDM mode selected at power-on/reset (POR)
2-3
JTAG mode selected at power-on/reset (POR)
JP8
*1-2
Current measurement for the CPU core +1.8V
JP9
*1-2
Current measurement for the CPU I/O pads +3.3V
JP10
*1-2
BDM connector (J2) I/O or Pad voltage +3.3V
JP2
JP3
JP4
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
1-9
M5249C3 Board
Table 1-2. Jumper Settings (continued)
Jumper Setting
2-3
BDM connector (J2) I/O or Pad voltage +1.8V
*1-2
BDM connector (J2) Core voltage +3.3V
2-3
BDM connector (J2) Core voltage +1.8V
**1-2
Flash EEPROM (U6) - boot into dBUG ROM monitor at
power-on/reset (POR)
2-3
Flash EEPROM (U6) - boot into Flash ignoring first 256K
sector at POR
JP13
*1-2
Audio DAC AK4360VF U1 left audio channel load
JP14
*1-2
Audio DAC AK4360VF U1 right audio channel load
JP15
*1-2
Routes CS1 from U2 (MCF5249) to PAL U5 and hence to
Ethernet controller U4. Removed this isolates CS1 signal for
use with the expansion connectors (J4 & J5)
JP11
JP12
1.11
Function
Using The BDM Port
The MCF5249 microprocessor has a built in debug module referred to as BDM (background debug
module). In order to use BDM, simply connect the 26-pin debug connector on the board, J2, to the P&E
BDM wiggler cable provided in the kit. No special setting is needed. Refer to the ColdFire® User's Manual
BDM Section for additional instructions.
NOTE
BDM functionality and use is supported via third party developer software
tools. Details may be found on CD-ROM included in this kit.
M5249C3 User’s Manual, Rev. 1
1-10
Freescale Semiconductor
Chapter 2
Using the Monitor/Debug Firmware
The M5249C3 single board computer has a resident firmware package that provides a self-contained
programming and operating environment. The firmware, named dBUG, provides the user with
monitor/debug interface, inline assembler and disassembly, program download, register and memory
manipulation, and I/O control functions. This chapter is a how-to-use description of the dBUG package,
including the user interface and command structure.
2.1
What Is dBUG?
dBUG is a traditional ROM monitor/debugger that offers a comfortable and intuitive command line
interface that can be used to download and execute code. It contains all the primary features needed in a
debugger to create a useful debugging environment.
dBUG is a resident firmware package for the ColdFire family single board computers. The firmware
(stored in one 1Mx16 Flash ROM device) provides a self-contained programming and operating
environment. dBUG interacts with the user through pre-defined commands that are entered via the
terminal. These commands are defined in Section 2.4, “Commands.”
The user interface to dBUG is the command line. A number of features have been implemented to achieve
an easy and intuitive command line interface.
dBUG assumes that an 80x24 character dumb-terminal is utilized to connect to the debugger. For serial
communications, dBUG requires eight data bits, no parity, and one stop bit, 8N1 with no flow control. The
default baud rate is 19200 but can be changed after the power-up.
The command line prompt is “dBUG> “. Any dBUG command may be entered from this prompt. dBUG
does not allow command lines to exceed 80 characters. Wherever possible, dBUG displays data in 80
columns or less. dBUG echoes each character as it is typed, eliminating the need for any “local echo” on
the terminal side.
In general, dBUG is not case sensitive. Commands may be entered either in upper or lower case,
depending upon the user’s equipment and preference. Only symbol names require that the exact case be
used.
Most commands can be recognized by using an abbreviated name. For instance, entering “h” is the same
as entering “help”. Thus, it is not necessary to type the entire command name.
The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. dBUG recognizes
this and allows for repeated execution of these commands with minimal typing. After a command is
entered, simply press <RETURN> or <ENTER> to invoke the command again. The command is executed
as if no command line parameters were provided.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-1
Using the Monitor/Debug Firmware
An additional function called the "TRAP 15 handler" allows the user program to utilize various routines
within dBUG. The TRAP 15 handler is discussed at the end of this chapter.
The operational mode of dBUG is demonstrated in Figure 2-1. After the system initialization, the board
waits for a command-line input from the user terminal. When a proper command is entered, the operation
continues in one of the two basic modes. If the command causes execution of the user program, the dBUG
firmware may or may not be re-entered, at the discretion of the user’s program. For the alternate case, the
command will be executed under control of the dBUG firmware, and after command completion, the
system returns to command entry mode.
During command execution, additional user input may be required depending on the command function.
For commands that accept an optional <width> to modify the memory access size, the valid values are:
• B 8-bit (byte) access
• W 16-bit (word) access
• L 32-bit (long) access
When no <width> option is provided, the default width is .W, 16-bit.
The core ColdFire register set is maintained by dBUG. These are listed below:
• A0-A7
• D0-D7
• PC
• SR
All control registers on ColdFire are not readable by the supervisor-programming model, and thus not
accessible via dBUG. User code may change these registers, but caution must be exercised as changes may
render dBUG inoperable.
A reference to “SP” (stack pointer) actually refers to general purpose address register seven, “A7."
2.2
Operational Procedure
System power-up and initial operation are described in detail in Chapter 1, “M5249C3 Board.” This
information is repeated here for convenience and to prevent possible damage.
2.2.1
•
•
•
System Power-up
Be sure the power supply is connected properly prior to power-up.
Make sure the terminal is connected to TERMINAL (P4) connector.
Turn power on to the board.
Figur 2-1 shows the dUBG operational mode.
M5249C3 User’s Manual, Rev. 1
2-2
Freescale Semiconductor
Using the Monitor/Debug Firmware
Initialize
Command Line
Input From Terminal
No
Execute
Command
Function
Yes
No
Does Command Line
Cause User Program
Execution
Yes
Jump To User
Program And
Begin Execution
Figure 2-1. Flow Diagram of dBUG Operational Mode
2.2.2
System Initialization
The act of powering up the board will initialize the system. The processor is reset and dBUG is invoked.
dBUG performs the following configurations of internal resources during the initialization. The
instruction cache is invalidated and disabled. The Vector Base Register, VBR, points to the Flash.
However, a copy of the exception table is made at address $00000000 in SDRAM. To take over an
exception vector, the user places the address of the exception handler in the appropriate vector in the vector
table located at 0x00000000, and then points the VBR to 0x00000000.
The Software Watchdog Timer is disabled and internal timers are placed in a stop condition. Interrupt
controller registers initialized with unique interrupt level/priority pairs. Please refer to the dBUG source
files on the ColdFire website (http://www.freescale.com/coldfire) for the complete initialization code
sequence.
After initialization, the terminal will display:
Hard Reset
DRAM Size: 8M
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-3
Using the Monitor/Debug Firmware
Copyright 1995-2002 Motorola, Inc. All Rights Reserved.
ColdFire MCF5249 EVS Firmware v2e.1a.1a (Build XXX on XXX)
Enter 'help' for help.
dBUG>
If you did not get this response check the setup, refer to Section 1.9, “System Power-up and Initial
Operation.”
Other means can be used to re-initialize the M5249C3 Computer Board firmware. These means are
discussed in the following paragraphs.
2.2.2.1
Hard RESET Button
Hard RESET (S1) is the red button. Depressing this button causes all processes to terminate, resets the
MCF5249 processor and board logic and restarts the dBUG firmware. Pressing the RESET button would
be the appropriate action if all else fails.
2.2.2.2
ABORT Button
ABORT (S2) is the button located next to the RESET button. The abort function causes an interrupt of the
present processing (a level 7 interrupt on MCF5249) and gives control to the dBUG firmware. This action
differs from RESET in that no processor register or memory contents are changed, the processor and
peripherals are not reset, and dBUG is not restarted. Also, in response to depressing the ABORT button,
the contents of the MCF5249 core internal registers are displayed.
The abort function is most appropriate when software is being debugged. The user can interrupt the
processor without destroying the present state of the system. This is accomplished by forcing a
non-maskable interrupt that will call a dBUG routine that will save the current state of the registers to
shadow registers in the monitor for display to the user. The user will be returned to the ROM monitor
prompt after exception handling.
2.2.2.3
Software Reset Command
dBUG does have a command that causes the dBUG to restart as if a hardware reset was invoked. The
command is "RESET".
2.3
Command Line Usage
The user interface to dBUG is the command line. A number of features have been implemented to achieve
an easy and intuitive command line interface.
dBUG assumes that an 80x24 ASCII character dumb terminal is used to connect to the debugger. For serial
communications, dBUG requires eight data bits, no parity, and one stop bit (8N1). The baud rate default
is 19200 bps — a speed commonly available from workstations, personal computers and dedicated
terminals.
The command line prompt is: dBUG>
M5249C3 User’s Manual, Rev. 1
2-4
Freescale Semiconductor
Using the Monitor/Debug Firmware
Any dBUG command may be entered from this prompt. dBUG does not allow command lines to exceed
80 characters. Wherever possible, dBUG displays data in 80 columns or less. dBUG echoes each character
as it is typed, eliminating the need for any local echo on the terminal side.
The <Backspace> and <Delete> keys are recognized as rub-out keys for correcting typographical
mistakes.
Command lines may be recalled using the <Control> U, <Control> D and <Control> R key sequences.
<Control> U and <Control> D cycle up and down through previous command lines. <Control> R recalls
and executes the last command line.
In general, dBUG is not case-sensitive. Commands may be entered either in uppercase or lowercase,
depending upon the user’s equipment and preference. Only symbol names require that the exact case be
used.
Most commands can be recognized by using an abbreviated name. For instance, entering h is the same as
entering help. Thus it is not necessary to type the entire command name.
The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. dBUG recognizes
this and allows for repeated execution of these commands with minimal typing. After a command is
entered, press the <Return> or <Enter> key to invoke the command again. The command is executed as if
no command line parameters were provided.
2.4
Commands
This section lists the commands that are available with all versions of dBUG. Some board or CPU
combinations may use additional commands not listed below.
Table 2-1. dBUG Command Summary
Mnemonic
Syntax
Description
ASM
asm <<addr> stmt>
Assemble
BC
bc addr1 addr2 length
Block Compare
BF
bf <width> begin end data <inc>
Block Fill
BM
bm begin end dest
Block Move
BR
br addr <-r> <-c count> <-t trigger>
Breakpoint
BS
bs <width> begin end data
Block Search
DC
dc value
Data Convert
DI
di<addr>
Disassemble
DL
dl <offset>
Download Serial
DN
dn <-c> <-e> <-i> <-s <-o offset>> <filename>
Download Network
GO
go <addr>
Execute
GT
gt addr
Execute To
HELP
help <command>
Help
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-5
Using the Monitor/Debug Firmware
Table 2-1. dBUG Command Summary (continued)
Mnemonic
Syntax
Description
ASM
asm <<addr> stmt>
Assemble
BC
bc addr1 addr2 length
Block Compare
BF
bf <width> begin end data <inc>
Block Fill
IRD
ird <module.register>
Internal Register Display
IRM
irm module.register data
Internal Register Modify
LR
lr<width> addr
Loop Read
LW
lw<width> addr data
Loop Write
MD
md<width> <begin> <end>
Memory Display
MM
mm<width> addr <data>
Memory Modify
MMAP
mmap
Memory Map Display
RD
rd <reg>
Register Display
RM
rm reg data
Register Modify
RESET
reset
Reset
SD
sd
Stack Dump
SET
set <option value>
Set Configurations
SHOW
show <option>
Show Configurations
STEP
step
Step (Over)
SYMBOL
symbol <symb> <-a symb value> <-r symb> -C|l|s> Symbol Management
TRACE
trace <num>
Trace (Into)
UPDBUG
updbug
Update dBUG
UPUSER
upuser <bytes>
Update User Flash
VERSION
version
Show Version
M5249C3 User’s Manual, Rev. 1
2-6
Freescale Semiconductor
Using the Monitor/Debug Firmware
ASM
Assembler
Usage:
ASM <<addr> stmt>
The ASM command is a primitive assembler. The <stmt> is assembled and the resulting code placed at
<addr>. This command has an interactive and non-interactive mode of operation.
The value for address <addr> may be an absolute address specified as a hexadecimal value, or a symbol
name. The value for stmt must be valid assembler mnemonics for the CPU.
For the interactive mode, the user enters the command and the optional <addr>. If the address is not
specified, then the last address is used. The memory contents at the address are disassembled, and the user
prompted for the new assembly. If valid, the new assembly is placed into memory, and the address
incremented accordingly. If the assembly is not valid, then memory is not modified, and an error message
produced. In either case, memory is disassembled and the process repeats.
The user may press the <Enter> or <Return> key to accept the current memory contents and skip to the
next instruction, or a enter period to quit the interactive mode.
In the non-interactive mode, the user specifies the address and the assembly statement on the command
line. The statement is the assembled, and if valid, placed into memory, otherwise an error message is
produced.
Examples:
To place a NOP instruction at address 0x00010000, the command is:
asm
10000 nop
To interactively assembly memory at address 0x00400000, the command is:
asm
400000
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-7
Using the Monitor/Debug Firmware
BC
Block Compare
Usage:
BC addr1 addr2 length
The BC command compares two contiguous blocks of memory on a byte by byte basis. The first block
starts at address addr1 and the second starts at address addr2, both of length bytes.
If the blocks are not identical, the address of the first mismatch is displayed. The value for addresses addr1
and addr2 may be an absolute address specified as a hexadecimal value or a symbol name. The value for
length may be a symbol name or a number converted according to the user defined radix (hexadecimal by
default).
Example:
To verify that the data starting at 0x20000 and ending at 0x30000 is identical to the data starting at
0x80000, the command is:
bc
20000 80000 10000
M5249C3 User’s Manual, Rev. 1
2-8
Freescale Semiconductor
Using the Monitor/Debug Firmware
BF
Block Fill
Usage:BF<width> begin end data <inc>
The BF command fills a contiguous block of memory starting at address begin, stopping at address end,
with the value data. <Width> modifies the size of the data that is written. If no <width> is specified, the
default of word sized data is used.
The value for addresses begin and end may be an absolute address specified as a hexadecimal value, or a
symbol name. The value for data may be a symbol name, or a number converted according to the
user-defined radix, normally hexadecimal.
The optional value <inc> can be used to increment (or decrement) the data value during the fill.
This command first aligns the starting address for the data access size, and then increments the address
accordingly during the operation. Thus, for the duration of the operation, this command performs
properly-aligned memory accesses.
Examples:
To fill a memory block starting at 0x00020000 and ending at 0x00040000 with the value 0x1234, the
command is:
bf
20000 40000 1234
To fill a block of memory starting at 0x00020000 and ending at 0x0004000 with a byte value of 0xAB, the
command is:
bf.b
20000 40000 AB
To zero out the BSS section of the target code (defined by the symbols bss_start and bss_end), the
command is:
bf
bss_start bss_end 0
To fill a block of memory starting at 0x00020000 and ending at 0x00040000 with data that increments by
2 for each <width>, the command is:
bf
20000 40000 0 2
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-9
Using the Monitor/Debug Firmware
BM
Block Move
Usage:
BM begin end dest
The BM command moves a contiguous block of memory starting at address begin and stopping at address
end to the new address dest. The BM command copies memory as a series of bytes, and does not alter the
original block.
The values for addresses begin, end, and dest may be absolute addresses specified as hexadecimal values,
or symbol names. If the destination address overlaps the block defined by begin and end, an error message
is produced and the command exits.
Examples:
To copy a block of memory starting at 0x00040000 and ending at 0x00080000 to the location 0x00200000,
the command is:
bm
40000 80000 200000
To copy the target code’s data section (defined by the symbols data_start and data_end) to 0x00200000,
the command is:
bm
data_start data_end 200000
NOTE
Refer to “upuser” command for copying code/data into Flash memory.
M5249C3 User’s Manual, Rev. 1
2-10
Freescale Semiconductor
Using the Monitor/Debug Firmware
BR
Breakpoints
Usage:BR addr <-r> <-c count> <-t trigger>
The BR command inserts or removes breakpoints at address addr. The value for addr may be an absolute
address specified as a hexadecimal value, or a symbol name. Count and trigger are numbers converted
according to the user-defined radix, normally hexadecimal.
If no argument is provided to the BR command, a listing of all defined breakpoints is displayed.
The -r option to the BR command removes a breakpoint defined at address addr. If no address is specified
in conjunction with the -r option, then all breakpoints are removed.
Each time a breakpoint is encountered during the execution of target code, its count value is incremented
by one. By default, the initial count value for a breakpoint is zero, but the -c option allows setting the initial
count for the breakpoint.
Each time a breakpoint is encountered during the execution of target code, the count value is compared
against the trigger value. If the count value is equal to or greater than the trigger value, a breakpoint is
encountered and control returned to dBUG. By default, the initial trigger value for a breakpoint is one, but
the -t option allows setting the initial trigger for the breakpoint.
If no address is specified in conjunction with the -c or -t options, then all breakpoints are initialized to the
values specified by the -c or -t option.
Examples:
To set a breakpoint at the C function main() (symbol _main; see “symbol” command), the command is:
br
_main
When the target code is executed and the processor reaches main(), control will be returned to dBUG.
To set a breakpoint at the C function bench() and set its trigger value to 3, the command is:
br
_bench -t 3
When the target code is executed, the processor must attempt to execute the function bench() a third time
before returning control back to dBUG.
To remove all breakpoints, the command is:
br
-r
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-11
Using the Monitor/Debug Firmware
BS
Block Search
Usage:
BS<width> begin end data
The BS command searches a contiguous block of memory starting at address begin, stopping at address
end, for the value data. <Width> modifies the size of the data that is compared during the search. If no
<width> is specified, the default of word sized data is used.
The values for addresses begin and end may be absolute addresses specified as hexadecimal values, or
symbol names. The value for data may be a symbol name or a number converted according to the
user-defined radix, normally hexadecimal.
This command first aligns the starting address for the data access size, and then increments the address
accordingly during the operation. Thus, for the duration of the operation, this command performs
properly-aligned memory accesses.
Examples:
To search for the 16-bit value 0x1234 in the memory block starting at 0x00040000 and ending at
0x00080000:
bs
40000 80000 1234
This reads the 16-bit word located at 0x00040000 and compares it against the 16-bit value 0x1234. If no
match is found, then the address is incremented to 0x00040002 and the next 16-bit value is read and
compared.
To search for the 32-bit value 0xABCD in the memory block starting at 0x00040000 and ending at
0x00080000:
bs.l
40000 80000 ABCD
This reads the 32-bit word located at 0x00040000 and compares it against the 32-bit value 0x0000ABCD.
If no match is found, then the address is incremented to 0x00040004 and the next 32-bit value is read and
compared.
M5249C3 User’s Manual, Rev. 1
2-12
Freescale Semiconductor
Using the Monitor/Debug Firmware
DC
Data Conversion
Usage:
DC data
The DC command displays the hexadecimal or decimal value data in hexadecimal, binary, and decimal
notation.
The value for data may be a symbol name or an absolute value. If an absolute value passed into the DC
command is prefixed by ‘0x’, then data is interpreted as a hexadecimal value. Otherwise data is interpreted
as a decimal value.
All values are treated as 32-bit quantities.
Examples:
To display the decimal and binary equivalent of 0x1234, the command is:
dc
0x1234
To display the hexadecimal and binary equivalent of 1234, the command is:
dc
1234
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-13
Using the Monitor/Debug Firmware
DI
Disassemble
Usage:
DI <addr>
The DI command disassembles target code pointed to by addr. The value for addr may be an absolute
address specified as a hexadecimal value, or a symbol name.
Wherever possible, the disassembler will use information from the symbol table to produce a more
meaningful disassembly. This is especially useful for branch target addresses and subroutine calls.
The DI command attempts to track the address of the last disassembled opcode. If no address is provided
to the DI command, then the DI command uses the address of the last opcode that was disassembled.
The DI command is repeatable.
Examples:
To disassemble code that starts at 0x00040000, the command is:
di
40000
To disassemble code of the C function main(), the command is:
di
_main
M5249C3 User’s Manual, Rev. 1
2-14
Freescale Semiconductor
Using the Monitor/Debug Firmware
DL
Download Console
Usage:
DL <offset>
The DL command performs an S-record download of data obtained from the console, typically a serial
port. The value for offset is converted according to the user-defined radix, normally hexadecimal. Please
reference the ColdFire Microprocessor Family Programmer’s Reference Manual for details on the
S-Record format.
If offset is provided, then the destination address of each S-record is adjusted by offset.
The DL command checks the destination download address for validity. If the destination is an address
outside the defined user space, then an error message is displayed and downloading aborted.
If the S-record file contains the entry point address, then the program counter is set to reflect this address.
Examples:
To download an S-record file through the serial port, the command is:
dl
To download an S-record file through the serial port, and add an offset to the destination address of 0x40,
the command is:
dl
0x40
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-15
Using the Monitor/Debug Firmware
DN
Download Network
Usage:
DN <-c> <-e> <-i> <-s> <-o offset> <filename>
The DN command downloads code from the network. The DN command handle files which are either
S-record, COFF, ELF or Image formats. The DN command uses Trivial File Transfer Protocol (TFTP) to
transfer files from a network host.
In general, the type of file to be downloaded and the name of the file must be specified to the DN
command. The -c option indicates a COFF download, the -e option indicates an ELF download, the -i
option indicates an Image download, and the -s indicates an S-record download. The -o option works only
in conjunction with the -s option to indicate an optional offset for S-record download. The filename is
passed directly to the TFTP server and therefore must be a valid filename on the server.
If neither of the -c, -e, -i, -s or filename options are specified, then a default filename and filetype will be
used. Default filename and filetype parameters are manipulated using the SET and SHOW commands.
The DN command checks the destination download address for validity. If the destination is an address
outside the defined user space, then an error message is displayed and downloading aborted.
For ELF and COFF files which contain symbolic debug information, the symbol tables are extracted from
the file during download and used by dBUG. Only global symbols are kept in dBUG. The dBUG symbol
table is not cleared prior to downloading, so it is the user’s responsibility to clear the symbol table as
necessary prior to downloading.
If an entry point address is specified in the S-record, COFF or ELF file, the program counter is set
accordingly.
Examples:
To download an S-record file with the name “srec.out”, the command is:
dn -s srec.out
To download a COFF file with the name “coff.out”, the command is:
dn -c coff.out
To download a file using the default filetype with the name “bench.out”, the command is:
dn bench.out
To download a file using the default filename and filetype, the command is:
dn
M5249C3 User’s Manual, Rev. 1
2-16
Freescale Semiconductor
Using the Monitor/Debug Firmware
GO
Execute
Usage:
GO <addr>
The GO command executes target code starting at address addr. The value for addr may be an absolute
address specified as a hexadecimal value, or a symbol name.
If no argument is provided, the GO command begins executing instructions at the current program counter.
When the GO command is executed, all user-defined breakpoints are inserted into the target code, and the
context is switched to the target program. Control is only regained when the target code encounters a
breakpoint, illegal instruction, trap #15 exception, or other exception which causes control to be handed
back to dBUG.
The GO command is repeatable.
Examples:
To execute code at the current program counter, the command is:
go
To execute code at the C function main(), the command is:
go _main
To execute code at the address 0x00040000, the command is:
go 40000
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-17
Using the Monitor/Debug Firmware
GT
Execute To
Usage:
GT addr
The GT command inserts a temporary breakpoint at addr and then executes target code starting at the
current program counter. The value for addr may be an absolute address specified as a hexadecimal value,
or a symbol name.
When the GT command is executed, all breakpoints are inserted into the target code, and the context is
switched to the target program. Control is only regained when the target code encounters a breakpoint,
illegal instruction, or other exception which causes control to be handed back to dBUG.
Examples:
To execute code up to the C function bench(), the command is:
gt _bench
M5249C3 User’s Manual, Rev. 1
2-18
Freescale Semiconductor
Using the Monitor/Debug Firmware
IRD
Internal Register Display
Usage:
IRD <module.register>
This command displays the internal registers of different modules inside the MCF5xxx. In the command
line, module refers to the module name where the register is located and register refers to the specific
register to display.
The registers are organized according to the module to which they belong. The available modules on the
MCF5xxx are CS, DMA0, DMA1, DMA2, DMA3, DRAMC, PP, MBUS, SIM, TIMER1, TIMER2,
UART0 and UART1. Refer to the MCF5407 user’s manual for more information on these modules and the
registers they contain.
Example:
ird
sim.rsr
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-19
Using the Monitor/Debug Firmware
IRM
Usage:
Internal Register Modify
IRM module.register data
This command modifies the contents of the internal registers of different modules inside the MCF5xxx. In
the command line, module refers to the module name where the register is located and register refers to
the specific register to modify. The data parameter specifies the new value to be written into the register.
The registers are organized according to the module to which they belong. The available modules on the
MCF5xxx are CS, DMA0, DMA1, DMA2, DMA3, DRAMC, PP, MBUS, SIM, TIMER1, TIMER2,
UART0 and UART1. Refer to the MCF5407 user’s manual for more information on these modules and the
registers they contain.
Example:
To modify the TMR register of the first Timer module to the value 0x0021, the command is:
irm
timer1.tmr 0021
M5249C3 User’s Manual, Rev. 1
2-20
Freescale Semiconductor
Using the Monitor/Debug Firmware
HELP
Usage:
Help
HELP <command>
The HELP command displays a brief syntax of the commands available within dBUG. In addition, the
address of where user code may start is given. If command is provided, then a brief listing of the syntax of
the specified command is displayed.
Examples:
To obtain a listing of all the commands available within dBUG, the command is:
help
To obtain help on the breakpoint command, the command is:
help br
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-21
Using the Monitor/Debug Firmware
LR
Loop Read
Usage:
LR<width> addr
The LR command continually reads the data at addr until a key is pressed. The optional <width> specifies
the size of the data to be read. If no <width> is specified, the command defaults to reading word sized data.
Example:
To continually read the longword data from address 0x20000, the command is:
lr.l
20000
M5249C3 User’s Manual, Rev. 1
2-22
Freescale Semiconductor
Using the Monitor/Debug Firmware
LW
Loop Write
Usage:
LW<width> addr data
The LW command continually writes data to addr. The optional width specifies the size of the access to
memory. The default access size is a word.
Examples:
To continually write the longword data 0x12345678 to address 0x20000, the command is:
lw.l
20000 12345678
Note that the following command writes 0x78 into memory:
lw.b
20000 12345678
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-23
Using the Monitor/Debug Firmware
MD
Memory Display
Usage: MD<width> <begin> <end>
The MD command displays a contiguous block of memory starting at address begin and stopping at
address end. The values for addresses begin and end may be absolute addresses specified as hexadecimal
values, or symbol names. Width modifies the size of the data that is displayed. If no <width> is specified,
the default of word sized data is used.
Memory display starts at the address begin. If no beginning address is provided, the MD command uses
the last address that was displayed. If no ending address is provided, then MD will display memory up to
an address that is 128 beyond the starting address.
This command first aligns the starting address for the data access size, and then increments the address
accordingly during the operation. Thus, for the duration of the operation, this command performs
properly-aligned memory accesses.
Examples:
To display memory at address 0x00400000, the command is:
md 400000
To display memory in the data section (defined by the symbols data_start and data_end), the command is:
md data_start
To display a range of bytes from 0x00040000 to 0x00050000, the command is:
md.b
40000 50000
To display a range of 32-bit values starting at 0x00040000 and ending at 0x00050000:
md.l
40000 50000
M5249C3 User’s Manual, Rev. 1
2-24
Freescale Semiconductor
Using the Monitor/Debug Firmware
MM
Memory Modify
Usage:
MM<width> addr <data>
The MM command modifies memory at the address addr. The value for addr may be an absolute address
specified as a hexadecimal value, or a symbol name. Width specifies the size of the data that is modified.
If no <width> is specified, the default of word sized data is used. The value for data may be a symbol name,
or a number converted according to the user-defined radix, normally hexadecimal.
If a value for data is provided, then the MM command immediately sets the contents of addr to data. If no
value for data is provided, then the MM command enters into a loop. The loop obtains a value for data,
sets the contents of the current address to data, increments the address according to the data size, and
repeats. The loop terminates when an invalid entry for the data value is entered, i.e., a period.
This command first aligns the starting address for the data access size, and then increments the address
accordingly during the operation. Thus, for the duration of the operation, this command performs
properly-aligned memory accesses.
Examples:
To set the byte at location 0x00010000 to be 0xFF, the command is:
mm.b
10000 FF
To interactively modify memory beginning at 0x00010000, the command is:
mm
10000
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-25
Using the Monitor/Debug Firmware
MMAP
Usage:
Memory Map Display
mmap
This command displays the memory map information for the M5249C3 evaluation board. The information
displayed includes the type of memory, the start and end address of the memory, and the port size of the
memory. The display also includes information on how the Chip-selects are used on the board.
Here is an example of the output from this command:
Type
Start
End
Port Size
----------------------------------------------------------------------SDRAM
0x00000000
0x003FFFFF
32-bit
Vector Table
0x00000000
0x000003FF
32-bit
USER SPACE
0x00020000
0x003FFFFF
32-bit
MBAR
0x10000000
0x100003FF
32-bit
Internal SRAM
0x20000000
0x20000FFF
32-bit
External SRAM
0x30000000
0x3007FFFF
32-bit
Flash
0xFFE00000
0xFFFFFFFF
16-bit
Chip Selects
-----------------------------CS0
Flash
CS1
Ethernet controller
CS2
not in use
CS3
not in use
M5249C3 User’s Manual, Rev. 1
2-26
Freescale Semiconductor
Using the Monitor/Debug Firmware
RD
Register Display
Usage:
RD <reg>
The RD command displays the register set of the target. If no argument for reg is provided, then all
registers are displayed. Otherwise, the value for reg is displayed.
dBUG preserves the registers by storing a copy of the register set in a buffer. The RD command displays
register values from the register buffer.
Examples:
To display all the registers and their values, the command is:
rd
To display only the program counter:
rd
pc
Here is an example of the output from this command:
PC: 00000000 SR: 2000 [t.Sm.000...xnzvc]
An: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000
Dn: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-27
Using the Monitor/Debug Firmware
RM
Register Modify
Usage:
RM reg data
The RM command modifies the contents of the register reg to data. The value for reg is the name of the
register, and the value for data may be a symbol name, or it is converted according to the user-defined
radix, normally hexadecimal.
dBUG preserves the registers by storing a copy of the register set in a buffer. The RM command updates
the copy of the register in the buffer. The actual value will not be written to the register until target code is
executed.
Examples:
To change register D0 on MC68000 and ColdFire to contain the value 0x1234, the command is:
rm
D0 1234
M5249C3 User’s Manual, Rev. 1
2-28
Freescale Semiconductor
Using the Monitor/Debug Firmware
RESET
Usage:
Reset the Board and dBUG
RESET
The RESET command resets the board and dBUG to their initial power-on states.
The RESET command executes the same sequence of code that occurs at power-on. If the RESET
command fails to reset the board adequately, cycle the power or press the reset button.
Examples:
To reset the board and clear the dBUG data structures, the command is:
reset
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-29
Using the Monitor/Debug Firmware
SET
Set Configurations
Usage:
SET <option value>
The SET command allows the setting of user-configurable options within dBUG. With no arguments, SET
displays the options and values available. The SHOW command displays the settings in the appropriate
format. The standard set of options is listed below.
• baud - This is the baud rate for the first serial port on the board. All communications between
dBUG and the user occur using either 9600 or 19200 bps, eight data bits, no parity, and one stop
bit, 8N1, with no flow control.
• base - This is the default radix for use in converting a number from its ASCII text representation
to the internal quantity used by dBUG. The default is hexadecimal (base 16), and other choices are
binary (base 2), octal (base 8), and decimal (base 10).
• client - This is the network Internet Protocol (IP) address of the board. For network
communications, the client IP is required to be set to a unique value, usually assigned by your local
network administrator.
• server - This is the network IP address of the machine which contains files accessible via TFTP.
Your local network administrator will have this information and can assist in properly configuring
a TFTP server if one does not exist.
• gateway - This is the network IP address of the gateway for your local subnetwork. If the client IP
address and server IP address are not on the same subnetwork, then this option must be properly
set. Your local network administrator will have this information.
• netmask - This is the network address mask to determine if use of a gateway is required. This field
must be properly set. Your local network administrator will have this information.
• filename - This is the default filename to be used for network download if no name is provided to
the DN command.
• filetype - This is the default file type to be used for network download if no type is provided to the
DN command. Valid values are: “srecord”, “coff”, and “elf”.
• mac - This is the ethernet Media Access Control (MAC) address (a.k.a hardware address) for the
evaluation board. This should be set to a unique value, and the most significant nibble should
always be even.
Examples:
To set the baud rate of the board to be 19200, the command is:
set
baud 19200
NOTE
See the SHOW command for a display containing the correct formatting of
these options.
M5249C3 User’s Manual, Rev. 1
2-30
Freescale Semiconductor
Using the Monitor/Debug Firmware
SHOW
Usage:
Show Configurations
SHOW <option>
The SHOW command displays the settings of the user-configurable options within dBUG. When no option
is provided, SHOW displays all options and values.
Examples:
To display all options and settings, the command is:
show
To display the current baud rate of the board, the command is:
show
baud
Here is an example of the output from a show command:
dBUG> show
base: 16
baud: 19200
server: 192.0.0.1
client: 192.0.0.2
gateway: 0.0.0.0
netmask: 255.255.255.0
filename: test.srec
filetype: S-Record
mac: 00:CF:52:49:C3:01
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-31
Using the Monitor/Debug Firmware
STEP
Step Over
Usage:
STEP
The STEP command can be used to “step over” a subroutine call, rather than tracing every instruction in
the subroutine. The ST command sets a temporary breakpoint one instruction beyond the current program
counter and then executes the target code.
The STEP command can be used to “step over” BSR and JSR instructions.
The STEP command will work for other instructions as well, but note that if the STEP command is used
with an instruction that will not return, i.e. BRA, then the temporary breakpoint may never be encountered
and dBUG may never regain control.
Examples:
To pass over a subroutine call, the command is:
step
M5249C3 User’s Manual, Rev. 1
2-32
Freescale Semiconductor
Using the Monitor/Debug Firmware
SYMBOL
Symbol Name Management
Usage:SYMBOL <symb> <-a symb value> <-r symb> <-c|l|s>
The SYMBOL command adds or removes symbol names from the symbol table. If only a symbol name is
provided to the SYMBOL command, then the symbol table is searched for a match on the symbol name
and its information displayed.
The -a option adds a symbol name and its value into the symbol table. The -r option removes a symbol
name from the table.
The -c option clears the entire symbol table, the -l option lists the contents of the symbol table, and the -s
option displays usage information for the symbol table.
Symbol names contained in the symbol table are truncated to 31 characters. Any symbol table lookups,
either by the SYMBOL command or by the disassembler, will only use the first 31 characters. Symbol
names are case-sensitive.
Symbols can also be added to the symbol table via in-line assembly labels and ethernet downloads of ELF
formatted files.
Examples:
To define the symbol “main” to have the value 0x00040000, the command is:
symbol
-a main 40000
To remove the symbol “junk” from the table, the command is:
symbol
-r junk
To see how full the symbol table is, the command is:
symbol
-s
To display the symbol table, the command is:
symbol
-l
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-33
Using the Monitor/Debug Firmware
TRACE
Usage:
Trace Into
TRACE <num>
The TRACE command allows single-instruction execution. If num is provided, then num instructions are
executed before control is handed back to dBUG. The value for num is a decimal number.
The TRACE command sets bits in the processors’ supervisor registers to achieve single-instruction
execution, and the target code executed. Control returns to dBUG after a single-instruction execution of
the target code.
This command is repeatable.
Examples:
To trace one instruction at the program counter, the command is:
tr
To trace 20 instructions from the program counter, the command is:
tr
20
M5249C3 User’s Manual, Rev. 1
2-34
Freescale Semiconductor
Using the Monitor/Debug Firmware
UPDBUG
Usage:
Update dBUG
updbug
The updbug command is used to update the dBUG image in Flash. When updates to the M5249C3 dBUG
are available, the updated image is downloaded to address 0x00020000. The new image is placed into
Flash using the UPDBUG command. The user is prompted for verification before performing the
operation. Use this command with extreme caution, as any error can render dBUG useless!
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-35
Using the Monitor/Debug Firmware
UPUSER
Usage:
Update User Flash
UPUSER <bytes>
The UPUSER command places user code and data into space allocated for the user in Flash. The optional
parameter bytes specifies the number of bytes to copy into the user portion of Flash.If the bytes parameter
is omitted, then this command writes to the entire user space. There are seven sectors of 256K each
available as user space. Users access this memory starting at address 0xFFE40000.
Examples:
To program all 7 sectors of user Flash, the command is:
upuser
To program only 1000 bytes into user Flash, the command is:
upuser 1000
M5249C3 User’s Manual, Rev. 1
2-36
Freescale Semiconductor
Using the Monitor/Debug Firmware
VERSION
Usage:
Display dBUG Version
VERSION
The VERSION command displays the version information for dBUG. The dBUG version, build number
and build date are all given.
The version number is separated by a decimal, for example, “v 2b.1c.1a”.
dBUG common
major and minor
revision
{
{
{
In this example, v 2b . 1c . 1a
CPU major
and minor
revision
board major
and minor
revision
The version date is the day and time at which the entire dBUG monitor was compiled and built.
Examples:
To display the version of the dBUG monitor, the command is:
version
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-37
Using the Monitor/Debug Firmware
2.5
TRAP #15 Functions
An additional utility within the dBUG firmware is a function called the TRAP 15 handler. This function
can be called by the user program to utilize various routines within the dBUG, to perform a special task,
and to return control to the dBUG. This section describes the TRAP 15 handler and how it is used.
There are four TRAP #15 functions. These are: OUT_CHAR, IN_CHAR, CHAR_PRESENT, and
EXIT_TO_dBUG.
2.5.1
OUT_CHAR
This function ( function code 0x0013) sends a character, which is in lower 8 bits of D1, to terminal.
Assembly example:
/* assume d1 contains the character */
move.l
#$0013,d0
Selects the function
TRAP
#15
The character in d1 is sent to terminal
C example:
void board_out_char (int ch)
{
/* If your C compiler produces a LINK/UNLK pair for this routine,
* then use the following code which takes this into account
*/
#if l
/* LINK a6,#0 -- produced by C compiler */
asm (“ move.l8(a6),d1”);
/* put ‘ch’into d1 */
asm (“ move.l#0x0013,d0”); /* select the function */
asm (“ trap#15”);
/* make the call */
/* UNLK a6 -- produced by C compiler */
#else
/* If C compiler does not produce a LINK/UNLK pair, the use
* the following code.
*/
asm (“ move.l4(sp),d1”);
/* put ‘ch’into d1 */
asm (“ move.l#0x0013,d0”); /* select the function */
asm (“ trap#15”);
/* make the call */
#endif
}
2.5.2
IN_CHAR
This function (function code 0x0010) returns an input character (from terminal) to the caller. The returned
character is in D1.
Assembly example:
move.l
trap
#$0010,d0
#15
Select the function
Make the call, the input character is in d1.
C example:
int board_in_char (void)
{
asm (“ move.l#0x0010,d0”);
/* select the function */
M5249C3 User’s Manual, Rev. 1
2-38
Freescale Semiconductor
Using the Monitor/Debug Firmware
asm (“ trap#15”);
asm (“ move.ld1,d0”);
/* make the call */
/* put the character in d0 */
}
2.5.3
CHAR_PRESENT
This function (function code 0x0014) checks if an input character is present to receive. A value of zero is
returned in D0 when no character is present. A non-zero value in D0 means a character is present.
Assembly example:
move.l
trap
#$0014,d0
Select the function
#15
Make the call, d0 contains the response (yes/no).
C example:
int board_char_present (void)
{
asm (“ move.l#0x0014,d0”);
asm (“ trap#15”);
}
2.5.4
/* select the function */
/* make the call */
EXIT_TO_dBUG
This function (function code 0x0000) transfers the control back to the dBUG, by terminating the user code.
The register context are preserved.
Assembly example:
move.l
trap
#$0000,d0
#15
Select the function
Make the call, exit to dBUG.
C example:
void board_exit_to_dbug (void)
{
asm (“ move.l#0x0000,d0”);
asm (“ trap#15”);
}
/* select the function */
/* exit and transfer to dBUG */
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
2-39
Using the Monitor/Debug Firmware
M5249C3 User’s Manual, Rev. 1
2-40
Freescale Semiconductor
Chapter 3
Hardware Description and Reconfiguration
This chapter provides a functional description of the M5249C3 board hardware. With the description
given here and the schematic diagrams in Appendix C, “Schematics,” the user can gain a good
understanding of the board's design. In this manual, an active low signal is indicated by a bar over the
signal name.
3.1
The Processor and Support Logic
This part of the chapter discusses the CPU and general support logic on the M5249C3 board.
3.1.1
Processor
The microprocessor used on the M5249C3 is the highly integrated ColdFire MCF5249, 32-bit processor.
The MCF5249 implements a ColdFire Version 2 core with 8-KByte instruction cache, two UART
channels, two timers, 96-KBytes of SRAM, a QSPI (Queued Serial Peripheral Interface) module, an I2C
module, 4x I2S modules, an IDE module, a Flash memory stick interface, 64 parallel I/O ports (which are
multiplexed with other signals) and the system integration module (SIM). All of the core processor
registers are 32 bits wide except for the Status Register (SR) which is 16 bits wide. This processor
communicates with external devices over a 16-bit wide data bus, D[31:16]. The chip can address
64-MBytes of memory space using a 25-bit wide address bus and internal chip-select logic. All the
processor's signals are available through the expansion connectors (J4 and J5). Refer to Section 3.3.1,
“Expansion Connectors - J4 and J5,” for their pin assignments.
The MCF5249 processor has the capability to support both an IEEE JTAG-compatible port and a BDM
debug port. These ports are multiplexed and can be used with third party tools to allow the user to
download code to the board. The board is configured to boot up in the normal/BDM mode of operation.
The BDM signals are available at port (J2). The processor also has the logic to generate up to four (4) chip
selects, CS0 to CS3, and support for 2 banks of SDRAM (included on the evaluation board as 8-Mbytes
in total configured as 4Mx16). The SDRAM_CS1 signal is used to provide selection and control of this
bank of SDRAM.
3.1.2
Reset Logic
The reset logic provides system initialisation. Reset occurs during power-on or via assertion of the signal
RESET which causes the MCF5249 to reset. Reset is also triggered by the reset switch (S1) which resets
the entire processor/system.
A hard reset and voltage sense controller (U9) is used to produce an active low power-on RESET signal.
The reset switch S1 is fed into U9 which generates the signal which is fed to the MCF5249 reset, RESET.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
3-1
Hardware Description and Reconfiguration
The RESET signal is an open collector signal and so can be wire OR’ed with other reset signals from
additional peripherals.
dBUG configures the MCF5249 microprocessor internal resources during initialization. The instruction
cache is invalidated and disabled. The Vector Base Register, VBR, contains an address which initially
points to the Flash memory. The contents of the exception table are written to address $00000000 in the
SDRAM. The Software Watchdog Timer is disabled, the Bus Monitor is enabled, and the internal timers
are placed in a stop condition. The interrupt controller registers are initialised with unique interrupt
level/priority pairs. A memory map for the entire board can be seen in Table 3-1.
3.1.3
HIZ Signal
The assertion of the HIZ signal forces all output drivers to a high-impedance state. On the M5249C3 board
the high impedance signal is pulled to +3.3V via a 4.7K pull-up resistor, ensuring that the output drivers
will not be in a high-impedance state during reset. HIZ is also available to the user on connector (J5).
3.1.4
Clock Circuitry
The M5249C3 board uses a 11.2896MHz crystal (X1 on the schematics) to provide the clock to the clock
driver chip (U10). The clock driver provides a buffered clock for the MCF5249 processor (U2). In addition
to the 11.2896MHz crystal, there is also a 25MHz oscillator (U3) which feeds the Ethernet chip (U4).
3.1.5
Watchdog Timer
The duration of the Watchdog is selected by the SWT[1:0] bits in the System Protection and Control
Register (SYPCR), SWT[1:0] = 11 gives a maximum timeout period of 228/System frequency. The dBUG
monitor initialises these bits with the value 0x11, which provides the maximum time-out period, but dBUG
does NOT enable the watchdog timer via the SYPCR register SWE bit.
3.1.6
Interrupt Sources
The ColdFire family of processors can receive seven levels of interrupt priorities. When the processor
receives an interrupt which has a higher priority than the current interrupt mask (in the status register), it
will perform an interrupt acknowledge cycle at the end of the current instruction cycle. This interrupt
acknowledge cycle indicates to the source of the interrupt that the request is being acknowledged and the
device should provide the proper vector number to indicate where the service routine for this interrupt level
is located. If the source of interrupt is not capable of providing a vector, its interrupt should be set up as
an autovector interrupt which directs the processor to a predefined entry in the exception table (refer to the
MCF5249 User's Manual).
The processor goes to an exception routine via the exception table. This table is stored in the Flash
EEPROM. The address of the table location is stored in the VBR. The dBUG ROM monitor writes a copy
of the exception table into the RAM starting at $00000000. To set an exception vector, the user places the
address of the exception handler in the appropriate vector in the vector table located at $00000000 and then
points the VBR to $00000000.
M5249C3 User’s Manual, Rev. 1
3-2
Freescale Semiconductor
Hardware Description and Reconfiguration
The MCF5249 microprocessor has eight external interrupt request lines INT[7:0], all of which are
multiplexed with other functions. The interrupt controller is capable of providing up to 32 interrupt
sources. These sources are:
• External interrupt signals INT[7:0]
• Software watchdog timer module
• Two general purpose timer modules
• UART module
• I2C module
• Audio interface modules
• DMA module
• QSPI module
All external interrupt inputs are edge sensitive. The active level is programmable. An interrupt request
must be held valid until an IACK cycle starts to guarantee correct processing. Each interrupt input can have
it’s priority programmed by setting the xIPL[2:0] bits in the Interrupt Control Registers.
NOTE
No interrupt sources should have the same level and priority as another.
Programming two interrupt sources with the same level and priority can
result in undefined operation.
The M5249C3 hardware uses INT7 to support the ABORT function using the ABORT switch (S2). This
switch is used to force an interrupt (level 7, priority 3) if the user's program execution should be aborted
without issuing a RESET (refer to Chapter 2, “Using the Monitor/Debug Firmware,” for more information
on ABORT). Since the ABORT switch is not capable of generating a vector in response to a level seven
interrupt acknowledge from the processor, the dBUG programs this interrupt request for autovector mode.
Refer to MCF5249 User’s Manual for more information about the interrupt controller.
3.1.7
Internal SRAM
The MCF5249 processor has 96-KBtyes of internal memory which may be programmed as data or
instruction memory. This memory is mapped to 0x20000000 and configured as data space but is not used
by the dBUG monitor except during system initialisation. After system initialisation is complete, the
internal memory is available to the user. The memory is relocatable to any 32-KByte boundary.
3.1.8
The MCF5249 Registers and Memory Map
The memory and I/O resources of the M5249C3 hardware are divided into two groups, MCF5249 internal
and external resources. All the I/O registers are memory mapped.
The MCF5249 processor has built in logic and up to four chip-select pins (CS[3:0]) which are used to
enable external memory and I/O devices. In addition there are SDRAS and SDCAS lines available for
controlling SDRAMs. There are registers to specify the address range, type of access and the method of
TA generation for each chip-select. These registers are programmed by the dBUG monitor to map the
external memory and I/O devices.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
3-3
Hardware Description and Reconfiguration
The M5249C3 uses the following signals to select external peripherals:
• CS0 to enable the Flash ROM (refer to Section 3.1.13, “Flash ROM”)
• SDRAS, SDCAS and SDRAM_CS1 to enable the SDRAM (refer to Section 3.1.12, “SDRAM”)
• CS1 for the Ethernet controller
The chip select mechanism of the MCF5249 processor allows the memory mapping to be defined for the
required memory space (User/Supervisor, Program/Data spaces).
All of the MCF5249 internal registers, configuration registers, parallel I/O port registers, UART registers
and system control registers are mapped by the MBAR register at any 1-KByte boundary. The MBAR1
register is mapped to 0x1000_0000 and MBAR2 mapped to 0x8000_0000 by the dBUG monitor. For a
complete map of these registers refer to the MCF5249 User's Manual.
The M5249C3 board has 8-MBytes of SDRAM installed. Refer to Section 3.1.12, “SDRAM,” for a
discussion of the SDRAM on the board. The dBUG ROM monitor is programmed in one AMD
Am29LV160DB-90 Flash ROM which occupies 2-MBytes of the address space. The first 256-KBytes, i.e
the first sector, are used by ROM Monitor and the remainder is left for the user. Refer to Section 3.1.13,
“Flash ROM.”
Table 3-1 shows the M5249C3 memory map.
Table 3-1. M5249C3 Memory Map
Address Range
$0000_0000 – $0002_0000
Signal and Device
SDRAM space for dBug ROM monitor use
Memory Access Time
Refer to manufacturer spec.
$0002_0000 – $007F_FFFF SDRAM space
Refer to manufacturer spec.
$1000_0000 – $1000_03FF System Integration Module (SIM) registers
Internal access
$1000_0000 – $1000_0054
Refer to MCF5249UM SIM section
MBAR—Module Base Addres Reg.
$2000_0000 – $2000_FFFF SRAM1
Internal access (1 cycle)
$2001_0000 – $2001_7FFF SRAM0
Internal access (1 cycle)
$3000_0000 – $3007_FFFF CS1, External Ethernet controller
8-7-7-7
$8000_0000 – $BFFF_FFFF MBAR2—Module Base Address Reg. 2
Refer to MCF5249UM SIM section
$FFE0_0000 – $FFFF_FFFF CS0, 2M Flash ROM
8-7-7-7
All of the unused area of the memory map is available to the user.
3.1.9
Reset Vector Mapping
After reset, the processor attempts to read the initial stack pointer and program counter values from
locations $00000000 & $00000004 (the first eight bytes of memory space). This requires the board to have
a non-volatile memory device in this range with the correct information stored in it. In some systems,
however, it is preferred to have RAM starting at address $00000000. The MCF5249 processor chip-select
zero (CS0) responds to any accesses after reset until the CSMR0 is written. Since CS0 (the global chip
select) is connected to the Flash ROM (U6), the Flash ROM initially appears at address $00000000 which
provides the initial stack pointer and program counter (the first eight bytes of the Flash ROM). The
M5249C3 User’s Manual, Rev. 1
3-4
Freescale Semiconductor
Hardware Description and Reconfiguration
initialisation routine then programs the chip-select logic, locates the Flash ROM to start at $FFE00000
and configures the rest of the internal and external peripherals.
3.1.10
TA Generation
The processor starts a bus cycle by asserting CSx with the other control signals. The processor then waits
for a transfer acknowledgment (TA) either from within (Auto acknowledge - AA mode) or from the
externally addressed device before it can complete the bus cycle. TA is used to indicate the completion of
the bus cycle. It also allows devices with different access times to communicate with the processor
properly (i.e. asynchronously) like the Ethernet controller (U4). The MCF5249 processor, as part of the
chip-select logic, has a built-in mechanism to generate TA for all external devices which do not have the
capability to generate this signal. For example the Flash ROM cannot generate a TA.signal. The chip-select
logic is programmed by the dBUG ROM Monitor to generate TA internally after a pre-programmed
number of wait states. In order to support future expansion of the M5249C3 board, the TA input of the
processor is also connected to the Processor Expansion Bus (J5, pin 66). This allows any expansion boards
to assert this line to provide a TA signal to the processor. On the expansion boards this signal should be
generated through an open collector buffer with no pull-up resistor; a pull-up resistor is included on this
board. All TA signals from expansion boards should be connected to this line.
3.1.11
Wait State Generator
The Flash ROM and SDRAM on the board may require some adjustments to the cycle time of the
processor to make them compatible with the processor’s external bus speed. To extend the CPU bus cycles
for the slower devices, the chip-select logic of the MCF5249 processor can be programmed to generate an
internal TA after a given number of wait states. Refer to Table 3-1 for information about the address space
of the memory and refer to the manufacturers specification for wait state requirements of the SDRAM and
Flash ROM.
3.1.12
SDRAM
The M5249C3 has one 64-MBit device on the board, in a 16-bit wide data bus configuration. The
MCF5249 processor supports one bank of SDRAM, which on this board is represented by SDRAM
device, (U7). These are connected to the MCF5249 to provide 4Mx16 of memory.
3.1.13
Flash ROM
There is one 2-MByte Flash ROM on the M5249C3, (U6).
The board is shipped with one AMD Am29LV160DB, 2-MByte Flash ROM. The first 256-Kbytes of the
Flash contains the ROM Monitor firmware dBUG. The remaining Flash memory is available to the user
via use of jumper 12.
The MCF5249 chip-select logic can be programmed to generate the TA for CS0 signal after a certain
number of wait states (i.e. auto acknowledge mode). The dBUG monitor programs this parameter to be
six wait-states.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
3-5
Hardware Description and Reconfiguration
3.1.14
JP12 Jumper and the User’s Program
Jumper 12 allows users to test code from boot/POR without having to overwrite the ROM Monitor.
When the jumper is set between pins 1 and 2, the behavior of the system is normal, dBUG boots and then
runs from 0xFFE00000. When the jumper is set between pins 2 and 3, the board boots from the second
half of the Flash (0xFFF00000).
Procedure:
1. Compile and link as though the code was to be placed at the base of the flash, but setup so that it
will download to the SDRAM starting at address 0xE0000. The user should refer to their compiler
documentation for this, since it will depend upon the compiler used.
2. Set up the jumper (JP12) for Normal operation, pin1 connected to pin 2.
3. Download to SDRAM (If using serial or ethernet, start the ROM Monitor first. If using BDM via
a wiggler cable, download first, then start ROM Monitor by pointing the program counter (PC) to
0x7FE00400 and run.)
4. In the ROM Monitor, execute the 'upuser' command.
5. Move jumper (JP12) to pin 2 connected to pin 3 and push the reset button (S1). User code should
now be running from reset/POR.
3.2
Serial Communication Channels
The M5249C3 offers two serial communications channels. They are discussed in this section.
3.2.1
MCF5249 UARTs
The MCF5249 device has two built in UARTs, each with its own software programmable baud rate
generators. One channel is the ROM Monitor to Terminal output and the other is available to the user. The
ROM Monitor programs the interrupt level for UART0 to Level 3, priority 2 and autovector mode of
operation. The interrupt level for UART1 is programmed to Level 3, priority 1 and autovector mode of
operation. The signals from these channels are available on expansion connector (J5). The signals of
UART0 and UART1 are also passed through the RS-232 driver/receivers (U13) & (U14) and are available
on DB-9 connectors (P3) and (P4). Refer to the MCF5249 User’s Manual for programming the UART’s
and their register maps.
3.2.2
QSPI Module
The QSPI (Queued Serial Peripheral Interface) module provides a serial peripheral interface with queued
transfer capability. It will support up to 16 stacked transfers at one time, minimising CPU intervention
between transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers.
Functionality is very similar, but not identical, to the QSPI portion of the QSM (Queued Serial Module)
implemented in the MC68332 processor.
• Programmable queue to support up to 16 transfers without user intervention
• Supports transfer sizes of 8 to 16 bits in 1-bit increments
M5249C3 User’s Manual, Rev. 1
3-6
Freescale Semiconductor
Hardware Description and Reconfiguration
•
•
•
•
•
Four peripheral chip-select lines for control of up to 15 devices
Baud rates from 274.5-Kbps to 17.5-Mbps at 140MHz.
Programmable delays before and after transfers
Programmable clock phase and polarity
Supports wrap-around mode for continuous transfers
Please see the MCF5249 Users Manual for more detail. The QSPI signals from the MCF5249 device are
brought out to expansion connector (J4). Some of these signals are multiplexed with other functions.
3.2.3
General Purpose I/O Pins
The MCF5249 offers 64-bits of general-purpose I/O of which 11 are dedicated general purpose inputs and
10 are dedicated general purpose outputs. Eight of the GPIO lines are also available as edge sensitive
interrupt inputs. The functions of all I/O pins are individually programmable, since they are multiplexed
with other pin functions. All general-purpose I/O pins (unless dedicated as either only input or output) can
be individually selected as input or output pins. After reset, all software configurable multi-function GPIO
pins default to general purpose input pins. At the same time, all multifunction pins that are not shared with
a GPIO pin default to high impedance. Internal pullup resistors avoid unknown read values in order to
reduce power consumption. They remain active until the corresponding port direction registers are
programmed.
Control registers are provided for each pin to select the function (GPIO or peripheral pin) assigned to each
pin individually. Pins can have from 1 to 4 functions including GPIO.
Please see the MCF5249 User’s manual for more detail. All of these signals are brought out to expansion
connectors (J4) & (J5).
3.2.4
Ethernet Controller
The MCF5249 device has an Ethernet controller, SMSC LAN91C111, memory mapped into the address
space using CS1. The Ethernet controller performs both the MAC & PHY functions and allows 10BaseT
or 100BaseT operation. This controller is clocked from a standalone 25MHz oscillator independent of the
CPU clock. The interface between the MCF5249 and the SMSC LAN91C111 is therefore asynchronous.
The Fast Ethernet controller (FEC) incorporates the following features:
• Full integration and compliance with the IEEE 802.3/802.3u 100Base-TX/10Base-T physical layer
standards
• Dual speed - 10/100Mbps
• 8Kbytes of internal Rx & Tx FIFO buffers
• Burst transfers are supported
• Single 25MHz operation for both the MAC & PHY
• On-chip wave shaping
• On-chip adaptive equaliser
• Baseline wander correction
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
3-7
Hardware Description and Reconfiguration
For more details see the LAN91C111 Users manual at http://www.smsc.com.
The on board ROM MONITOR is programmed to allow a user to download files from a network to
memory in different formats. The current compiler formats supported are S-Record, COFF, ELF or Image.
3.2.5
Audio Module
The MCF5249 processor’s audio module includes the following features:
• Support for reception and transmission of digital audio over serial interfaces IIS/EIAJ and digital
interface IEC958
• 4x IIS/EIAJ interfaces
• 2x IEC958 receivers (4x multiplexed inputs)
• 1x IEC958 transmitter - two outputs - one with professional subcoding, one with consumer
subcoding
• Allows direct transmission of received audio to an audio transmitter without CPU intervention.
• IEC958 receivers and transmitter support main audio, plus handling of IEC958 C, U and V
sub-channels
• Frequency measurement block - precise measurement of the incoming sample frequency
All the Audio signals are brought out to expansion connectors (J4) & (J5). For further details please refer
to the MCF5249 User’s manual.
3.2.6
I2C Module
The MCF5249 processor’s I2C module includes the following features:
• Compatibility with the I2C bus standard
• Multimaster operation
• Software programmable for one of 64 different clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte by byte data transfer
• Arbitration-lost interrupt with auto mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation and detection
• Repeated start signal generation
• Acknowledge bit generation and detection
• Bus busy detection
3.2.7
Analog to Digital Converter (ADC) Module
The MCF5249 processor’s ADC module includes the following features:
• Sigma-Delta based ADC with 12-bit resolution
M5249C3 User’s Manual, Rev. 1
3-8
Freescale Semiconductor
Hardware Description and Reconfiguration
•
Four multiplexed inputs - EBUIN3_ADIN0_GPI38, EBUIN4_ADIN1_GPI39,
RXD2_ADIN2_GPI28 and CTS2_ADIN3_GPI31
The digital portion of the ADC is on-chip, an analog comparator must be sourced externally
Single output - TOUT1_ADOUT_GPO35, provides the reference voltage which requires an
external comparator (resistor/capacitor circuit).
Software interrupt provided when the ADC measurement is complete
•
•
•
3.2.8
Flash Memory Card/IDE Interface Module
The MCF5249 processor’s Flash Memory Card/IDE module includes the following features:
• TBA
3.3
Connectors and Expansion Bus
There are 2 expansion connectors on the M5249C3 (J4 and J5) which are used to connect the board to
external I/O devices and/or expansion boards.
3.3.1
Expansion Connectors - J4 and J5
Table 3-2 shows pin assignments for the (J4) connector.
Table 3-2. J4 Connector Pin Assignment
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
+1.8V
2
+1.8V
61
CS1
62
A22
3
+1.8V
4
GND
63
NC
64
A23
5
NC
6
A1
65
SCL0/QSPICLK
66
GND
7
NC
8
A2
67
GND
68
A24
9
GND
10
A3
69
SDA0/QSPIDIN
70
NC
11
CS0
12
+1.8V
71
BCLKE
72
CMDSDIO2/GPIO34
13
NC
14
A4
73
BCLK
74
+3.3V
15
+3.3V
16
A5
75
+3.3V
76
NC
17
D16
18
A6
77
SDUDQM
78
SCLKOUT/GPIO15
19
D17
20
GND
79
SDRAS
80
EF/GPIO19
21
GND
22
A7
81
SDRAM_CS1
82
GND
23
D18
24
A8
83
GND
84
SDATA0_SDI01/GPIO54
25
D19
26
+3.3V
85
SDWE
86
SDATA_BS2/RSTO
27
+3.3V
28
A9
87
SDCAS
88
BUFENB1/GPIO57
29
D20
30
A10
89
SDLDQM
90
+3.3V
31
D21
32
A11
91
+3.3V
92
SDATA1_BS1/GPIO9
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
3-9
Hardware Description and Reconfiguration
Table 3-2. J4 Connector Pin Assignment (continued)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
33
D22
34
GND
93
SDATA3/GPIO56
94
QSPI_CS0/GPIO29
35
GND
36
A12
95
+5V
96
QSPI_CS1/GPIO24
37
D23
38
A13
97
GND
98
GND
39
D24
40
A14
99
SDRAM_CS2
100
QSPI_DOUT/GPIO26
41
D25
42
+3.3V
101
GPIO5
102
QSPI_CS2/GPIO21
43
+3.3V
44
A15
103
GPIO6
104
QSPI_CS3/GPIO22
45
D26
46
A16
105
+3.3V
106
+1.8V
47
D27
48
A17
107
GND
108
GND
49
D28
50
GND
109
GND
110
GND
51
GND
52
A18
111
+1.8V
112
+1.8V
53
D29
54
A19
113
+5V
114
+5V
55
D30
56
A20
115
+5V
116
+5V
57
D31
58
+3.3V
117
GND
118
GND
59
+3.3V
60
A21
119
GND
120
GND
Table 3-3 shows the pin assignments of the J5 connector.
Table 3-3. J5 Connector pin assignment
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
+1.8V
2
+1.8V
61
R/W
62
GND
3
GND
4
GND
63
XTRIM/GPO38
64
GND
5
TXD0/GPO27
6
DDATA0
65
CL11/GPO39
66
TA
7
RXD0/GPI27
8
DDATA1
67
GND
68
RESET
9
LRCK3/GPIO45
10
+3.3V
69
BUFENB2/GPIO17
70
+1.8V
11
+1.8V
12
DDATA2
71
CRIN
72
SDATAI1
13
SRE/GPIO11
14
DDATA3
73
SCLK4/GPIO50
74
GND
15
TA_IN
16
PST0
75
+3.3V
76
SDATAI3/GPI41
17
RXD1/GPI28
18
GND
77
SCLK1
78
+1.8V
19
GND
20
PST1
79
SDATAO1/GPIO25
80
SDATAI4/GPI42
21
SCLK3/GPIO49
22
PST2
81
LRCK1
82
GND
23
RTS0/GPO30
24
PST3
83
GND
84
LRCK4/GPIO46
25
TXD1/GPO28
26
+1.8V
85
SDATAO2
86
+3.3V
27
+3.3V
28
DSO
87
LRCK2/GPIO44
88
TIN1/GPIO23
29
RTS1/GPO31
30
DSI
89
SCL1/GPIO3
90
EBUIN1/GPI36
M5249C3 User’s Manual, Rev. 1
3-10
Freescale Semiconductor
Hardware Description and Reconfiguration
Table 3-3. J5 Connector pin assignment (continued)
3.3.2
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
31
TOUT0/GPO33
32
GND
91
+3.3V
92
EBUIN2/GPI37
33
NC
34
DSCLK
93
OE
94
EBUIN3/GPI38
35
GND
36
BKPT
95
SDA1/GPIO55
96
GND
37
SWE/GPIO12
38
+3.3V
97
TOUT1/GPO35
98
SCLK2/GPIO48
39
NC
40
EBUIN4/GPI39
99
GND
100
CL16/GPO42
41
PSTCLK
42
CTS0/GPI30
101
EBUOUT2/GPO37
102
NC
43
+1.8V
44
GND
103
CFLG/GPIO18
104
NC
45
SFSY/GPIO52
46
CTS1/GPI31
105
GND
106
+1.8V
47
RCK/GPIO51
48
GND
107
+1.8V
108
+1.8V
49
SUBR/GPIO53
50
+1.8V
109
+3.3V
110
+3.3V
51
GND
52
TIN0/GPI33
111
EBUOUT1/GPO36
112
NC
53
IDEDIOL/GPIO13
54
GND
113
+5V
114
+5V
55
IDEIORDY/GPIO16
56
HI-Z
115
+5V
116
+5V
57
IDEDIOW/GPIO14
58
TCK
117
GND
118
GND
59
+3.3V
60
+1.8V
119
GND
120
GND
The Debug Connector J2
The MCF5249 processor has a Background Debug Mode (BDM) port, which supports Real-Time Trace
Support and Real-Time Debug. The signals which are neccessary for debug are available at connector (J2).
Figure 3-1 shows the (J2) Connector pin assignment.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
3-11
Hardware Description and Reconfiguration
BKPT
Developer Reserved
1
2
GND
3
4
GND
5
6
RESET
7
8
I/O or Pad Voltage
9
10
GND
11
12
PST2
13
14
PST0
15
16
DDATA2
17
18
DDATA1
DDATA0
19
20
GND
Freescale Reserved
21
22
Freescale Reserved
GND
23
24
Core Voltage
25
26
DSCLK
Developer Reserved
DSI
DSO
PST3
PST1
DDATA3
PSTCLK
TA
Figure 3-1. The J2 Connector pin assignment
M5249C3 User’s Manual, Rev. 1
3-12
Freescale Semiconductor
Appendix A
Configuring dBUG for Network Downloads
The dBUG module has the ability to perform downloads over an Ethernet network using the Trivial File
Transfer Protocol, TFTP (NOTE: this requires a TFTP server to be running on the host attached to the
board). Prior to using this feature, several parameters are required for network downloads to occur. The
information that is required and the steps for configuring dBUG are described below.
A.1
Required Network Parameters
For performing network downloads, dBUG needs 6 parameters; 4 are network-related, and 2 are
download-related. The parameters are listed below, with the dBUG designation following in parenthesis.
All computers connected to an Ethernet network running the IP protocol need 3 network-specific
parameters. These parameters are:
Internet Protocol, IP, address for the computer (client IP),
IP address of the Gateway for non-local traffic (gateway IP), and
Network netmask for flagging traffic as local or non-local (netmask).
In addition, the dBUG network download command requires the following three parameters:
IP address of the TFTP server (server IP),
Name of the file to download (filename),
Type of the file to download (filetype of S-record, COFF, ELF, or Image).
Your local system administrator can assign a unique IP address for the board, and also provide you the IP
addresses of the gateway, netmask, and TFTP server. Fill out the lines below with this information.
Client IP:
Server IP:
Gateway:
Netmask:
A.2
___.___.___.___(IP address of the board)
___.___.___.___(IP address of the TFTP server)
___.___.___.___(IP address of the gateway)
___.___.___.___(Network netmask)
Configuring dBUG Network Parameters
Once the network parameters have been obtained, the dBUG Rom Monitor must be configured. The
following commands are used to configure the network parameters.
set
set
set
set
set
client <client IP>
server <server IP>
gateway <gateway IP>
netmask <netmask>
mac <addr>
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
A-1
Configuring dBUG for Network Downloads
For example, the TFTP server is named ‘santafe’ and has IP address 123.45.67.1. The board is assigned
the IP address of 123.45.68.15. The gateway IP address is 123.45.68.250, and the netmask is
255.255.255.0. The MAC address is chosen arbitrarily and is unique. The commands to dBUG are:
set
set
set
set
set
client 123.45.68.15
server 123.45.67.1
gateway 123.45.68.250
netmask 255.255.255.0
mac 00:CF:52:49:C3:01
The last step is to inform dBUG of the name and type of the file to download. Prior to giving the name of
the file, keep in mind the following.
Most, if not all, TFTP servers will only permit access to files starting at a particular sub-directory. (This
is a security feature which prevents reading of arbitrary files by unknown persons.) For example, SunOS
uses the directory /tftp_boot as the default TFTP directory. When specifying a filename to a SunOS TFTP
server, all filenames are relative to /tftp_boot. As a result, you normally will be required to copy the file
to download into the directory used by the TFTP server.
A default filename for network downloads is maintained by dBUG. To change the default filename, use
the command:
set filename <filename>
When using the Ethernet network for download, either S-record, COFF, ELF, or Image files may be
downloaded. A default filetype for network downloads is maintained by dBUG as well. To change the
default filetype, use the command:
set filetype <srecord|coff|elf|image>
Continuing with the above example, the compiler produces an executable COFF file, ‘a.out’. This file is
copied to the /tftp_boot directory on the server with the command:
rcp a.out santafe:/tftp_boot/a.out
Change the default filename and filetype with the commands:
set filename a.out
set filetype coff
Finally, perform the network download with the ‘dn’ command. The network download process uses the
configured IP addresses and the default filename and filetype for initiating a TFTP download from the
TFTP server.
A.3
Troubleshooting Network Problems
Most problems related to network downloads are a direct result of improper configuration. Verify that all
IP addresses configured into dBUG are correct. This is accomplished via the ‘show ’command.
Using an IP address already assigned to another machine will cause dBUG network download to fail, and
probably other severe network problems. Make certain the client IP address is unique for the board.
Check for proper insertion or connection of the network cable. Is the status LED lit indicating that network
traffic is present?
M5249C3 User’s Manual, Rev. 1
A-2
Freescale Semiconductor
Configuring dBUG for Network Downloads
Check for proper configuration and operation of the TFTP server. Most Unix workstations can execute a
command named ‘tftp’ which can be used to connect to the TFTP server as well. Is the default TFTP root
directory present and readable?
If ‘ICMP_DESTINATION_UNREACHABLE’ or similar ICMP message appears, then a serious error has
occurred. Reset the board, and wait one minute for the TFTP server to time out and terminate any open
connections. Verify that the IP addresses for the server and gateway are correct. Also verify that a TFTP
server is running on the server.
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
A-3
Configuring dBUG for Network Downloads
M5249C3 User’s Manual, Rev. 1
A-4
Freescale Semiconductor
Appendix B
PAL Equations
The PAL equations listed below provide simple logic equations for the memory mapped interface to the
Ethernet controller U4 (sheet 5 of the schematics). The first equation inverts the interrupt signal from the
LAN91C111 and generates an IRQ6 signal to the MCF5249. The next equation inverts the R/W signal
from the MCF5249 to create the W/R signal required by the Ethernet controller. The next two equations
create the positive read (RD) and write (WR) control signals required by the LAN91C111 using the R/W
and CS1 signals from the MCF5249. Finally the reset logic of the LAN91C111 requires a positive logic
RESET signal which is a simple inversion of RESET signal applied to the MCF5249 from either the BDM
port, reset switch (S1) or power on reset (POR).
Important Note the " symbol at the start of some of the signal definitions comments out the signal. Intially
an asynchronous TA terminated interface was considered for the ethernet controller, which is why these
signals have been brought out to the PAL. After initial debug of the board a simple asynchronous
auto-acknowledge interface with wait states set up in the chip select control register sufficed.
module EthernetIF
title 'Ethernet Interface logic for the M5249C3 board'
"March 2 2002 Revision 1.0 of the code"
"EthernetIF device 'ispLSI22LV10';
;"*****************************************************"
;"This abel file contains the code to interface the SMSC"
;"10/100baseT Ethernet controller LAN91C111-NE to the"
;"MCF5249 ColdFire processor"
;"It was targeted to Lattice ispLSI 22LV10 PAL"
;"CS:380E "
;"*****************************************************"
;"*****************************************************"
;"Declaration Section
"
;"*****************************************************"
" Inputs
BCLK
RESET
!CS1
R_W
"!TA_IN
PIN
PIN
PIN
PIN
PIN
2;
3;
4;
5;
6;
"!OE
"!SRDY
INTR0
"ARDY
PIN
PIN
PIN
PIN
7;
9;
10;
11;
" Bus clock input to the 22V10 from MCF5249
" /RESET Input from MCF5249
" /CS1 Chip Select 1 input from MCF5249
" Read not Write input from MCF5249
"" /TA Transfer Ack. input from expansion
connector
"" /OE Output Enable input from MCF5249
"" /SRDY Synchronous Ready input from LAN91C111
" Interrupt 0 input from LAN91C111
"" ARDY Asynchronous ready input from LAN91C111
" Outputs
"!ANRDYREG
PIN
17 ISTYPE 'reg';
"" Registered ARDY
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
B-1
PAL Equations
"!ANRDYDLY
!WR
!RD
"!RDYRTN
"!ADS
W_R
RESET_OUT
!IRQ6
"!TA
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
18 ISTYPE 'reg';
19;
20;
21;
23;
24;
25;
26;
27;
"" Delayed, registered ARDY
" /WR Write Output to LAN91C111
" /RD Read Output to LAN91C111
"" /RDYRTN Ready Return Output to LAN91C111
"" /ADS Address Data Strobe Output to LAN91C111
" Write not Read Output to LAN91C111
" RESET Output to LAN91C111
" Interrupt Request 6 Output
"" /TA Output to the MCF5249
;"*****************************************************"
;"Equations Section
"
;"*****************************************************"
equations
" Invert interrupt from Ethernet controller to GPIO6/IRQ6
IRQ6 = !INTR0;
" Generate inverted R_W
W_R = !R_W;
" Generate Read and Write to controller for asynchronous access
RD = CS1 & R_W;
WR = CS1 & !R_W;
" Generate inverted reset
RESET_OUT = !RESET ;
end
M5249C3 User’s Manual, Rev. 1
B-2
Freescale Semiconductor
Appendix C
Schematics
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
C-1
A
B
C
D
SDRAM_CS2
-RESET
5
-SDRAS
-SDCAS
SDRAM_CS1
-SDWE
SDUDQM
SDLDQM
BCLKE
CRIN
CRIN
Expansion Connectors
Sheet 6
PSU_Osc
TXD0/GPO27
TXD1/GPO28
-RTS0/GPO30
-RTS1/GPO31
SDA1/GPIO55
SCL1/GPIO3
SCL0/QSPICLK
SDA0/QSPIDIN
QSPI_DOUT/GPIO26
QSPI_CS0/GPIO29
QSPI_CS1/GPIO24
QSPI_CS2/GPIO21
QSPI_CS3/GPIO22
RXD0/GPI27
-CTS0/GPI30
RXD1/GPI28
-CTS1/GPI31
-TA_IN
-TA
GPIO5
D[31:16]
A[24:1]
TCK
HI-Z
SDATAI1
SDATAI3/GPI41
SDATAI4/GPI42
EBUIN1/GPI36
EBUIN2/GPI37
EBUIN3/GPI38
EBUIN4/GPI39
TIN0/GPI33
LRCK1
LRCK2/GPIO44
LRCK3/GPIO45
LRCK4/GPIO46
PST[3:0]
DDATA[3:0]
PSTCLK
DSCLK
-BKPT
DSI
DSO
-CS0
R/W
-OE
BCLK
SDATAO1/GPIO25
RCK/GPIO51
SFSY/GPIO52
SUBR/GPIO53
EF/GPIO19
CFLG/GPIO18
TIN1/GPIO23
IDEDIOR/GPIO13
IDEDIOW/GPIO14
IDEIORDY/GPIO16
BUFENB1/GPIO57
BUFENB2/GPIO17
SWE/GPIO12
SRE/GPIO11
SDATA0_SDIO1/GPIO54
SDATA1_BS1/GPIO9
SDATA_BS2/RSTO
SDATA3/GPIO56
SCLKOUT/GPIO15
SDRAM_CS2
CMDSDIO2/GPIO34
SCLK1
SCLK2/GPIO48
SCLK3/GPIO49
SCLK4/GPIO50
-RESET
GPIO6
SDATAO2
-CS1
XTRIM/GPO38
CL11/GPO39
CL16/GPO42
EBUOUT1/GPO36
EBUOUT2/GPO37
TOUT0/GPO33
TOUT1/GPO35
-TA
-RESET
3
2
D[31:16]
A[24:1]
Serial_I2C_QSPI
SCLK4/GPIO50
LRCK4/GPIO46
TXD0/GPO27
TXD1/GPO28
-RTS0/GPO30
-RTS1/GPO31
SDA1/GPIO55
SCL1/GPIO3
SCL0/QSPICLK
SDA0/QSPIDIN
QSPI_DOUT/GPIO26
QSPI_CS0/GPIO29
QSPI_CS1/GPIO24
QSPI_CS2/GPIO21
QSPI_CS3/GPIO22
Ethernet
D[31:16]
GPIO6
-TA_IN
-TA
-OE
-CS1
A[24:1]
R/W
BCLK
-RESET
Sheet 5
Audio
SCLK1
LRCK1
SDATAI1
SDATAO2
CL11/GPO39
CL16/GPO42
SCLK2/GPIO48
LRCK2/GPIO44
SCLK3/GPIO49
Sheet 2
IDE
BUFENB2/GPIO17
D[31:16]
A[24:1]
GPIO5
EF/GPIO19
IDEIOR/GPIO13
IDEIOW/GPIO14
IDEIORDY/GPIO16
R/W
Sheet 10
Memory
D[31:16]
A[24:1]
-SDRAS
-SDCAS
SDRAM_CS1
-SDWE
SDUDQM
SDLDQM
BCLKE
-CS0
R/W
-OE
BCLK
-RESET
Sheet 7
1
1
Thursday, March 07, 2002
Document Number
Hierarchical Block Diagram
Sheet
1
MCF5249 Evaluation Board - Part number RE10811B
of
Freescale Semiconductor - Microcontroller Division (MCD)
Date:
Size
C
Title
D[31:16]
SDATAI3/GPI41
SDATAI4/GPI42
RXD0/GPI27
-CTS0/GPI30
RXD1/GPI28
-CTS1/GPI31
A[24:1]
2
A[24:1]
Sheet 9
ColdFire MCF5249
Debug_Test Points
PST[3:0]
DDATA[3:0]
PSTCLK
DSCLK
-BKPT
DSI
DSO
-CS0
R/W
-OE
BCLK
3
D[31:16]
CPU
TCK
HI-Z
SDATAI1
SDATAI3/GPI41
SDATAI4/GPI42
EBUIN1/GPI36
EBUIN2/GPI37
EBUIN3/GPI38
EBUIN4/GPI39
TIN0/GPI33
LRCK1
LRCK2/GPIO44
LRCK3/GPIO45
LRCK4/GPIO46
PST[3:0]
DDATA[3:0]
PSTCLK
DSCLK
-BKPT
DSI
DSO
-CS0
R/W
-OE
BCLK
SDATAO1/GPIO25
RCK/GPIO51
SFSY/GPIO52
SUBR/GPIO53
EF/GPIO19
CFLG/GPIO18
TIN1/GPIO23
IDEDIOR/GPIO13
IDEDIOW/GPIO14
IDEIORDY/GPIO16
BUFENB1/GPIO57
BUFENB2/GPIO17
SWE/GPIO12
SRE/GPIO11
SDATA0_SDIO1/GPIO54
SDATA1_BS1/GPIO9
SDATA_BS2/RSTO
SDATA3/GPIO56
SCLKOUT/GPIO15
SDRAM_CS2
CMDSDIO2/GPIO34
SCLK1
SCLK2/GPIO48
SCLK3/GPIO49
SCLK4/GPIO50
-RESET
GPIO6
SDATAO2
-CS1
XTRIM/GPO38
CL11/GPO39
CL16/GPO42
EBUOUT1/GPO36
EBUOUT2/GPO37
TOUT0/GPO33
TOUT1/GPO35
Sheet 3
PST[3:0]
DDATA[3:0]
Sheet 4
-SDRAS
-SDCAS
SDRAM_CS1
-SDWE
SDUDQM
SDLDQM
BCLKE
A[24:1]
4
PST[3:0]
DDATA[3:0]
4
TXD0/GPO27
TXD1/GPO28
-RTS0/GPO30
-RTS1/GPO31
SDA1/GPIO55
SCL1/GPIO3
SCL0/QSPICLK
SDA0/QSPIDIN
QSPI_DOUT/GPIO26
QSPI_CS0/GPIO29
QSPI_CS1/GPIO24
QSPI_CS2/GPIO21
QSPI_CS3/GPIO22
5
CRIN
CRIN
D[31:16]
-TA
GPIO5
C-2
RXD0/GPI27
-CTS0/GPI30
RXD1/GPI28
-CTS1/GPI31
Sheet 8
10
Rev
1.1
AFre
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
A
B
C
D
2
2
2
5
DIF Low= 16bit LSB justified, High= I2S 16/18/20-bit
JP4
+3.3V
CKS Low= 256fs, High= 384fs
2
JP3
+3.3V
BOOST Low = no high pass correction, High = high pass correction
JP2
+3.3V
DEM Low = no de-emphasis, High = de-emphasis
JP1
+3.3V
All default jumper settings on this sheet are between pins 1 & 2
1
3
1
3
1
3
1
3
1
1
4
RCA PHONO JACK
J10
J9
RCA PHONO JACK
2
2
470
R107
470
R108
+3.3V
C124
1
2
3
4
5
6
7
8
9
10
11
12
3
C14
0.22uF
R2
10
R1
10
0.1uF
C3
Analog ground
0.1uF
C126
330u 10V
C12
JP13
R119
18
330u 10V
1
2
3
4
5
6
7
8
AINR
AINL
VREF
VCOM
AGND
VA
VD
DGND
U19
2
16
15
14
13
12
11
10
9
2
1
4
3
J1
STEREO JACK SOCKET SW 3.5mm
Analog ground
+3.3V
2
4
6
8
Document Number
MCF5249 - Audio Interfaces
Thursday, March 07, 2002
Date:
1
Sheet
2
MCF5249 Evaluation Board - Part number RE10811B
Size
B
Title
+5V
Analog ground
2
4
6
8
4x 4.7K
of
10
Rev
1.1
CL11/GPO39
SCLK1
CL16/GPO42
LRCK1
SDATAI1
Freescale Semiconductor - Microcontroller Division (MCD)
Jumpers 13 & 14 are fitted during assembly
R120
18
JP14
1
3
5
7
RP43
1
3
5
7
1
All analog ground - single ground connection to digital ground
AK5353VT
TST
TTL
DIF
PDN
SCLK
MCLK
LRCK
SDTO
0.1uF 1uF 50V 0.1uF 1uF 50V
C8
C7
C5
C6
C10
10uF 16V
C11
C9
0.1uF
2
10uF 16V
C122
10uF 16V
C4
+3.3V
0.1uF
C127
10uF 16V
C121
C13
0.22uF
24
23
22
21
20
19
18
17
16
15
14
13
4.7uF 25V
C120
FERRITE_BEAD
2
TST1
TST2
VDD
VSS
VREF
VCOM
TST3
HPVCC
HPGND
NC
AOUTL
AOUTR
0.1uF
C125
AK4360VF
MCLK
PDN
BICK
SDATA
LRCK
MT0
MT1
DEM
MUTEN
BOOST
CKS
DIF
U1
0.1uF
4.7uF 25V
2.2nF
C119
L3
2.2nF
1
C117
C123
3
+5V
MT0 = LOW and MT1 = HIGH providesfastest MUTE time
CKS = LOW 256fsMCLK
DIF = HIGH so audio interface set for I2S mode (20-bit if
fs >40)
SCLK3/GPIO49
CL16/GPO42
CL11/GPO39
SCLK2/GPIO48
SDATAO2
LRCK2/GPIO44
4.7uF 25V
C118
Analog left channel input
4.7uF 25V
C116
Analog right channel input
2
4
2
1
Freescale Semiconductor
1
5
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
C-3
A
B
C
D
-TA
DDATA[3:0]
PSTCLK
PST[3:0]
CMDSDIO2/GPIO34
SWE/GPIO12
SRE/GPIO11
SDATA0_SDIO1/GPIO54
SDATA1_BS1/GPIO9
SDATA_BS2/RSTO
SDATA3/GPIO56
SCLKOUT/GPIO15
IDEDIOR/GPIO13
IDEDIOW/GPIO14
IDEIORDY/GPIO16
BUFENB1/GPIO57
BUFENB2/GPIO17
QSPI_CS2/GPIO21
QSPI_CS3/GPIO22
QSPI_CS1/GPIO24
EF/GPIO19
CFLG/GPIO18
TIN1/GPIO23
QSPI_DOUT/GPIO26
QSPI_CS0/GPIO29
CRIN
XTRIM/GPO38
CL11/GPO39
CL16/GPO42
SDA1/GPIO55
SCL1/GPIO3
SDA0/QSPIDIN
SCL0/QSPICLK
RCK/GPIO51
SFSY/GPIO52
SUBR/GPIO53
TOUT0/GPO33
TOUT1/GPO35
TIN0/GPI33
RXD1/GPI28
TXD1/GPO28
-RTS1/GPO31
-CTS1/GPI31
RXD0/GPI27
TXD0/GPO27
-RTS0/GPO30
-CTS0/GPI30
EBUOUT1/GPO36
EBUOUT2/GPO37
EBUIN1/GPI36
EBUIN2/GPI37
EBUIN3/GPI38
EBUIN4/GPI39
LRCK1
LRCK2/GPIO44
LRCK3/GPIO45
LRCK4/GPIO46
SCLK1
SCLK2/GPIO48
SCLK3/GPIO49
SCLK4/GPIO50
1nF
C19
1
3
5
7
+3.3V supply decoupling
0.1uF
C18
1
3
5
7
1
3
5
7
RP3
1nF
C20
4x 4.7K
2
4
6
8
2
4
6
8
+3.3V
1nF
C21
5
Jumpers only required if I2C channel 0 is used.
For assembly fit to one jumper pin only.
+5V
RP6 4x 4.7K
1
2
1 JP6 2SCL0
1
2
3
4
1 JP5 2
3
4
SDA0
5
6
5
6
7
8
7
8
1
3
5
7
RP2
0.1uF
C17
4x 4.7K
2
2
4
4
6
6
8
8
SDATAO1/GPIO25
SDATAO2
SDATAI1
SDATAI3/GPI41
SDATAI4/GPI42
-RESET
0.1uF
0.1uF
+3.3V
C16
C15
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
RP14B
RP33D
RP36D
RP15B
RP16D
RP34A
RP33B
RP24A
RP32C
RP33A
RP36C
RP36B
RP23D
RP24B
RP17D
RP34B
RP21B
RP19B
RP19C
RP20D
RP27A
RP37D
RP34C
RP33C
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
RP31D
RP32B
RP31A
RP27C
RP32D
RP25B
RP31B
RP29D
RP20C
RP20A
RP20B
RP28D
RP16C
RP38C
RP25D
RP23A
RP39A
RP30D
RP39B
RP39C
RP27B
DDATA0
DDATA1
DDATA2
DDATA3
47
47
47
47
47
47
47
47
RP18B
RP18A
RP19A
RP1-7
47
47
47
47
47
47
RP15D
RP15A
RP22D
RP14D
RP15C
RP14A
470pF
C25
+3.3V
4x 4.7K
2
4
6
8
2
4
6
8
47
47
47
1
3
5
7
RP4
470pF
C24
RP16B
RP23B
RP14C
1
3
5
7
470pF
C23
RP19D
PST0 RP17B
PST1 RP17A
PST2 RP21C
PST3 RP18D
1nF
C22
4
M11
P11
E4
D4
F12
F13
G12
A13
N11
B13
B10
A9
A10
B11
B7
D7
D8
D9
N9
P9
K12
N10
P10
A8
N14
P13
B8
M13
L13
N13
A7
L14
L12
P14
K13
B9
M14
P12
SDA1/GPIO55
SCL1/GPIO3/INT3
SDA0/QSPIDIN
SCL0/QSPICLK
RCK/GPIO51
SFSY/GPIO52
SUBR/GPIO53
TOUT0/GPO33
TOUT1/GPO35
TIN0/GPI33
RXD1/GPI28
TXD1/GPO28
RTS1/GPO31
CTS1/GPI31
RXD0/GPI27
TXD0/GPO27
RTS0/GPO30
CTS0/GPI30
EBUOUT1/GPO36
EBUOUT2/GPO37
EBUIN1/GPI36
EBUIN2/GPI37
EBUIN3/GPI38
EBUIN4/GPI39
LRCK1
LRCK2/GPIO44
LRCK3/GPIO45
LRCK4/GPIO46
SCLK1
SCLK2/GPIO48
SCLK3/GPIO49
SCLK4/GPIO50
SDATAO1/GPIO25
SDATAO2/GPO41
SDATAI1
SDATAI3/GPI41
SDATAI4/GPI42
RSTI
U2
470pF
C26
+1.8VP
470pF
C130
+1.8VP
C4
E6
CORE-VDD
CORE-GND
H14
CRIN
F14
XTRIM/GPO38
G14
CL11/GPO39
G13
CL16/GPO42
0.1uF
C27
K6
K5
CORE-VDD
CORE-GND
E9
E10
CORE-VDD
CORE-GND
+3.3VP
RP16A
0.1uF
0.1uF
0.1uF
C30
3
+3.3VP +1.8VP
C29
C28
ColdFire MCF5249
47
H13
IDEDIOR/GPIO13
H12
IDEDIOW/GPIO14
G11
IDEIORDY/GPIO16
J4
BUFENB1/GPIO57
K11
BUFENB2/GPIO17
L10
K9
CORE-VDD
CORE-GND
QSPI_CS2/GPIO21
QSPI_CS3/GPIO22
QSPI_CS1/GPIO24
EF/GPIO19
CFLG/GPIO18
TIN1/GPI023
QSPI_DOUT/GPIO26
QSPI_CS0/GPIO29
L6
L8
L4
F4
L9
D6
N5
P4
J12
J13
PLL1VDD
PLL1GND
1nF
1nF
3
RP24C
RP21A
RP24D
RP17C
1nF
C33
+3.3VP
+1.8V supply decoupling
C32
C31
H11
J14
PLLCVDD
PLLCGND
K14
J11
PLLGVDD
PLLGGND
CMDSDIO2/GPIO34
SWE/GPIO12
SRE/GPIO11
SDATA0_SDIO1/GPIO54
SDATA1_BS1/GPIO9
SDATA2_BS2/RSTO
SDATA3/GPIO56
SCLKOUT/GPIO15
E3
E7
E8
G4
M4
H3
J3
F3
D12
E11
PAD-VDD
PAD-GND
47
47
47
47
1nF
C34
E5
D5
PAD-VDD
PAD-GND
L3
H4
PAD-VDD
PAD-GND
D10
D11 TDSO
TDI/DSI
E13
TMS/BKPT
E12
F11 TCK
C11 TRST/DSCLK
HI-Z
K8
K10
PAD-VDD
PAD-GND
CNPSTCLK/GPIO63
DBDCPST0/GPIO59
DBDCPST1/GPIO60
DBDCPST2/GPIO61
DBDCPST3/GPIO62
DBDCDDATA0/GPIO0/INT0
DBDCDDATA1/GPIO1/INT1
DBDCDDATA2/GPIO2/INT2
DBDCDDATA3/GPIO4/INT4
TA/GPIO20
D13
B14
C14
C13
D14
A11
B12
A12
A14
L11
C37
470pF
C36
470pF
C35
470pF
2
1
3
5
7
1
3
5
7
1
3
5
7
47
47
RP18C
RP34D
E14
N12
1
3
5
7
RP9
1
3
5
7
RP8
1
3
5
7
+3.3V
+3.3V
+3.3V
2
4x 4.7K
2
4
6
8
2
4
6
8
4x 4.7K
2
4
6
8
2
4
6
8
4x 4.7K
2
4
6
8
2
4
6
8
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
Default jumper setting between pins 1 & 2,
debug mode - BDM. Setting between pins
2 & 3 enables JTAG mode
MCF5249 MAPBGA160
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
RP32A
RP30A
RP22C
RP35B
RP29A
RP29B
RP30B
RP26D
RP29C
RP26C
RP38D
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
47
RP31C
RP36A
RP22B
RP25C
RP22A
RP25A
RP35D
RP37C
RP35C
RP26A
RP37A
RP35A
RP37B
RP40A
RP28A
RP40C
RP28B
RP26B
RP38B
RP40D
RP28C
RP38A
RP27D
RP39D
RP40B
47
RP30C
RP1-7
N8
N2
A6
A1
P1
P2
N3
F1
P3
E1
E2
P8
N7
P7
N6
P6
P5
L7
K7
F2
G1
G2
H1
H2
J1
J2
K1
B6
A5
B5
A4
B4
A3
B3
A2
C1
C2
B1
B2
K2
L1
L2
M1
D1
D2
M2
N1
D3
G3
K4
K3
DEBUG
JP7
RP7
+3.3V
R/W
OE
SDRAM_CS2/GPIO7/INT7
SDRAM_CS1
CS1/GPIO58
CS0
SDRAS
SDCAS
SDWE
SDUDQM/UWE
SDLDQM/LWE
BCLKE
BCLK/GPIO10
DATA_16
DATA_17
DATA_18
DATA_19
DATA_20
DATA_21
DATA_22
DATA_23
DATA_24
DATA_25
DATA_26
DATA_27
DATA_28
DATA_29
DATA_30
DATA_31
2
470pF
C38
+1.8VP
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A25row/A24column_GPO8
GPIO5/INT5
GPIO6/INT6
N4
L5
C12
C3 TEST0
M3 TEST1
M12 TEST2
TEST3
4
1
C-4
3
5
1
3
5
7
1
3
5
7
1
3
5
7
47
HI-Z
TCK
DSCLK
-BKPT
DSI
DSO
R/W
-OE
SDRAM_CS2
SDRAM_CS1
-CS1
-CS0
-SDRAS
-SDCAS
-SDWE
SDUDQM
SDLDQM
BCLKE
BCLK
D[31:16]
A[24:1]
GPIO6
GPIO5
1
Thursday, March 21, 2002
Document Number
MCF5249 CPU and Pull-ups
Sheet
3
MCF5249 Evaluation Board - Part number RE10811B
of
Freescale Semiconductor - Microcontroller Division (MCD)
Date:
Size
C
Title
RP23C
RP21D
47
+3.3V
4x 4.7K
2
4
6
8
2
4
6
8
D[31:16]
RP5
+3.3V
4x 4.7K
2
4
6
8
2
4
6
8
A[24:1]
1
3
5
7
RP1
1
10
Rev
1.1
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
A
B
C
D
1
JP10
JP11
3
3
+1.8V
+1.8V
CRIN
R/W
5
4
DDATA[3:0]
NOTE: Place TP7 & TP8 at the corners of the PCB to
allow easy connection of 'scope probe ground leads.
These test points are fitted for both prototype and
production boards.
1
GROUND
1
GROUND
CPU CLOCK OUTPUT
1
TP6
CHIP SELECT 0
1
TP4
OUTPUT ENABLE
1
TP2
TP8
4
3
DDATA[3:0]
PST2
PST0
1
3
5
7
9
11
13
15
17
19
21
23
25
J2
PST[3:0]
47pF
C39
2
4
6
8
10
12
14
16
18
20
22
24
26
PST3
PST1
3
Thursday, March 07, 2002
Date:
2
Document Number
Debug (BDM) Port & Test Points
Sheet
4
MCF5249 Evaluation Board - Part number RE10811B
1
of
Freescale Semiconductor - Microcontroller Division (MCD)
PSTCLK
-TA
DSI
DSO
-BKPT
DSCLK
1
10
Rev
1.1
IMPORTANT NOTE: ONLY a 3.3V BDM
debugging cable can be used with the
MCF5249 processor.
Size
A
Title
NOTE: Test Points TP1 to TP6 are onl
populated on prototype boards. Please
use the label shown for each test point
on the silkscreen of the PCB.
2
DDATA3
DDATA1
Shrouded BDM Header
NOTE: 4.7K pull up resistors are used on signals -BKPT, DSCLK,
DSI, DSO, -RESET & -TA.
DDATA2
DDATA0
-RESET
TP7
BCLK
-CS0
-OE
Core Voltage.
I/O or Pad Voltage.
PST[3:0]
CPU CLOCK INPUT
1
TP5
READ/WRITE
1
TP3
TRANSFER ACK
1
TP1
JUMPERS 10 & 11 SHOULD BE
INSTALLED ACROSS PINS 1&2
DURING ASSEMBLY.
+3.3V
1
2
Freescale Semiconductor
2
+3.3V
5
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
C-5
A
B
C
D
12
iSP Prog.
1
2
3
4
5
6
7
8
J12
+5V
R/W
-TA_IN
-OE
-CS1
GPIO6
-TA
BCLK
-RESET
11
JP15
5
R94
10K
+3.3V
R85
1K
2
NOTE: JP15 is normally fitted.
Remove to allow use of CS1
with expansion connectors.
1
NOTE: separate
network ground.
11
12
NOTE: separate
network ground.
Amphenol RHJS-5381 RJ45_LED
R88
1K
+3.3V
14
14
10
1
2
3
4
5
6
7
8
10
9
1
3
5
7
9
13
13
I3
I4
I5
MODE
I6
I7
I8
U5
C40
1nF
4x 75
RP10
14
3
+3.3V
+3.3V
+3.3V
C41
10nF
R92
24.9
R89
24.9
9
10
I/O2
I/O3
I/O4
TDO
I/O5
I/O6
I/O7
R121
1K
+3.3V
25
24
23
22
21
20
19
+3.3V
R90
24.9
49.9
R86
+3.3V
4
V2
VIA
1
2
4
6
8
+3.3V
V1
VIA
1
RP13 4x 10K
1
2
1
3
4
3
5
6
5
7
8
7
NOTE: Place via's on all unused U5
I/O pins. U5 is an ispGAL which
allows re-programming via J12.
ispGAL22LV10-5LJ PLCC 28pin
R91
24.9
HALO TG110-S050N5
8
7
11
15
6
16
T1
2
4
1
NOTE: separate
network ground.
RP45 4x 4.7K
2
1
2
4
3
4
6
5
6
8
7
8
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
J3
+3.3V
8
6
4
2
8
6
4
2
7
5
3
1
7
5
3
1
4
3
2
1
28
27
26
I2
I1
CP/I0
TCLK
VCC
I/O0
I/O1
I9
I10
VSS
TDI
I11
I/O9
I/O8
12
13
14
15
16
17
18
49.9
R87
8
6
4
2
CLK
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
25Mhz
GND
NC
VDD
RP12 4x 10K
7
8
7
5
6
5
3
4
3
1
2
1
R93
11K 1%
7
4
NC
U3
3
+3.3V
VDD
nCSOUT
IOS0
IOS1
IOS2
ENEEP
EEDO
EEDI
EESK
EECS
AVDD
RBIAS
AGND
TPO+
TPOAVDD
TPI+
TPIAGND
nLNK
LBK
nLEDA
nLEDB
GND
MDI
MDO
MCLK
nCNTRL
INTR0
RESET
nRD
nWR
U4
8
11
14
OSCILLATOR LAYOUT FOOTPRINT FOR
8 & 14 DIL OSC. PACKAGES
D24
D25
D26
D27
1
3
2
D28
D29
D30
D31
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
nBE2
nBE1
nBE0
GND
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
VDD
D8
D9
D10
D11
GND
D12
D13
D14
D15
GND
D16
D17
SMSC LAN91C111-NE
XTAL2
XTAL1
RX_ER
RX_DV
RXD0
RXD1
RXD2
RXD3
VDD
CRS100
RX25
GND
TXD0
TXD1
TXD2
TXD3
COL100
TXEN100
VDD
TX25
GND
D0
D1
D2
D3
GND
D4
D5
D6
D7
VDD
nBE3
VDD
nDATACS
nCYCLE
W/nR
nADS
ARDY
GND
nVLBUS
AEN
LCLK
nSRDY
VDD
nLEDV
nRDYRTN
X25OUT
D31
D30
D29
D28
GND
D27
D26
D25
D24
GND
D23
D22
D21
D20
VDD
D19
D18
C-6
1
3
5
7
2
RP11 4x 10K
2
1
2
4
3
4
6
5
6
8
7
8
+3.3V
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
5
C43
1nF
C44
0.1uF
D20
D21
D22
D23
D16
D17
D18
D19
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
C45
0.1uF
C46
0.1uF
A[24:1]
C47
1nF
C48
1nF
Monday, March 18, 2002
1
Sheet
Document Number
10/100baseT Ethernet Port & Magnetics
5
MCF524 Evaluation Board - Part number RE10811B
of
10
Rev
1.1
C49
1nF
+3.3V
A[24:1]
D[31:16]
Freescale Semiconductor - Microcontroller Division (MCD)
Date:
Size
B
Title
C42
0.1uF
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
+3.3V
D[31:16]
1
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
Freescale Semiconductor
A
B
C
D
-SDWE
-SDCAS
SDLDQM
SDUDQM
-SDRAS
SDRAM_CS1
SDA0/QSPIDIN
BCLKE
BCLK
SCL0/QSPICLK
-CS1
-CS0
D[31:16]
5
SDRAM_CS2
GPIO5
GPIO6
SDATA3/GPIO56
D[31:16]
A[24:1]
5
D29
D30
D31
D26
D27
D28
D23
D24
D25
D20
D21
D22
D18
D19
D16
D17
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
J4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
4
C50
1nF
+5V
C51
1nF
A24
A21
A22
A23
A18
A19
A20
A15
A16
A17
A12
A13
A14
A9
A10
A11
A7
A8
A4
A5
A6
A1
A2
A3
+1.8V +3.3V +5V
AMP 177983-5 120way SMT Receptacle
+5V +3.3V +1.8V
A[24:1]
4
C52
0.1uF
C53
0.1uF
QSPI_DOUT/GPIO26
QSPI_CS2/GPIO21
QSPI_CS3/GPIO22
SDATA1_BS1/GPIO9
QSPI_CS0/GPIO29
QSPI_CS1/GPIO24
SDATA0_SDIO1/GPIO54
SDATA_BS2/RSTO
BUFENB1/GPIO57
C54
10nF
+3.3V
RED LED
D13
R109
470
3
C59
470pF
C60
470pF
C61
470pF
+1.8V
EBUOUT1/GPO36
EBUOUT2/GPO37
CFLG/GPIO18
-OE
SDA1/GPIO55
TOUT1/GPO35
SDATAO2
LRCK2/GPIO44
SCL1/GPIO3
SCLK1
SDATAO1/GPIO25
LRCK1
BUFENB2/GPIO17
CRIN
SCLK4/GPIO50
R/W
XTRIM/GPO38
CL11/GPO39
IDEDIOR/GPIO13
IDEIORDY/GPIO16
IDEDIOW/GPIO14
SFSY/GPIO52
RCK/GPIO51
SUBR/GPIO53
PSTCLK
SWE/GPIO12
-RTS1/GPO31
TOUT0/GPO33
SCLK3/GPIO49
-RTS0/GPO30
TXD1/GPO28
SRE/GPIO11
-TA_IN
RXD1/GPI28
TXD0/GPO27
RXD0/GPI27
LRCK3/GPIO45
RED LED
D16
470
470
D17
R112
+3.3V
R113
RED LED
+3.3V
RED LED
D20
R116
470
+3.3V
C58
470pF
RED LED
D21
R117
470
+3.3V
C57
10nF
RED LED
D19
R115
470
+3.3V
C56
10nF
RED LED
D14
R110
470
+3.3V
C55
10nF
RED LED
D18
R114
470
+3.3V
NOTE: Please place D13 through D21 diodes together in a line.
+3.3V
SCLKOUT/GPIO15
EF/GPIO19
CMDSDIO2/GPIO34
RED LED
D15
R111
470
+3.3V
3
C62
10nF
+3.3V
4.7K
R123
2
C63
10nF
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
J5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
C64
470pF
C65
470pF
C66
470pF
PST[3:0]
DDATA[3:0]
Thursday, March 21, 2002
Date:
1
Document Number
MCF5249 Expansion Connectors
Sheet
6
MCF5249 Evaluation Board - Part number RE10811B
of
Freescale Semiconductor - Microcontroller Division (MCD)
SCLK2/GPIO48
CL16/GPO42
TIN1/GPIO23
EBUIN1/GPI36
EBUIN2/GPI37
EBUIN3/GPI38
LRCK4/GPIO46
SDATAI4/GPI42
SDATAI3/GPI41
SDATAI1
-TA
-RESET
HI-Z
TCK
TIN0/GPI33
-CTS1/GPI31
EBUIN4/GPI39
-CTS0/GPI30
DSCLK
-BKPT
DSO
DSI
PST[3:0]
DDATA[3:0]
Size
C
Title
C67
470pF
Analog Ground
PST1
PST2
PST3
DDATA2
DDATA3
PST0
DDATA0
DDATA1
+1.8V +3.3V +5V
AMP 177983-5 120way SMT Receptacle
+5V +3.3V +1.8V
1
10
Rev
1.1
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
C-7
C-8
A
B
C
D
BUFENB2/GPIO17
R/W
D[31:16]
A[24:1]
5
5
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
A[24:1]
A1
A2
A3
A4
A5
4
10
15
21
1
48
25
24
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
4
10
15
21
1
48
25
24
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
GND
GND
GND
GND
VCC
VCC
VCC
VCC
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
GND
GND
GND
GND
VCC
VCC
VCC
VCC
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
C113
1nF
+3.3V
28
34
39
45
7
18
31
42
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
28
34
39
45
7
18
31
42
C114
0.1uF
MC74LCX16245DT
GND
GND
GND
GND
1DIR
1OE
2OE
2DIR
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
U17 Bi-directional
MC74LCX16245DT
GND
GND
GND
GND
1DIR
1OE
2OE
2DIR
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
C112
0.1uF
U16 Uni-directional
C111
1nF
+3.3V
4
IDE_D15
IDE_D14
IDE_D13
IDE_D12
IDE_D11
IDE_D10
IDE_D9
IDE_D8
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
+3.3V
+3.3V
IDE_A0
IDE_A1
IDE_A2
IDE_CS0
IDE_CS1
4
1
3
5
7
1
3
5
7
2
4
6
8
2
4
6
8
RP42 4x 10K
3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HDR20 X 2 Shrouded
IDE_RESET 1
IDE_D7
3
IDE_D6
5
IDE_D5
7
IDE_D4
9
IDE_D3
11
IDE_D2
13
IDE_D1
15
IDE_D0
17
19
21
IDE_IOW
23
IDE_IOR
25
IDE_IOCHRDY
27
29
IDE_IRQ
31
IDE_A1
33
IDE_A0
35
IDE_CS0
37
IDE_ACTIVITY 39
3
IDE_A2
IDE_CS1
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
2
2
Date:
Size
B
Title
1
3
5
7
2
4
6
8
+3.3V
IDEIORDY/GPIO16
IDEIOR/GPIO13
IDEIOW/GPIO14
GPIO5
2
4
6
8
RP41 4x 4.7K
1
3
5
7
Thursday, March 21, 2002
Document Number
IDE Interface
1
Sheet
10
MCF5249 Evaluation Board - Part number RE10811B
of
Freescale Semiconductor - Microcontroller Division (MCD)
RED IDE LED
D9
R102
270
+3.3V
EF/GPIO19
1
10
Rev
1.1
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
A
B
C
2
A20
-OE
-CS0
R/W
-RESET
5
A19
A18
A8
A7
A6
A5
A4
A3
A2
A16
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DEFAULT SETTING - JUMPER 12 SHOULD
BE INSTALLED ACROSS PINS 1&2
16MBit Flash Boot
JP12
4.7K
R103
+3.3V
1
Freescale Semiconductor
3
D
5
U6
Flash memory
C70
0.1uF
4
4
A[24:1]
48 A17
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
C72
0.1uF
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
C71
0.1uF
AM29LV160DB90EC (1M X16bit) 48pin TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A[24:1]
C69
0.1uF
+3.3V
A1
D27
D19
D26
D18
D25
D17
D24
D16
D31
D23
D30
D22
D29
D21
D28
D20
R95 4.7K
+3.3V
3
A[24:1]
D[31:16]
3
C73
1nF
+3.3V
A5
B6
C6
D6
D5
E6
F6
G6
G1
F1
E1
D2
D1
C1
B1
A2
K6
K5
L5
M6
M5
N5
N2
M2
M1
L2
L1
K2
L6
K1
A22
A21
A16
A15
A14
A13
A12
A11
A10
A9
A17
A18
A19
A20
C75
1nF
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
C74
1nF
CLK
CKE
WE#
CS#
DQMH
DQML
CAS#
RAS#
VSS
VSS
VSS
H1
J1
H6
J2
H2
H5
J6
J5
G5
N1
A1
F5
C5
E2
B2
E5
B5
F2
C2
A[24:1]
2
K4S641633D-G (4Mx16) 52PBGA (4x13)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
VSSQ
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
VDDQ
VDDQ
A6
G2
N6
D[31:16]
VDD
VDD
VDD
SDRAM memory
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U7
C76
1nF
2
+3.3V
Date:
Size
B
Title
Thursday, March 07, 2002
Document Number
Flash & SDRAM memory
1
Sheet
7
MCF5249 Evaluation Board - Part number RE10811B
of
Freescale Semiconductor - Microcontroller Division (MCD)
A[24:1]
BCLK
BCLKE
-SDWE
SDRAM_CS1
SDUDQM
SDLDQM
-SDCAS
-SDRAS
D[31:16]
1
10
Rev
1.1
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
C-9
A
B
C
D
R99
3K
R96
1K
C92
22pF
+1.8V
OE
A
GND
1 2
R101 1M
5
3
2
Vcc5 RST
RSTINGND
Vcc3
MR
U9
C115
1nF
4
R122
4.7K
Y
VCC
4
5
CONTROL
RESET
RESET
VCC
SENSE
1
2
3
C93
22pF
CRIN
1
6
5
8
7
R97
270
R104
270
-RESET
-
+
PC power
+5V
GND
GND
+12V
J11
4
3
2
1
Augat 25V-02
2
1
4
2-way Bare Wire
Power
P2 Connector
Switchcraft RAPC712
-
0.1uF
C94
Power Jack Connector P1 2.1mm diameter
+
3
2
1
1nF
C95
2
MRA4003T3
D4
1
D2
2
MBRS340T3
D7
5A Fast blow.
F1
5
1
C96
1000uF
3
5
1
5.0V Regulator
MBRS340T3
1
+1.8V
+1.8V
+3.3V
+5V
C81
0.1uF
~ON/OFF
VIN
~ON/OFF
VIN
FB
VOUT
U12 LM2596S-5
FB
VOUT
U11 LM2596S-3.3
3.3V Regulator
MBRS340T3
D1
NOTE: Schottky Diode prevents excessive
difference between 3.3V & 1.8V
rails, at power down
MRA4003T3
D3
NOTE: Diodes prevent excessive
difference between 3.3V & 1.8V
rails, at power up
NOTE: the positive terminal of each power
connector is shown on the silkscreen of
the PCB
+3.3V
+3.3V
SDRAM_CS2
DC voltage input range +7 to +14V
KS11R23CQD
RESET
S1
D10
RED LED
+3.3V
Debounced IRQ7 Signal
+3.3V
HARD_RESET
RED LED
D5
+3.3V
TLC7733ID
GND
CT
RESIN
U18
+3.3V
MAX6355LSUT-T
6
5
4
U10
NC7SZU04
+5V
11.2896 MHz X1
1
2
3
+3.3V
KS11R22CQD
S2
Abort/IRQ7
+3.3V
3
GND
3
4
1
2
GND
3
TAB
6
TAB
6
4
2
4
2
C82
0.1uF
C84
1nF
VIN
D8
MBRS340T3
25uH
L2
C85
1nF
2
120
C97
330uF
C90
330uF
2
C98
0.1uF
C91
0.1uF
R100 56
R98
VOUT
LT1086CM
D6
MBRS340T3
2
All caps less
than 1uF are
0805 body
size
1.8V Regulator
U8
25uH
L1
C86
10uF
3
C83
1nF
All resistors are
0805 body size.
1
2
1
2
ADJ
C-10
1
5
JP9
2
+3.3V
Date:
Size
B
Title
+5V GREEN POWER LED
D12
+5V
2
+1.8V
+1.8VP
+1.8V GREEN POWER LED
D22
JP8
Thursday, March 21, 2002
1
Sheet
Document Number
Power Supply, Reset & Clock Oscillator
8
MCF5249 Evaluation Board - Part number RE10811B
of
Freescale Semiconductor - Microcontroller Division (MCD)
560
R106
+3.3V GREEN POWER LED
D11
R105
270
1
+3.3VP
0.1uF
C88
JP9 SHOULD BE
INSTALLED DURING
ASSEMBLY
C87
330uF
R118
22
1
JP8 SHOULD BE
INSTALLED DURING
ASSEMBLY
1
10
Rev
1.1
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
Freescale Semiconductor
A
B
C
D
C102
0.1uF
C108
0.1uF
RXD1/GPI28
LRCK4/GPIO46
TXD1/GPO28
-RTS1/GPO31
-CTS1/GPI31
C107
1nF
+3.3V
SDATAI4/GPI42
RXD0/GPI27
SCLK4/GPIO50
TXD0/GPO27
-RTS0/GPO30
-CTS0/GPI30
C101
1nF
+3.3V
SDATAI3/GPI41
5
5
RP44 4x 4.7K
2
1
2
4
3
4
6
5
6
8
7
8
C109
0.22uF
C103
0.22uF
C110
0.22uF
C104
0.22uF
4
NOTE: The I2C/Mbus on the MCF5249 will
support both 3.3V & 5V devices.
1
3
5
7
+5V
C106
0.22uF
C105
0.22uF
C100
0.22uF
C99
0.22uF
4
U13
MAX3225CAP
FORCEOFF
VCC
GND
T1OUT
R1IN
R1OUT
FORCEON
T1IN
T2IN
INVALID
MAX3225CAP
FORCEOFF
VCC
GND
T1OUT
R1IN
R1OUT
FORCEON
T1IN
T2IN
INVALID
+5V
+3.3V
NOT POPULATED AT ASSEMBLY.
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
+3.3V
3
I2C Molex Conn. 71565
1
2
3
4
J7
RS232 Transceiver.
READY
C1+
V+
C1C2+
C2VT2OUT
R2IN
R2OUT
U14
RS232 Transceiver.
READY
C1+
V+
C1C2+
C2VT2OUT
R2IN
R2OUT
SCL1/GPIO3
SDA1/GPIO55
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
3
2
NOT POPULATED AT ASSEMBLY.
QSPI connector 0.1 pitch
1
2
3
4
5
6
7
8
9
10
J6
+5V +3.3V
2
P4
SCL0/QSPICLK
SDA0/QSPIDIN
QSPI_DOUT/GPIO26
QSPI_CS0/GPIO29
QSPI_CS1/GPIO24
QSPI_CS2/GPIO21
QSPI_CS3/GPIO22
AUXILLARY PORT
9-WAY D-TYPE
(Female)
5
9
4
8
3
7
2
6
1
Thursday, March 21, 2002
Document Number
RS232 Serial, I2C & QSPI Interfaces
1
Sheet
9
MCF5249 Evaluation Board - Part number RE10811B
of
Freescale Semiconductor - Microcontroller Division (MCD)
Date:
Size
B
Title
P3
TERMINAL PORT
9-WAY D-TYPE
(Female)
5
9
4
8
3
7
2
6
1
1
10
Rev
1.1
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
C-11
C-12
A
B
C
D
C102
0.1uF
C108
0.1uF
RXD1/GPI28
LRCK4/GPIO46
TXD1/GPO28
-RTS1/GPO31
-CTS1/GPI31
C107
1nF
+3.3V
SDATAI4/GPI42
RXD0/GPI27
SCLK4/GPIO50
TXD0/GPO27
-RTS0/GPO30
-CTS0/GPI30
C101
1nF
+3.3V
SDATAI3/GPI41
5
5
RP44 4x 4.7K
2
1
2
4
3
4
6
5
6
8
7
8
C109
0.22uF
C103
0.22uF
C110
0.22uF
C104
0.22uF
4
NOTE: The I2C/Mbus on the MCF5249 will
support both 3.3V & 5V devices.
1
3
5
7
+5V
C106
0.22uF
C105
0.22uF
C100
0.22uF
C99
0.22uF
4
U13
MAX3225CAP
FORCEOFF
VCC
GND
T1OUT
R1IN
R1OUT
FORCEON
T1IN
T2IN
INVALID
MAX3225CAP
FORCEOFF
VCC
GND
T1OUT
R1IN
R1OUT
FORCEON
T1IN
T2IN
INVALID
+5V
+3.3V
NOT POPULATED AT ASSEMBLY.
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
+3.3V
3
I2C Molex Conn. 71565
1
2
3
4
J7
RS232 Transceiver.
READY
C1+
V+
C1C2+
C2VT2OUT
R2IN
R2OUT
U14
RS232 Transceiver.
READY
C1+
V+
C1C2+
C2VT2OUT
R2IN
R2OUT
SCL1/GPIO3
SDA1/GPIO55
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
3
2
NOT POPULATED AT ASSEMBLY.
QSPI connector 0.1 pitch
1
2
3
4
5
6
7
8
9
10
J6
+5V +3.3V
2
P4
SCL0/QSPICLK
SDA0/QSPIDIN
QSPI_DOUT/GPIO26
QSPI_CS0/GPIO29
QSPI_CS1/GPIO24
QSPI_CS2/GPIO21
QSPI_CS3/GPIO22
AUXILLARY PORT
9-WAY D-TYPE
(Female)
5
9
4
8
3
7
2
6
1
Tuesday, February 19, 2002
Document Number
RS232 Serial, I2C & QSPI Interfaces
1
Sheet
9
MCF5249 Evaluation Board - Part number RE10811B
of
Freescale Semiconductor - Microcontroller Division(MCD)
Date:
Size
B
Title
P3
TERMINAL PORT
9-WAY D-TYPE
(Female)
5
9
4
8
3
7
2
6
1
1
10
Rev
1.0
A
B
C
D
Schematics
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
Appendix D
Evaluation Board BOM
Table D-1. M5249C3 Bill of Materials
Item
Qty
Reference
Part
1
36
C3,C5,C7,C9,C15,C16,C17,C18,C
27,C28,C29,C30,C42,C44,
C45,C46,C52,C53,C69,C70,
C71,C72,C81,C82,C88,C91,C94,C
98,C102,C108,C112,C114,
C124,C125,C126, C127
0.1uF 25V
2
5
C4,C10,C86,C121,C122
10uF 16V Electrolytic (Al)
SMT Capacitors
3
2
C6,C8
1uF 50V Electrolytic (Al)
SMT Capacitors
4
5
C11,C12,C87,C90,C97
5
10
C13,C14,C99,C100,C103,C104,C
105,C106,C109,C110,
0.22uF 16 or 25V
6
28
C19,C20,C21,C22,C31,C32,C33,C
34,C40,C43,C47,C48,C49,
C50,C51,C73,C74,C75,C76,C83,C
84,C85,C95,C101,C107,C111,C11
3,C115
1nF 50V COG
SMT Decoupling Capacitors
7
17
C23,C24,C25,C26,C35,C36,C37,C
38,C58,C59,C60,C61,C64,
C65,C66,C67,C130
470pF 50V COG
SMT Decoupling Capacitors
8
1
C39
47pF 50V COG
SMT Capacitors
9
7
C41,C54,C55,C56,C57,C62,C63
10nF 25V X7R
SMT Capacitors
10
2
C92,C93
22pF 50V COG
SMT Capacitors
11
1
C96
12
4
C116,C118,C119,C120
4.7uF 16V X7R
SMT Capacitors
13
2
C117,C123
2.2nF 50V X7R
SMT Capacitors
14
5
D1,D2,D6,D7,D8
MBRS340T3
SMT Schottky Power Diodes
15
2
D3,D4
MRA4003T3
SMT Power Diodes
16
3
D5,D9,D10
17
3
D11,D12,D22
18
9
D13,D14,D15,D16,D17,D18,D19,
D20,D21
330uF 10V Tant. AVX
TPSE337K10CLR
Rubycon 35V 1000uF
Liteon LTL-94PURK-TA
Liteon LTL-94PGK-TA
Liteon LTL-94PURK-TA
Function
SMT Decoupling Capacitors
SMT Decoupling Capacitors
SMT Capacitors
Thru’ hole Capacitor
Red SMT LEDs
Green SMT LEDs
Red SMT LEDs
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
D-1
Evaluation Board BOM
Table D-1. M5249C3 Bill of Materials (continued)
Item
Qty
Reference
Part
19
1
F1
Multicomp MCHTE-15M
20
1
JP1
Harwin M22-2010305
3-way jumper - de-emphasis select,
low = no, high = yes
21
1
JP2
Harwin M22-2010305
3-way jumper - high pass correction,
low = no, high = yes
22
1
JP3
Harwin M22-2010305
3-way jumper - clock sample freq.,
low = 256fs, high = 384fs
23
1
JP4
Harwin M22-2010305
3-way jumper - audio bit stream, low
= 16-bit LSB justified, high = I2S
16/18/20-bit
24
1
JP5
Harwin M22-2010205
2-way jumper - I2C SDA0 pull-up
25
1
JP6
Harwin M22-2010205
2-way jumper - I2C SCL0 pull-up
26
1
JP7
Harwin M22-2010305
3-way jumper - BDM/JTAG select
27
3
JP8, JP9, JP15
Harwin M22-2010205
2-way jumpers - 1.8V uP power, 3.3V
uP power & -CS1 for expansion
connector not E’net
28
3
JP10,JP11,JP12
Harwin M22-2010305
3-way jumpers - I/O voltage select,
Core voltage select & dBUG or user
code select for Flash
29
2
JP13,JP14
Harwin M22-2010205
2-way jumpers - audio output load
impedance select
30
1
J1
Schurter 4832.2320
31
1
J2
2x13 0.1 pitch connector
32
1
J3
Amphenol RHJS-5381
33
2
J4,J5
34
1
J6
1x10 0.1 pitch connector
35
1
J7
Molex 71565
36
1
J8
2x20 0.1 pitch connector
37
2
J9,J10
Marushin Electric/Schurter RCA Phono Audio jack socket
MR551L
38
1
J11
PC disk drive power conn. Alternate EVB power connector
39
1
J12
40
2
L1,L2
41
1
L3
42
1
P1
Switchcraft RAPC712
43
1
P2
Augat 25V-02
AMP 177983-5
1x8 0.1 pitch SIL conn.
Siemens B82111-B-C24
Function
Fuse
3.5mm Stereo jack socket (SW)
Shrouded BDM header
RJ45 connector+integrated LEDS
120 way SMT receptacle - expansion
connectors
QSPI connector (not fitted)
I2C connector (not fitted)
IDE connector
iSP GAL programming connector
DC-DC Power supply inductors
Murata BLM31AJ601SN1L Ferrite bead inductor
2.1mm barrel power connector
2-way bare wire power connector
M5249C3 User’s Manual, Rev. 1
D-2
Freescale Semiconductor
Evaluation Board BOM
Table D-1. M5249C3 Bill of Materials (continued)
Item
Qty
Reference
Part
44
2
P3,P4
45
13
RP1, RP2, RP3, RP4, RP5, RP6,
RP7, RP8, RP9, RP41, RP43,
RP44, RP45
Philips ARC241-4K7
4x 4.7K ohm SMT resistor packs
46
1
RP10
Philips ARC241-75R
4x 75 ohm SMT resistor pack
47
4
RP11,RP12,RP13,RP42
Philips ARC241-10K
4x 10K ohm SMT resistor packs
48
27
RP14,RP15,RP16,RP17,RP18,
RP19,RP20,RP21,RP22,RP23,
RP24,RP25,RP26,RP27,RP28,
RP29,RP30,RP31,RP32,RP33,
RP34,RP35,RP36,RP37,RP38,
RP39, RP40
Philips ARC241-47R
4x 47 ohm SMT resistor packs
49
2
R1,R2
SMT 10 ohm 0805 resistors
50
4
R85,R88,R96,R121
SMT 1K ohm 0805 resistors
51
2
R86,R87
SMT 49.9 ohm 1% 0805 resistors
52
4
R89,R90,R91,R92
SMT 24.9 ohm 1% 0805 resistors
53
1
R93
SMT 11K ohm 1% 0805 resistor
54
1
R94
SMT 10K ohm 0805 resistor
55
4
R95,R103,R122,R123
SMT 4.7K ohm 0805 resistors
56
4
R97,R102,R104,R105
SMT 270 ohm 0805 resistors
57
1
R98
SMT 120 ohm 0805 resistor
58
1
R99
SMT 3K ohm 0805 resistor
59
1
R100
SMT 56 ohm 0805 resistor
60
1
R101
SMT 1M ohm 0805 resistor
61
1
R106
SMT 560 ohm 0805 resistor
62
11
R107,R108,R109,R110,R111,
R112,R113,R114,R115,R116,
R117
SMT 470 ohm 0805 resistors
63
1
R118
SMT 22 ohm 0805 resistor
64
2
R119,R120
SMT 18 ohm 0805 resistors
65
1
S1
C&K KS11R23CQD
Red reset switch
66
1
S2
C&K KS11R22CQD
Black abort/Int. switch
67
8
TP1,TP2,TP3,TP4,TP5,TP6,TP7,T
Keystone Electrical
SMT Test points - only TP7 & TP8
P8
Components Cat. No.5015 (GND) fitted for production
68
1
T1
Halo TG110-S050N5
69
1
U1
AKM AK4360VF
70
1
U2
McMurdo SDEX9SNT
Function
RS232 ports - 9 way thru’ hole
Ethernet isolation transformer
DAC and stereo amplifier
Freescale XCF5249VF140 ColdFire V2 CPU - 140MHz
M5249C3 User’s Manual, Rev. 1
Freescale Semiconductor
D-3
Evaluation Board BOM
Table D-1. M5249C3 Bill of Materials (continued)
Item
Qty
Reference
Part
71
1
U3
Pletronics
25MHz oscillator for LAN91C111
72
1
U4
SMSC LAN91C111
Ethernet controller 10/100BaseT
73
1
U5
Lattice ispGAL22LV1-5LJ
74
1
U6
AMD Am29LV160DB90EC 1Mx16 48pin TSSOP Flash
EEPROM memory
75
1
U7
Samsung K4S641633D-G Synchronous DRAM 4Mx16
52PBGA (4x13)
76
1
U8
Linear Technology
LT1086CM
DC to DC regulator (+5V to +1.8V)
77
1
U9
Maxim MAX6355LSUT-T
Reset controller and 3 rail voltage
sensor (+5V, +3.3V & +1.8V)
78
1
U10
National Semiconductor
NC7SZU04
CMOS unbuffered inverter driving
oscillator circuit
79
1
U11
National Semiconductor
LM2596S-3.3
DC to DC regulator (+7V/+14V to
+3.3V)
80
1
U12
National Semiconductor
LM2596S-5
DC to DC regulator (+7v/+14V to
+5V)
81
2
U13, U14
Maxim MAX3225CAP
+3.3V RS232 transceivers
82
2
U16, U17
On Semiconductor
MC74LCX16245DT
16bit wide bus transceivers
83
1
U18
TI TLC7733ID
Abort switch debounce circuit
84
1
U19
AKM AK5353VT
Stereo audio ADC via I2S I/F
85
1
X1
HC49US case
Function
PAL22V10 3.3V in-system
programmable (isp)
11.2896MHz quartz crystal
M5249C3 User’s Manual, Rev. 1
D-4
Freescale Semiconductor