Download HY11S14 Hardware User`s Manual

HY11S14
Hardware User’s Manual
.
© 2009-2012 HYCON Technology Corp.
www.hycontek.com
APD-HYIDE005-V04_EN
HY11S14
HY-IDE Hardware User’s Manual
Table of Contents
1. IDE FRAME............................................................................................................................................... 4 2. HY-IDE USB CONTROL BOARD............................................................................................................. 6 2.1. Diagram................................................................................................................................................. 6 2.2. Circuit Description ................................................................................................................................. 7 3. HY-IDE ICE BOARD ................................................................................................................................. 8 3.1. Diagram................................................................................................................................................. 8 3.2. Circuit Description ............................................................................................................................... 10 3.3. Circuit Diagram ................................................................................................................................... 12 4. HY-IDE TARGET BOARD....................................................................................................................... 14 .
4.1. Diagram............................................................................................................................................... 14 4.2. Circuit Description ............................................................................................................................... 16 4.3. Circuit Diagram ................................................................................................................................... 24 5. SIMPLE ERROR DETECTION ............................................................................................................... 26 5.1. ICE cannot connect to software .......................................................................................................... 26 5.2. Program Memory Loading Fail............................................................................................................ 29 6. REVISION HISTORY .............................................................................................................................. 31 © 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page2
HY11S14
HY-IDE Hardware User’s Manual
Attention：
1.
HYCON Technology Corp. reserves the right to change the content of this datasheet without further
notice. For most up-to-date information, please constantly visit our website:
http://www.hycontek.com .
2.
HYCON Technology Corp. is not responsible for problems caused by figures or application circuits
narrated herein whose related industrial properties belong to third parties.
3.
Specifications of any HYCON Technology Corp. products detailed or contained herein stipulate the
performance, characteristics, and functions of the specified products in the independent state. We
does not guarantee of the performance, characteristics, and functions of the specified products as
placed in the customer’s products or equipment. Constant and sufficient verification and evaluation
is highly advised.
4.
Please note the operating conditions of input voltage, output voltage and load current and ensure
the IC internal power consumption does not exceed that of package tolerance. HYCON Technology
Corp. assumes no responsibility for equipment failures that resulted from using products at values
that exceed, even momentarily, rated values listed in products specifications of HYCON products
specified herein.
5.
Notwithstanding this product has built-in ESD protection circuit, please do not exert excessive static
electricity to protection circuit.
6.
.
Products specified or contained herein cannot be employed in applications which require extremely
high levels of reliability, such as device or equipment affecting the human body, health/medical
equipments, security systems, or any apparatus installed in aircrafts and other vehicles.
7.
Despite the fact that HYCON Technology Corp. endeavors to enhance product quality as well as
reliability in every possible way, failure or malfunction of semiconductor products may happen.
Hence, users are strongly recommended to comply with safety design including redundancy and
fire-precaution equipments to prevent any accidents and fires that may follow.
8.
Use of the information described herein for other purposes and/or reproduction or copying without
the permission of HYCON Technology Corp. is strictly prohibited.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page3
HY11S14
HY-IDE Hardware User’s Manual
1. IDE Frame
HY-IDE (HYCON-Integrated Development Environment) is composed by USB Control
Board, ICE Board and Target Board that can emulate HY11P Series products’ function and
features. Through PC connection, HY-IDE can carry out emulation, debugging,
program…etc. function. As illustrated in Figure 1.
The actual connection way of HY-IDE boards connected to HY-IDE software can be
referred to Figure 1- 1.
The numbers of HY-IDE boards was listed as follows:
Model No.
DK02
DK03
Target Board
A09001-1
A11022-1
ICE Board
A09001-2
A11022-2
USB Control Board
A09001-3
A11022-3
Board
The following statement can be referred when using development kit, HY11S14-DK02
and HY11S14-DK03. The difference between DK02 and DK03 will be specified particularly.
.
PS
2
USB
DK02
DK03
Figure 1
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page4
HY11S14
HY-IDE Hardware User’s Manual
DK02
DK03
Figure 1- 1
.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page5
HY11S14
HY-IDE Hardware User’s Manual
2. HY-IDE USB Control Board
2.1. Diagram
HY-IDE USB control board is the bridge that connecting PC and HY-IDE ICE Board.
Users can emulate HY11P Series products’ function and implement programming OTP
products in the engineering stage by the control board, as shown in Figure 2.
.
Figure 2
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page6
HY11S14
HY-IDE Hardware User’s Manual
2.2. Circuit Description
Below is the description of Figure 2 connector：

J4 : Adapter 9V Input
The internal is negative and the external is positive, providing programming power
source (must be connected while OTP programming).
 U7 : USB Port and PC End Connector
Download program for emulation debug function
Download programming program for HY11P Series products
 J1 : HY-ICE Board Control Port
PIN 1 ICESDO
connects ICE_SDO of HY11S14
PIN 2 ICESDI
connects ICE_SDI of HY11S14
PIN 3 ICESCS
connects ICE_CS of HY11S14
PIN 4 VDD
connects ICE_VCC of HY11S14
PIN 5 ICESCK
connects ICE_SCK of HY11S14
PIN 6 VSS
connects ICE_VSS of HY11S14
 P6 : HY11P Series Programming Control Port
PIN 1 VPP(6V)
connects VPP of the IC
PIN 2 ICECK
connects PSCK of the IC
PIN 3 ICESDI
connects PSDI
. of the IC
PIN 4 ICESDO
connects PSDO of the IC
PIN 5 VDD(3V)
connects VDD of the IC
PIN 6 VSS
connects VSS of the IC
 S1 : Program, IC Programming Button
 S2 : Blank Check, IC Blank Check Button
 D4 : Two color LED;
Red LED：OTP programming, Blank Check…. execution error light
Green LED：OTP programming, Blank Check…execution success light
Green LED：USB or Adapter is powered on
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page7
HY11S14
HY-IDE Hardware User’s Manual
3. HY-IDE ICE Board
3.1. Diagram
HY-IDE ICE Board is the chip board of HY11S14. Its main function is to carry out
emulation of HY11P Series Products. This ICE chip can directly emulate HY11P1X
Series, HY11P2X Series, HY11P3X Series, HY11P4X Series and HY11P5X Series. The
diagram of HY-IDE ICE Board of DK02 is shown as Figure 3 and HY-IDE ICE Board of
DK03 is shown as Figure 4.
J2
J1
1 2 3
1 2 3
J1
1-2
1-2
11PXX
2-3
2-3
55
55
56
56
53
53
54
54
51
51
52
52
49
49
50
50
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
1 2
47
47
48
48
.
33
33
34
34
103 105 107 109 111 113 115 117 119 121 123 125 127
103 105 107 109 111 113 115 117 119 121 123 125 127
104 106 108 110 112 114 116 118 120 122 124 126 128
104 106 108 110 112 114 116 118 120 122 124 126 128
57
57
58
58
59
59
60
60
61
61
62
62
97 99 101
97 99 101
98100102
98100102
63
63
64
64
J2
11S14
Power Select
S1
Switch
VIN
ON
Remarks
VIN~3V
VDD_bat
ON
VDD_bat~3V
VDD_i
ON
VDD_i~3V
Figure 3
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page8
J5
VIN
VDD_bat~3V
VDD_i
ON
VDD_i~3V
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58
103 105 107 109 111 113 115 117 119 121 123 125 127
VIN
VDD_bat
49
49
50
50
47
47
48
48
ON
45
45
46
46
VIN~3V
VDD_bat
43
43
44
44
ON
41
41
42
42
Switch
VIN
104 106 108 110 112 114 116 118 120 122 124 126 128
VDD_i
39
39
40
40
Power Select
104 106 108 110 112 114 116 118 120 122 124 126 128
VDD_bat
37
37
38
38
Remarks
S1
103 105 107 109 111 113 115 117 119 121 123 125 127
35
35
36
36
59
59
60
60
61
61
62
62
63
63
64
64
97 99 101
97 99 101
98100102
98100102
.
APD-HYIDE005-V04_EN
page9
© 2009-2012 HYCON Technology Corp
www.hycontek.com
33
33
34
34
1 2
U2
SRAM
U3
SRAM
U4
HY11S14
HY-IDE Hardware User’s Manual
Figure 4
HY11S14
HY-IDE Hardware User’s Manual
3.2. Circuit Description
Below is the description of Figure 3 connector：
 J4：Connects the J1 PS2 communication port of HY-IDE USB Control Board. PC

gives commands to HY11S14 through Control Board. It can download program to
SRAM6 and can perform single execution, Free RUN…etc. debugging functions.
S1：ICE board power selection (voltage comes from the USB Control Board)
VIN – when it switched to ON, it represents VIN~3V voltage.
VDD_bat – when it switched to ON, it represents VDD_bat~3V voltage.
VDD_i – when it switched to ON, it represents VDD_i~3V voltage.
 Setup Ways of Power Selection:
ICE Board power can be supplied by PC through USB or from external power
sources;
When it is powered by USB, the switches of S1 VDD_bat and VDD_i , must be
turned to ON.
When it is powered via external power source, it must be connected though
HY-IDE Target Board V1 and the switch of VDD_bat must be turned to ON.
 J5: Can set up whether to short VIN and VDD_bat



J6: For DK03, CR1 must be shorted,
U3, U4: SRAM.
.
J1, J2: Capacity selection of the emulation chip (For DK02)
The ROM Size of HY11S14 is 16k Word (32K Byte). So, when HY11S14 is chosen,
J1 PIN 1-2 and J2 PIN 1-2 must be shorted.
When using HY11P Series products of which ROM Size is under 8K Word (16K
Byte), J1 PIN 2-3 and J2 PIN 2-3 must be shorted.
 CR1, R1, C1 & C2: Connects external Crystal and other peripheral capacitors or
resistors.
 C4: VDD power input regulated capacitor is recommended to keep in between
1uF to 10uF
 C5: VLCD power output regulated capacitor is recommended to keep in between
1uF to 4.7uF
 C6 and C7: Analog power regulated capacitor
In order to enhance the operation performance of ADC, the regulated capacitor is
suggested to locate as closer to the pin as possible.
C6: VDDA capacitor 1uF ~ 10uF; C7: ACM capacitor 47nF ~ 100nF.
 C8 and C9 : ADC Input Filter Capacitor
In order to enhance the operation performance of ADC, the filter capacitor is
suggested to locate as closer to the pin as possible.
C8 : ADC Input filter capacitor (AI0 – AI1) 0.1uF.
 C9 : ADC Reference filter capacitor (AI2 – AI3) 0.1uF.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page10
HY11S14
HY-IDE Hardware User’s Manual

RST Circuit：Is demonstrated as in Figure 5.
Figure 5
.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page11
HY11S14
HY-IDE Hardware User’s Manual
3.3. Circuit Diagram
The Circuit Diagram of DK02 can be referred to Figure 6, the Circuit Diagram of DK03
can be referred to Figure 7.
VDD_i
C3
0.1uF
C4
10uF
VSS_i
R2 VDD_i
CR1
4MHz
10uF
VSS_i
PT2.0
PT2.1
PT2.2
PT2.3
PT2.4
PT2.5
PT2.6
PT2.7
C5
VLCD
4.7uF
U1
HY11S14_LQFP128
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SBM_SEL/ICE_ADR15
ICE_ADR14
ICE_ADR13
ICE_ADR12
ICE_ADR11
ICE_ADR10
ICE_ADR9
ICE_ADR8
ICE_ADR7
ICE_ADR6
ICE_ADR5
ICE_ADR4
ICE_ADR3
ICE_ADR2
ICE_ADR1
ICE_ADR0
ICE_DA7
ICE_DA6
ICE_DA5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
_SBM-SEL
_ADR14
_ADR13
_ADR12
_ADR11
_ADR10
_ADR9
_ADR8
_ADR7
_ADR6
_ADR5
_ADR4
_ADR3
_ADR2
_ADR1
_ADR0
_DA7
_DA6
_DA5
J4
PS2-6PIN
S
1
2
4
5
_VSS_ram
U2A
7400
U2B
7400
3
6
9
10
12
13
14
_ADR14
U2C
7400
U2D
7400
J1
SBMSel
8
11
7
_VSS_ram 1
_VSS_ram 2
_ADR7 3
_ADR6 4
_ADR5 5
_ADR4 6
_ADR3 7
_ADR2 8
_ADR1 9
_ADR0 10
_DA0
11
12
_DA1
13
_DA2
_VSS_ram 14
1
_ADR12 2
_ADR7 3
_ADR6 4
_ADR5 5
_ADR4 6
_ADR3 7
_ADR2 8
_ADR1 9
_ADR0 10
_DA0
11
_DA1
12
_DA2
13
_VSS_ram 14
_SBM-SEL
VDD_bat _VSS_ram
C10
0.1uF
_VCC_ram
6
5
4
_VSS_ram
Power Sel
S1
VDD_bat
VIN
VDD_bat
VIN 1
VIN VDD_bat
2
VDD_bat VDD_i
3
VDD_i
J5
2
1
VDD_Bat
_CSRAM
U3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
62256
U4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
62256
Title
A4
Size
J2
CSSel
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
*. ICE Memory NET
VDD_bat
_WE
_ADR13
_ADR8
_ADR9
_ADR11
_RD
_ADR10
_CSRAM_S
_DA7
_DA6
_DA5
_DA4
_DA3
_CS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD_bat
_WE
_VSS_ram
_ADR8
_ADR9
_VSS_ram
_RD
_ADR10
_CSSBM
_DA7
_DA6
_DA5
_DA4
_DA3
SBMMemory
A09001-2
Number
HY11S14 ICE Board
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Program Memory
1
2
3
1
R1
1M
C6
C7
NC
VDD
PT2.0/XTO
PT2.1/XTI
PT2.2/PFD/PWM0/CPAI0
PT2.3/CPAI1/PWM1/TMCKI
PT2.4/CCP0/CPAI2/PWM2
PT2.5/CCP1/CPAI3/PWM3
PT2.6/CPAI4/CPAO
PT2.7/CPAI5/CPAO
NC
VDDA
ACM
OPO
AI0/PT4.0
AI1/PT4.1
AI2/PT4.2
AI3/PT4.3
AI4/PT4.4
AI5/PT4.5
AI6/PT4.6
AI7/PT4.7
AI8/PT5.0
AI9/PT5.1
AI10/PT5.2
AI11/PT5.3
AI12/PT5.4
AI13/PT5.5
AI14/PT5.6
AI15/PT5.7
NC
VSS
HY11S14_128
VIN
VDD_bat
R7
R6 47K
47K
_SDO
_SDI
_SCS
_SCK
1
2
3
1
C1
22pF
C2
22pF
VSS_i
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
R3
0
VDD_bat
C14
1uF
_VSS_ram
_VCC_ram
R5
47K
_VSS_ram
2
VSS_i
被動元件近IC
100nF
VDDA
ACM
OPO
AI0
C8
0.1uF AI1
AI2
C9
0.1uF AI3
AI4
AI5
AI6
AI7
AI8
AI9
AI10
AI11
AI12
AI13
AI14
AI15
VSS_i
_VSS_ram
VDD_i
R4
100K
C13
1nF
VSS_i
_VCC_ram
J3
ICE Signal
1
2
3
4
5
6
VDD_bat
C11
0.1uF
_VSS_ram
VDD_bat
C12
0.1uF
_VSS_ram
V02
Revision
APD-HYIDE005-V04_EN
page12
© 2009-2012 HYCON Technology Corp
www.hycontek.com
.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
_ V S S _ ram 2 0
_ SD I
21
_ SD O
22
23
_ SC K
24
_ SC S
_ CS 2 5
_ RD 2 6
_WE 27
_ DA 0 2 8
_ DA 1 2 9
_ DA 2 3 0
_ DA 3 3 1
_ DA 4 3 2
1 29
1 30
1
C OM 0
C OM 1
C OM 2
C OM 3
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S EG 1 0
S EG 1 1
S EG 1 2
S EG 1 3
S EG 1 4
S EG 1 5
S EG 1 6
S EG 1 7
S EG 1 8
S EG 1 9
S EG 2 0
S EG 2 1
S EG 2 2
S EG 2 3
S EG 2 4
S EG 2 5
S EG 2 6
S EG 2 7
S EG 2 8
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
V LC D
C OM 0
C OM 1
S EG 0 / CO M 2
S EG 1 / CO M 3
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S EG 1 0
S EG 1 1
S EG 1 2
S EG 1 3
S EG 1 4
S EG 1 5
S EG 1 6
S EG 1 7
S EG 1 8
S EG 1 9
S EG 2 0
S EG 2 1
S EG 2 2
S EG 2 3
S EG 2 4
S EG 2 5
S EG 2 6
S EG 2 7
S EG 2 8
V PP / R ST
P T1 .0 / IN T 0/ C P AI6 / PS C K
P T1 .1 / IN T 1/ C P AI7 / SC E / PS D I
P T1 .2 / IN T 2/ S D I/ S V SIN
P T1 .3 / TS T /IN T 3/ R X
P T1 .4 / IN T 4/ T X
P T1 .5 / IN T 5/ S D O/ P S D O
P T1 .6 / IN T 6/ S C K
P T1 .7 / IN T 7/ B Z
P T3 .0
P T3 .1
P T3 .2
P T3 .3
P T3 .4
P T3 .5
P T3 .6
P T3 .7
NC
IC E_ V CC
IC E_ V SS
IC E_ S DI
IC E_ S DO
IC E_ S CK
IC E_ C S
IC E_ C S0
IC E_ R D
IC E_ W E
IC E_ D A0
IC E_ D A1
IC E_ D A2
IC E_ D A3
IC E_ D A4
V IN
V IN
V PP
P T1 .0
P T1 .1
P T1 .2
P T1 .3
P T1 .4
P T1 .5
P T1 .6
P T1 .7
P T3 .0
P T3 .1
P T3 .2
P T3 .3
P T3 .4
P T3 .5
P T3 .6
P T3 .7
Figure 6
HY11S14
HY-IDE Hardware User’s Manual
VSS_i
C1
C2
C4
10uF VSS_i
PT2.0
PT2.1
PT2.2
PT2.3
PT2.4
PT2.5
PT2.6
PT2.7
VSS_i
VDD_i
C7
C6
10uF
CR1
8MHz
R2
J6
C3
0.1uF
VDD_i
VSS_i
1M
22pF R1
22pF
被動元件近IC
100nF
VDDA
ACM
OPO
AI0
C8
0.1uF AI1
AI2
C9
0.1uF AI3
AI4
AI5
AI6
AI7
AI8
AI9
AI10
AI11
AI12
AI13
AI14
AI15
VSS_i
_VSS_ram
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
R3
0
C5
VLCD
4.7uF
U1
NC
VDD
PT2.0/XTO
PT2.1/XTI
PT2.2/PFD/PWM0/CPAI0
PT2.3/CPAI1/PWM1/TMCKI
PT2.4/CCP0/CPAI2/PWM2
PT2.5/CCP1/CPAI3/PWM3
PT2.6/CPAI4/CPAO
PT2.7/CPAI5/CPAO
NC
VDDA
ACM
OPO
AI0/PT4.0
AI1/PT4.1
AI2/PT4.2
AI3/PT4.3
AI4/PT4.4
AI5/PT4.5
AI6/PT4.6
AI7/PT4.7
AI8/PT5.0
AI9/PT5.1
AI10/PT5.2
AI11/PT5.3
AI12/PT5.4
AI13/PT5.5
AI14/PT5.6
AI15/PT5.7
NC
VSS
VDD_i
R4
100K
C13
1nF
VSS_i
HY11S14_LQFP128
VDD_bat
C14
1uF
_VSS_ram
_VCC_ram
J3
ICE Signal
1
2
3
4
5
6
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SBM_SEL/ICE_ADR15
ICE_ADR14
ICE_ADR13
ICE_ADR12
ICE_ADR11
ICE_ADR10
ICE_ADR9
ICE_ADR8
ICE_ADR7
ICE_ADR6
ICE_ADR5
ICE_ADR4
ICE_ADR3
ICE_ADR2
ICE_ADR1
ICE_ADR0
ICE_DA7
ICE_DA6
ICE_DA5
R5
47K
HY11S14_128
VIN
VDD_bat
R7
R6 47K
47K
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
_V S S_ ram 20
_S D I
21
_S D O 22
_S CK
23
24
_S CS
_CS 25
_RD 26
_W E 27
_D A 0 28
_D A 1 29
_D A 2 30
_D A 3 31
_D A 4 32
12 9
13 0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
4
6
8
10
12
J4
1
3
5
7
9
11
J5
3
6
_VSS_ram
_VCC_ram
GND
9
10
12
13
U2C
SN74HC00
U2D
PS2-6PIN
J7
Power Sel
S1
SN74HC00
1
2
3
4
5
6
VIN
VDD_bat
VIN 1
VDD_bat2
VDD_i 3
_SCK
_SDO
_SDI
_SCS
VDD_Bat
2
1
VIN
VDD_bat
VDD_i
VDD_bat
_VSS_ram
C10
1 7
0.1uF
U2B
SN74HC00
U2A
14 2
1
2
4
5
SN74HC00
_VSS_ram
_VCC_ram
_SCK
_SDO
_SDI
_SCS
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
VCC
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
_SBM-SEL
_ADR14
_ADR13
_ADR12
_ADR11
_ADR10
_ADR9
_ADR8
_ADR7
_ADR6
_ADR5
_ADR4
_ADR3
_ADR2
_ADR1
_ADR0
_DA7
_DA6
_DA5
.
ICE PIN
8
11
6
5
4
_CSRAM
_VCC_ram
S
_VSS_ram
_ADR14 1
_ADR12 2
_ADR7 3
_ADR6 4
_ADR5 5
_ADR4 6
_ADR3 7
_ADR2 8
_ADR1 9
_ADR0 10
_DA0
11
_DA1
12
_DA2
13
_VSS_ram14
_VSS_ram 1
_VSS_ram 2
_ADR7 3
_ADR6 4
_ADR5 5
_ADR4 6
_ADR3 7
_ADR2 8
_ADR1 9
_ADR0 10
11
_DA0
12
_DA1
13
_DA2
_VSS_ram 14
Title
Size
A4
Dt
U3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
62256
U4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
62256
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VDD_bat
_WE
_ADR13
_ADR8
_ADR9
_ADR11
_RD
_ADR10
_CSRAM
_DA7
_DA6
_DA5
_DA4
_DA3
*. ICE Memory NET
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD_bat
_WE
_VSS_ram
_ADR8
_ADR9
_VSS_ram
_RD
_ADR10
_CSSBM
_DA7
_DA6
_DA5
_DA4
_DA3
Program Memory
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SBM Memory
HY11S14 ICE Board
2011
A11022-2
Number
25 N
VDD_bat
C11
0.1uF
_VSS_ram
VDD_bat
V01
Revisi
C12
0.1uF
f
_VSS_ram
Sh t
APD-HYIDE005-V04_EN
page13
© 2009-2012 HYCON Technology Corp
www.hycontek.com
COM 0
COM 1
COM 2
COM 3
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S EG 10
S EG 11
S EG 12
S EG 13
S EG 14
S EG 15
S EG 16
S EG 17
S EG 18
S EG 19
S EG 20
S EG 21
S EG 22
S EG 23
S EG 24
S EG 25
S EG 26
S EG 27
S EG 28
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
V LCD
COM 0
COM 1
S EG 0/CO M2
S EG 1/CO M3
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S EG 10
S EG 11
S EG 12
S EG 13
S EG 14
S EG 15
S EG 16
S EG 17
S EG 18
S EG 19
S EG 20
S EG 21
S EG 22
S EG 23
S EG 24
S EG 25
S EG 26
S EG 27
S EG 28
V PP /RS T
P T1. 0/I NT 0/CP AI 6/P SCK
P T1. 1/I NT 1/CP AI 7/S CE /P SD I
P T1. 2/I NT 2/S D I/S VS IN
P T1. 3/T ST /IN T 3/RX
P T1. 4/I NT 4/T X
P T1. 5/I NT 5/S D O/PS DO
P T1. 6/I NT 6/S CK
P T1. 7/I NT 7/BZ
P T3. 0
P T3. 1
P T3. 2
P T3. 3
P T3. 4
P T3. 5
P T3. 6
P T3. 7
NC
ICE_ VCC
ICE_ VS S
ICE_ SD I
ICE_ SD O
ICE_ SCK
ICE_ CS
ICE_ CS 0
ICE_ RD
ICE_ W E
ICE_ DA 0
ICE_ DA 1
ICE_ DA 2
ICE_ DA 3
ICE_ DA 4
V IN
V IN
V PP
P T1. 0
P T1. 1
P T1. 2
P T1. 3
P T1. 4
P T1. 5
P T1. 6
P T1. 7
P T3. 0
P T3. 1
P T3. 2
P T3. 3
P T3. 4
P T3. 5
P T3. 6
P T3. 7
Figure 7
HY11S14
HY-IDE Hardware User’s Manual
4. HY-IDE Target Board
4.1. Diagram
HY-IDE Target Board facilitates users to design circuit and to connect the circuit to the
ICE Board. Target Board equips with basic circuit and components, according to circuit
requirements, users can connect the circuit and the self-designed PCB board through I/O or
Analog Ports. The relative peripherals include oscillator (CR1, CR2), EEPROM (U2),
MAX232 (U3), RS232 connector (CON1), Regulator (U4), LED (D2~D9), Key Switch
(S3~S8) and Buzzer (U5). Target Board of DK2 is illustrated as in Figure 8. Target Board of
DK03 is illustrated as in Figure 9.
WP Select
74
74
73
73
72
72
71
71
15
70
70
69
69
16
68
68
67
67
17
18
18
20
EXT 3
2
3V 1
21
66
66
65
65
S1
7
8
9
10
12
11
8
7
16
17
18
19
20
21
22
23
24
4
15
3
14
2
13
1
26
25
27
28
29
30
31
32
33
34
.
55
55
56
56
CR1
CR2
JP12
36
37
38
39
40
1 3 5 7 9 11 13
1 3 5 7 9 11 13
2 4 6 8 10 12 14
2 4 6 8 10 12 14
S5_PT1.1
1
2
3
4
5
6
VPP
PT1.0
PT1.1
PT1.5
VDD
VSS
U5
J7
J8
2 J9
1
2
4
6
8
BZ
1
3
5
7
CON1
J13
POWER
15 17 19 21 23 25 27 29 31 VIN
15 17 19 21 23 25 27 29 31VIN
S6
S8
1
2
3
1
2
U3
JP9
2
6
16 18 20 22 24 26 28 30 32 VDDBAT
16 18 20 22 24 26 28 30 32 VDDBAT
S7
1
2
4
6
8
10
12
1
3
5
7
9
11
ON
RXD
MAX 232
35
S4_PT1.0
JP5 1
VSSBAT
U4
J1
VDD
SDI
SCK
SDO
CS
VSS
J5
S3_RST
2
1
2
V1 1
J2 S2
SPI
76
76
75
75
14
OTP
78
78
77
77
13
Current
80
80
79
79
12
63
63
64
64
82
82
81
81
11
61
61
62
62
ON
84
84
83
83
10
GS2612
6
6
103 105 107 109 111 113 115 117 119 121 123 125 127
5
5
103 105 107 109 111 113 115 117 119 121 123 125 127
4
4
104 106 108 110 112 114 116 118 120 122 124 126 128
3
3
104 106 108 110 112 114 116 118 120 122 124 126 128
2
1
2
1
JP1
97 99 101
97 99 101
98100102
98100102
JP3
86
86
85
85
9
59
59
60
60
20
19
11
88
88
87
87
8
57
57
58
58
18
17
12
9
90
90
89
89
7
53
53
54
54
16
10
7
92
92
91
91
6
51
51
52
52
15
8
5
5
VBAT
JP4 1
49
49
50
50
14
6
3
94
94
93
93
4
47
47
48
48
13
4
1
3
45
45
46
46
12
96
96
95
95
2
JP2
2
43
43
44
44
11
JP6
1
41
41
42
42
9
10
D9
U2
39
39
40
40
8
D8
J6
37
37
38
38
7
D7
35
35
36
36
6
D6
33
33
34
34
5
D5
S9
EEPROM Sel
1
2
3
J3
4
3
D4
ON
24C02
2
1
D3
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
JP1
654321
JP8
D2
S10
TXD
7
3
8
4
9
5
Rs232 Sel
Figure 8
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page14
HY11S14
HY-IDE Hardware User’s Manual
JP8
D2
JP1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
D3
ON
EEPROM Sel
1
2
3
J3
D4
D5
D6
EXT 3
2
3V 1
D7
J6
D8
1
D9
JP6
S9
2
4
6
8
10
12
1
3
5
7
9
11
2
3
4
5
6
7
8
9
96
96
95
95
94
94
93
93
92
92
91
91
90
90
89
89
88
88
87
87
86
86
85
85
84
84
83
83
82
82
81
81
ON
J16
10
80
80
79
79
11
12
78
78
77
77
76
76
75
75
13
74
74
73
73
14
72
72
71
71
15
70
70
69
69
16
68
68
67
67
17
18
18
20
21
66
66
65
65
2
1
U2
VBAT
JP4 1
J2 S2
JP5 1
VSSBAT
U4
J1
S1
VDD
SDI
SCK
SDO
CS
VSS
JP3
JP2
CR1
2
V1 1
VPP
PT1.0
PT1.1
PT1.5
VDD
VSS
CR2
U5
1
2
3
4
5
6
J7
J8
2 J9
1
JP1
BZ
1 3 5 7 9 11 13
1 3 5 7 9 11 13
2 4 6 8 10 12 14
2 4 6 8 10 12 14
2
4
6
8
10
12
1
3
5
7
9
11
15 17 19 21 23 25 27 29 31 VIN
15 17 19 21 23 25 27 29 31VIN
16 18 20 22 24 26 28 30 32 VDDBAT
16 18 20 22 24 26 28 30 32 VDDBAT
.
S6
S7
S8
1
2
JP9
3
ON
RXD
2
4
6
8
10
12
1
3
5
7
9
11
1
2
S10
TXD
Rs232 Sel
J5
S3_RST S4_PT1.0 S5_PT1.1
J13
POWER
MAX 232
JP12
Figure 9
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page15
HY11S14
HY-IDE Hardware User’s Manual
4.2. Circuit Description
 Power System：
ICE power system can be powered by 3V regulated by HY-IDE USB Control Board
or via external power input (external input power cannot exceed 3.6V that defined
in HY11P series datasheets). When performing emulation on ICE, it can be
powered by connecting U7 of HY-IDE USB Control Board via USB wire to PC end.
USB power and external power is described as follows:
 USB Power:
When the system is powered by USB, the VDD_bat and VDD_i options of S1
switch of HY-IDE ICE Board must be turned to ON. Then it can be powered by the
USB via regulated 3V of the Regulator.
When measuring IC current consumption, the option of VIN and VDD_bat
must be switched to ON, supplying 3V power from regulator via USB and the
current consumption is measured by J1 of the Target Board.
 External Power:
When using external power, users must notice that the VIN, VDD_i options of
the HY-IDE ICE Board S1 switch must be switched to OFF status.
The external power can be inputted via VBAT positive end of JP4 of HY-IDE
Target Board, the negative end is. inputted by VSSBAT. S2 is the power on/off
switch control.
 J2: Power selection (choose whether the whole system power passes
through Regulator (U4))
J2 PIN 1-2 short represents when VBAT external power input to U4, the
voltage is regulated to 3V output, supplying VDD_i for the whole system
(the output voltage is changeable through modifying R8, R14 and R15.
The equation is: VOUT  1.240V  (1 
R8  R14
)
R15
).
J2 PIN 2-3 short represents VBAT power is directly inputted to VDD_i.
(Please note that the power should not exceed the specification of 3.6V)
 J1: can bridge current meter to test the whole VDD_i current
consumption. It must be short circuit when it is not connected to the current
meter, as shown in Figure 10.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page16
HY11S14
HY-IDE Hardware User’s Manual
*. POWER NET
J1
Current test
J2
1
2
EXT
VDD_bat
3
2
3V
1
C7
10uF
C6
0.1uF
1N4001
S2
5
ON1
COM1
1
OFF1
4
6
ON2
COM2
2
OFF2
VSS_i
VDD Sel
VDD_i
3
D1
R8
100K
電流錶
C21
10uF
R14
42.2K
R15
100K
1
2
3
4
EN
IN
OUT
ADJ
U4
GND
GND
GND
GND
GS2612
JP4
VBAT
VIN
JP5
VSSBAT
8
7
6
5
VSS_i
VSS_i
Figure 10

J7：SPI communication port, as shown in
Figure 11.
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
VDD
PT1.2(SDI)
PT1.6(SCK)
PT1.5(SDO)
PT1.1(CS)
VSS
.
Figure 11

J8 : OTP programming port
When product programming is implemented, HY-IDE ICE Board must be
disconnected and the to be programmed chip must be connected. Through
connecting J8 pin of HY-IDE Target Board to the J5 pin of HY-IDE USB
Control Board, the programming function of HY-IDE Control Board can then
program HY11P series chip, as shown in
Figure 12.
PIN 1 VPP (PIN 1)
PIN 2 PT1.0 (PIN 2)
PIN 3 PT1.1 (PIN 3)
PIN 4 PT1.5 (PIN 7)
PIN 5 VDD (PIN 98)
PIN 6 VSS (PIN 128)
Figure 12
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page17
HY11S14
HY-IDE Hardware User’s Manual
 CON1: UART communication port (RS232); in common use for 9-PIN
connector, as illustrated in Figure 13.
J13: is the power input JUMP for U3 MAX232. If short, it is connected with J1
VDD_bat power. MAX232 is a signal voltage conversion IC, it can convert I/O
power signal to standard RS232 potential signal.
S10: is the connecting pin switch of RS232. RXD means connecting to PT1.3,
TXD means connecting to PT1.4
.
Figure 13

J9: Buzzer JUMP that connects to PT1.7 signal, as shown in Figure 14.
Figure 14
 U2: EEPROM 24C02, as shown in Figure 15.
S9: When using EEPROM 24C02 to save the calibration parameters, PIN 1-2
of S9 must be started.
J3: Short PIN 1-2 when it is prohibit writing 24C02.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page18
HY11S14
HY-IDE Hardware User’s Manual
Figure 15

J6, JP11: LCD pin, as shown in Figure 16.
.
Figure 16
The LCD panel on HY-IDE Target Board is HYCON Technology’s own
mold specification, the panel symbol and pin definition is shown as Figure 17
and Figure 18. Detailed panel specification is:
Operation Voltage：3.0V
Visible angle：60
Operation Frequency：60Hz
Bias：1/3 bias
Waveform：1/4 duty
Pin：90 degree
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page19
HY11S14
HY-IDE Hardware User’s Manual
COM1
COM2
COM3
COM4
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17
1A
1E
2A
2E
3A
3E
4A
4E
5A
5E
6A
6E
S1
S5
S10
S9
S18
1B
1F
2B
2F
3B
3F
4B
4F
5B
5F
6B
6F
S2
S6
S11
S14
S19
1C
1G
2C
2G
3C
3G
4C
4G
5C
5G
6C
6G
S3
S7
S12
S15
S20
1D
1H
2D
2H
3D
3H
4D
4H
5D
5H
6D
S17
S4
S8
S13
S16
S21
Figure 17
70mm
m A
K
M V
g
TARE
ZERO
27mm
17.78mm
8.89mm
1
21
0.812mm
PIN
1
2
3
4
5
I/O
COM1
COM2
COM3
COM4
PIN
12
13
14
I/O
SEG8
SEG9
SEG10
.
2.54mm
6
7
8
9
10
11
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
15
16
17
18
19
20
21
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
Figure 18
 CR1, R1, C1 and C2: Connecting external crystal oscillation circuit, as
shown Figure 19.
HY-IDE Target Board is connected to CR1-4MHZ and CR2-32768Hz
oscillator.
S1: Control PT2.0 pin and connect to CR1 or CR2 device; their switches
cannot be started at the same time.
PIN1 ON, represents connecting to 4MHZ oscillation circuit
PIN2 ON, represents connecting to 32768HZ oscillation circuit
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page20
HY11S14
HY-IDE Hardware User’s Manual
Figure 19
 JP9, JP12: PT1, PT3 Port of DK02 is shown as Figure 20. PT1, PT3 Port
of DK03 is shown as Figure 21.
S4~S8: button, S3-RST, S4-PT1.0, S5-PT1.1
J5: is the expandable pin for S6, S7, and S8 button
.
Figure 20
C24
*. PT1,PT3 I/O NET
VDD_i
VSS_i
0.1uF
VDD_i
S4
PT1.0
PT1.2
PT1.4
PT1.6
PT1.0
S5 PT1.1
VSS_i PT1.1
VSS_i
VDD_i
S6
VDD_i
2
4
6
8
10
12
J5
PT1.1
PT1.3
PT1.5
PT1.7
1
PT3.0
3
PT3.2
5
PT3.4
7
PT3.6
9
11
I/O(PT3)
PT1.1
PT1.3
PT1.5
PT1.7
VSS_i
VDD_i
2
4
6
8
10
12
S7
1
2
3
S8
Key
I/O(PT1)
JP12
PT3.0
PT3.2
PT3.4
PT3.6
VSS_i
JP9
VDD_i
PT1.0 1
PT1.2 3
PT1.4 5
PT1.6 7
VSS_i 9
11
PT3.1
PT3.3
PT3.5
PT3.7
PT3.1
PT3.3
PT3.5
PT3.7
VSS_i
VDD_i
J7
1
2
3
4
5
6
SPI
PT1.2
PT1.6
PT1.5
PT1.1
SDI(PT1.2)
SCK(PT1.6)
SDO(PT1.5)
CS(PT1.1)
VSS_i
VSS_i
Figure 21
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page21
HY11S14
HY-IDE Hardware User’s Manual
 JP8: PT2 Port is shown as Figure 22.
D2~D9: is the default pin for PT2.0~PT2.7 LED. Using different PT2 pin, JP8
must be shorted.
Figure 22
 D10: Is small package, SOT-23, Signal diode, as shown in Figure 23.
J10: Pump control signal
J12: Connecting JUMP of PT2.2 pin. PFD frequency output as PUMP voltage
control.
J11: Pump voltage output
.
Figure 23
 Analog Port: For DK02, as shown in Figure 24. For DK03, as shown in
Figure 25.
JP3: Analog port, providing external sensor input signal connection.
Other ports are all expandable analog signal input; they can be designed
according to user’s application.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page22
HY11S14
HY-IDE Hardware User’s Manual
Figure 24
.
Figure 25
 C10~C15: Filter capacitor, shown as Figure 26
 . This filter capacitor provides ADC input signal source or it can filter
voltage reference source
Figure 26
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page23
HY11S14
HY-IDE Hardware User’s Manual
4.3. Circuit Diagram
The Circuit Diagram of DK02 can be referred to Figure 27, the Circuit Diagram of
DK03 can be referred to Figure 28.
VDDA
R1
10k
JP1
1
3
ADREF
OPNVS
OPPVS
C8
0.1uF
VCC
WP
SCL
SDA
AI2
2 AI2
AI3
4 AI3
R9
RES1
R10
RES1
VDDA
AI0
AI1
VSS_i
JP6
1
3
5
7
9
11
JP2
1
3
5
7
ADINPUT
C1
CAP
R11
RES1
R12
2
4
6
8
10
12
RES1
OPNET
VSS_i WP select
J3
1
1
2
2
3
3
*. EEPROM NET
OP0O_1
OPNVS
OPNIN
OPPVS
OPPIN
OPPGND
VDD_bat
VDD_bat
8
7
6
5
2
4
6
8
VDDA
AI0
AI1
VSS_i
OPPGND
OP0O_1
OPNVS
C9
OPNIN
OPPVS
VSS_i
OPPIN
OPPGND
VDD_bat
R4
10K
J4
OPO
R13
135
ACM
27nF
R5
10K
2
4
6
8
10
12
14
16
18
20
*. 框內電路靠近JP3
*. JP3靠近晶片
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
J12
PFDSel
VIN
R19
Q1
B2N3906
VDD_i
3
VSS_i
22pF
C3
K/AK
C10~C15 IC
Analog Net
A
C25
BAV99
R20
1
4.7uF
C22
0.1uF
VSS_i
*. PT2 I/O NET
VSS
PT2.7
PT2.6
PT2.5
PT2.4
PT2.3
PT2.2
PT2.1
PT2.0
VDD
D10
VDDA
ACM
OPO
AI0
AI1
AI2
AI3
AI4
AI5
AI6
AI7
AI8
AI9
AI10
AI11
AI12
AI13
AI14
AI15
*. Analog NET
JP3
VDDAVDDA
1
ACM ACM
3
OPO OPO
5
AI0 AI0
7
AI1 AI1
9
AI2 AI2
11
AI3 AI3
13
AI4 AI4
15
AI5 AI5
17
AI6 AI6
19
AI7 AI7
21
AI8 AI8
23
AI9 AI9
25
AI10 AI10
27
AI11 AI11
29
AI12 AI12
31
AI13 AI13
33
AI14 AI14
35
AI15 AI15
37
VSS_i
39
2
VSS_i Analog Port VSS_i
J10
Pump Control
R18
10K
PT2.2
VSS_i
PT2.7
PT2.6
PT2.5
PT2.4
PT2.3
PT2.2
PT2.1
PT2.0
VDD_i
C2
C4
1
2
22pF
R6
S1
IC
C11
C12
4
3
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VDD_i
PT2.0
PT2.1
PT2.2
PT2.3
PT2.4
PT2.5
PT2.6
PT2.7
VDDA
ACM
OPO
AI0
AI1
AI2
AI3
AI4
AI5
AI6
AI7
AI8
AI9
AI10
AI11
AI12
AI13
AI14
AI15
VSS_i
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
S3
S5 PT1.1
S4
VSS_i RST
PT1.0
VSS_i PT1.1
C15
0.1uF C14
C10 C13
22pF
C5
CR2
32768
OSC Sel
10M
22pF
CR1
4MHz
R7
1M
VSS_i
2
VSS_i
C26
0.1uF
J11
PUMP Output
PUMP Circuit
C10~C15
A I5
A I6
R2
10k
VSS_i
U2
NC
NC
NC
VSS
24C02
S9
4 SCL PT2.2
3 SDA PT2.3
VSS_i JP8
1
3
5
7
9
11
13
15
17
19
VDD_i I/O (PT2)
1
3
CE
1
R3
10k
1
2
3
4
1
2
EEPROMSel
D9
PT2.6_1
PT2.7_1
PT27
D8
PT2.5_1
PT2.0_1
PT2.4_1
PT2.3_1
PT2.2_1
PT2.1_1
PT26
D7
PT25
D6
PT24
D5
PT23
D4
PT22
D3
PT21
D2
PT20
1
3
2
1
I IC_ S D A
O PP IN O PN I N
VSS_i
VDD_i
VSS_i
HY11S14_LQFP128
J9
2
1
BZ
PT1.1
PT1.3
PT1.5
PT1.7
U5
BUZZER
VDD_i
PT1.1
PT1.3
PT1.5
PT1.7
PT3.1
PT3.3
PT3.5
PT3.7
VSS_i
PT3.1
PT3.3
PT3.5
PT3.7
VSS_i
2
4
6
8
2
4
6
8
10
12
0.1uF
C24
JP9
VDD_i
PT1.0 1
PT1.2 3
PT1.4 5
PT1.6 7
VSS_i 9
11
I/O(PT3)
I/O(PT1)
PT1.0
PT1.2
PT1.4
PT1.6
JP12
PT3.0
PT3.2 1
PT3.4 3
PT3.6 5
7
VDD_i
J8
Program
VSS_i
VDD_i
C23
10nF
R16
100K
VDD_i
HY11S14
NC
VDD
PT2.0/XTO
PT2.1/XTI
PT2.2/PFD/PWM0/CPAI0
PT2.3/CPAI1/PWM1/TMCKI
PT2.4/CCP0/CPAI2/PWM2
PT2.5/CCP1/CPAI3/PWM3
PT2.6/CPAI4/CPAO
PT2.7/CPAI5/CPAO
NC
VDDA
ACM
OPO
AI0/PT4.0
AI1/PT4.1
AI2/PT4.2
AI3/PT4.3
AI4/PT4.4
AI5/PT4.5
AI6/PT4.6
AI7/PT4.7
AI8/PT5.0
AI9/PT5.1
AI10/PT5.2
AI11/PT5.3
AI12/PT5.4
AI13/PT5.5
AI14/PT5.6
AI15/PT5.7
NC
VSS
U1
COM 0
C OM 1
C OM 2
C OM 3
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S EG 1 0
S EG 1 1
S EG 1 2
S EG 1 3
S EG 1 4
S EG 1 5
S EG 1 6
S EG 1 7
S EG 1 8
S EG 1 9
S EG 2 0
S EG 2 1
S EG 2 2
S EG 2 3
S EG 2 4
S EG 2 5
S EG 2 6
S EG 2 7
S EG 2 8
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SBM_SEL/ICE_ADR15
ICE_ADR14
ICE_ADR13
ICE_ADR12
ICE_ADR11
ICE_ADR10
ICE_ADR9
ICE_ADR8
ICE_ADR7
ICE_ADR6
ICE_ADR5
ICE_ADR4
ICE_ADR3
ICE_ADR2
ICE_ADR1
ICE_ADR0
ICE_DA7
ICE_DA6
ICE_DA5
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PT3.0
PT3.2
PT3.4
PT3.6
VSS_i
VSS_i
S6
S7
S8
J7
S6:
1
2
3
4
5
6
SPI
VIN
Key
1
2
3
J5
PT1.3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
*. PT1,PT3 I/O NET
VDD_i
SDI(PT1.2)
SCK(PT1.6)
SDO(PT1.5)
CS(PT1.1)
VSS_i
PT1.2
PT1.6
PT1.5
PT1.1
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
_SBM-SEL
_ADR14
_ADR13
_ADR12
_ADR11
_ADR10
_ADR9
_ADR8
_ADR7
_ADR6
_ADR5
_ADR4
_ADR3
_ADR2
_ADR1
_ADR0
_DA7
_DA6
_DA5
COM0
COM1
COM2
COM3
1
2
3
4
VDD_i
J1
Current test
VDD_bat
C18
J2
EXT
3
2
3V
1
VDD Sel
VSS_i
MAX232
TXD 1
RXD 2
LCD_20*4
RS232 Sel
S10
1uF
U3
1
C1+
VCC
C16
2
VS+
GND
1uF
3
MAX232
C1T1OUT
4
C2+
R1IN
5
C2R1OUT
C17
6
VST1IN
1uF RXD_PC
7
T2OUT
T2IN
8
TXD_PC
R2IN
R2OUT
C20
1uF
VSS_i
J6
LCD_20*4
COM0
COM1
COM2/SEG0
COM3/SEG1
VSS_i
C6
0.1uF
C21
10uF
C7
10uF
R8
100K
R14
42.2K
R15
100K
VSS_i
1
2
VDD_bat J13
RS232 Power
D1
EN
IN
OUT
ADJ
RS232
CON1
U4
1N4001
1
2
3
4
1
2
3
4
5
COM0
COM2
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG32
SEG34
SEG36
SEG38
SEG40
A09001-1
Number
VSS_i
8
7
6
5
6
ON2
COM2
2
OFF2
S2
5
ON1
COM1
1
OFF1
*. POWER NET
3
4
GND
GND
GND
GND
GS2612
COM1
COM3
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG33
SEG35
SEG37
SEG39
SEG41
VIN
JP4
VBAT
JP5
VSSBAT
COM1
COM3
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG33
SEG35
SEG37
SEG39
SEG41
V02
Revision
*. LCD NET
*. EUART NET
6
7
8
9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
R17
0
VSS_i
JP11
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
LCD2
HY11S14 Target Board
COM0
COM2
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG32
SEG34
SEG36
SEG38
SEG40
C19
1uF
16
15
14
13
VSS_i
12
RXD_PC
11
TXD_PC
10 TXD
9 RXD
4 PT1.4 TXD
3 PT1.3 RXD
Title
A4
Size
APD-HYIDE005-V04_EN
page24
© 2009-2012 HYCON Technology Corp
www.hycontek.com
I IC_ S CL
V LC D
COM 0
COM 1
S E G 0 / CO M 2
S E G 1 / CO M 3
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S EG 1 0
S EG 1 1
S EG 1 2
S EG 1 3
S EG 1 4
S EG 1 5
S EG 1 6
S EG 1 7
S EG 1 8
S EG 1 9
S EG 2 0
S EG 2 1
S EG 2 2
S EG 2 3
S EG 2 4
S EG 2 5
S EG 2 6
S EG 2 7
S EG 2 8
V PP / R ST
P T 1 .0 / IN T 0/ C P A I6 / PS C K
P T 1 .1 / IN T 1/ C P A I7 / SC E / PS D I
P T 1 .2 / IN T 2/ S D I/ S V SI N
P T 1 .3 / T S T /IN T 3/ R X
P T 1 .4 / IN T 4/ T X
P T 1 .5 / IN T 5/ S D O / P SD O
P T 1 .6 / IN T 6/ S C K
P T 1 .7 / IN T 7/ B Z
P T 3 .0
P T 3 .1
P T 3 .2
P T 3 .3
P T 3 .4
P T 3 .5
P T 3 .6
P T 3 .7
NC
I C E _ V CC
I C E _ V SS
IC E_ S D I
IC E_ S D O
I C E _ S CK
IC E_ C S
I C E _ C S0
IC E_ R D
IC E_ W E
IC E_ D A 0
IC E_ D A 1
IC E_ D A 2
IC E_ D A 3
IC E_ D A 4
V IN
V IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
_ V S S _ ra m 2 0
_ SD I
21
_ SD O
22
23
_ SC K
IC EC S 2 4
_ CS 2 5
_ RD 2 6
_WE 27
_ DA 0 2 8
_ DA 1 2 9
_ DA 2 3 0
_ DA 3 3 1
_ DA 4 3 2
1 29
1 30
.
V PP
P T 1 .0
P T 1 .1
P T 1 .2
P T 1 .3
P T 1 .4
P T 1 .5
P T 1 .6
P T 1 .7
P T 3 .0
P T 3 .1
P T 3 .2
P T 3 .3
P T 3 .4
P T 3 .5
P T 3 .6
P T 3 .7
1
2
3
4
5
6
2
1
VSS_i
VSS_i
9
8
7
6
5
4
3
2
I IC_ S D A
I IC_ S CL
1
2
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S EG 1 0
S EG 1 1
S EG 1 2
S EG 1 3
S EG 1 4
S EG 1 5
S EG 1 6
S EG 1 7
S EG 1 8
S EG 1 9
S EG 2 0
S EG 2 1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S EG 1 0
S EG 1 1
S EG 1 2
S EG 1 3
S EG 1 4
S EG 1 5
S EG 1 6
S EG 1 7
S EG 1 8
S EG 1 9
S EG 2 0
S EG 2 1
VSS_i
RP
470
1
Figure 27
HY11S14
HY-IDE Hardware User’s Manual
VDDA
J14 R1
10k
JP1
1
3
ADREF
OPNVS
OPPVS
C8
0.1uF
VCC
WP
SCL
SDA
AI2
2 AI2
AI3
4 AI3
R9
RES1
R10
RES1
S9
JP6
1
3
5
7
9
11
J16
VDDA
1
AI0
2
AI1
3
VSS_i
4
R4
10K
VDD_bat
OP0O_1
C9
OPNVS
OPNIN
OPPVS
VSS_i
OPPIN
OPPGND
OPPGND
ADINPUT
JP2
VDDA
1
AI0
2
AI1
3
VSS_i
4
C1
CAP
R11
RES1
R12
2
4
6
8
10
12
RES1
OPNET
VSS_i WP select
J3
1
1
2
2
3
3
*. EEPROMNET
OP0O_1
OPNVS
OPNIN
OPPVS
OPPIN
OPPGND
VDD_bat
VDD_bat
8
7
6
5
4 SCL PT2.2
3 SDA PT2.3
J4
OPO
R13
135
ACM
27nF
R5
10K
*. 框內電路靠近JP3
*. JP3靠近晶片
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
J12
PFD Sel
VIN
R19
Q1
B2N3906
VDD_i
3
1
2
S1
C11
C12
C15
0.1uFC14
C10 C13
22pF
C5
CR2
32768
OSC Sel
C2
22pF
R6
10M
22pF
C4
CR1
VSS_i
1M
4MHz
R7
VSS_i
22pF
C3
K/AK
PUMP Circuit
C26
0.1uF
J11
PUMP Output
2
VSS_i
4
3
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VDD_i
S3
97
98
PT2.0 99
PT2.1 100
PT2.2 101
PT2.3 102
PT2.4 103
PT2.5 104
PT2.6 105
PT2.7 106
107
VDDA 108
ACM 109
OPO 110
AI0 111
AI1 112
AI2 113
AI3 114
AI4 115
AI5 116
AI6 117
AI7 118
AI8 119
AI9 120
AI10 121
AI11 122
AI12 123
AI13 124
AI14 125
AI15 126
127
VSS_i 128
VSS_i RST
S4
PT1.0
S5 PT1.1
VSS_i PT1.1
C10~C15近IC
Analog Net 信號均經過C10~C15 後再進IC腳位
A
C25
BAV99
R20
1
4.7uF
C22
0.1uF
VSS_i
*. PT2 I/O NET
VSS
PT2.7
PT2.6
PT2.5
PT2.4
PT2.3
PT2.2
PT2.1
PT2.0
VDD
D10
VDDA
ACM
OPO
AI0
AI1
AI2
AI3
AI4
AI5
AI6
AI7
AI8
AI9
AI10
AI11
AI12
AI13
AI14
AI15
*. Analog NET
JP3
VDDAVDDA
1
ACM ACM
3
OPO OPO
5
AI0 AI0
7
AI1 AI1
9
AI2 AI2
11
AI3 AI3
13
AI4 AI4
15
AI5 AI5
17
AI6 AI6
19
AI7 AI7
21
AI8 AI8
23
AI9 AI9
25
AI10 AI10
27
AI11 AI11
29
AI12 AI12
31
AI13 AI13
33
AI14 AI14
35
AI15 AI15
37
VSS_i
39
2
VSS_i Analog Port VSS_i
J10
Pump Control
R18
10K
PT2.2
VSS_i
PT2.7
PT2.6
PT2.5
PT2.4
PT2.3
PT2.2
PT2.1
PT2.0
VDD_i
A I5
A I6
R2
10k
U2
VSS_i
NC
NC
NC
VSS
24C02
O P P IN O P N IN
EEPROM Sel
1
3
5
7
9
11
13
15
17
19
1
VSS_i
PT1.0
PT1.2
PT1.4
PT1.6
PT3.0
PT3.2
PT3.4
PT3.6
VDD_i
VSS_i
HY11S14_LQFP128
J9
2
1
U5
BUZZER
VDD_i
VSS_i
PT3.1
PT3.3
PT3.5
PT3.7
VSS_i
VDD_i
PT1.1
PT1.3
PT1.5
PT1.7
BZ
PT3.1
PT3.3
PT3.5
PT3.7
PT1.1
PT1.3
PT1.5
PT1.7
VSS_i
2
4
6
8
10
12
2
4
6
8
10
12
0.1uF
C24
1
3
5
7
9
11
I/O(PT3)
1
PT3.0
3
PT3.2
5
PT3.4
7
PT3.6
9
11
I/O(PT1)
JP12
JP9
VDD_i
PT1.0
PT1.2
PT1.4
PT1.6
VSS_i
VDD_i
J8
Program
VSS_i
VSS_i
VDD_i
VDD_i
C23
10nF
R16
100K
VDD_i
HY11S14
NC
VDD
PT2.0/XTO
PT2.1/XTI
PT2.2/PFD/PWM0/CPAI0
PT2.3/CPAI1/PWM1/TMCKI
PT2.4/CCP0/CPAI2/PWM2
PT2.5/CCP1/CPAI3/PWM3
PT2.6/CPAI4/CPAO
PT2.7/CPAI5/CPAO
NC
VDDA
ACM
OPO
AI0/PT4.0
AI1/PT4.1
AI2/PT4.2
AI3/PT4.3
AI4/PT4.4
AI5/PT4.5
AI6/PT4.6
AI7/PT4.7
AI8/PT5.0
AI9/PT5.1
AI10/PT5.2
AI11/PT5.3
AI12/PT5.4
AI13/PT5.5
AI14/PT5.6
AI15/PT5.7
NC
VSS
U1
C OM 0
C OM 1
C OM 2
C OM 3
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S E G 10
S E G 11
S E G 12
S E G 13
S E G 14
S E G 15
S E G 16
S E G 17
S E G 18
S E G 19
S E G 20
S E G 21
S E G 22
S E G 23
S E G 24
S E G 25
S E G 26
S E G 27
S E G 28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SBM_SEL/ICE_ADR15
ICE_ADR14
ICE_ADR13
ICE_ADR12
ICE_ADR11
ICE_ADR10
ICE_ADR9
ICE_ADR8
ICE_ADR7
ICE_ADR6
ICE_ADR5
ICE_ADR4
ICE_ADR3
ICE_ADR2
ICE_ADR1
ICE_ADR0
ICE_DA7
ICE_DA6
ICE_DA5
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
.
3
CE
1
J15 R3
10k
1
2
3
4
1
2
D9
PT2.7_1
PT2.6_1
PT2.5_1
PT27
D8
PT26
D7
PT25
VSS_i JP8
D6
PT24
2
4
6
8
10
12
14
16
18
20
VDD_i I/O (PT2)
PT2.4_1
PT2.3_1
PT2.2_1
PT2.1_1
PT2.0_1
D5
PT23
D4
PT22
D3
PT21
D2
PT20
1
3
2
1
II C_ S D A
VSS_i
S6
S7
S8
VSS_i
J7
1
2
3
4
5
6
SPI
VIN
SDI(PT1.2)
SCK(PT1.6)
SDO(PT1.5)
CS(PT1.1)
Key
1
2
3
J5
*. PT1,PT3 I/O NET
VDD_i
PT1.2
PT1.6
PT1.5
PT1.1
VSS_i
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
_SBM-SEL
_ADR14
_ADR13
_ADR12
_ADR11
_ADR10
_ADR9
_ADR8
_ADR7
_ADR6
_ADR5
_ADR4
_ADR3
_ADR2
_ADR1
_ADR0
_DA7
_DA6
_DA5
COM0
COM1
COM2
COM3
1
2
3
4
VDD_i
J1
Current test
VDD_bat
C18
J2
EXT
3
2
3V
1
VDD Sel
VSS_i
S10
RS232 Sel
LCD_20*4
TXD 1
RXD 2
MAX232
1uF
U3
1
C1+
VCC
C16
2
VS+
GND
1uF
3
MAX232
C1T1OUT
4
C2+
R1IN
5
C2R1OUT
C17
6
VST1IN
1uF RXD_PC
7
T2OUT
T2IN
8
TXD_PC
R2IN
R2OUT
C20
1uF
VSS_i
J6
LCD_20*4
COM0
COM1
COM2/SEG0
COM3/SEG1
VSS_i
C6
0.1uF
C21
10uF
C7
10uF
R8
100K
R14
42.2K
R15
100K
VSS_i
1
2
VDD_bat J13
RS232 Power
D1
5
4
3
2
1
S2
5
ON1
COM1
1
OFF1
*. POWER NET
3
6
ON2
COM2
2
OFF2
GND
GND
GND
GND
4
GS2612 VSS_i
8
7
6
5
EN
IN
OUT
ADJ
Sheet of
JP4
VBAT
V1
VIN
JP5
VSSBAT
V01
Revision
COM1 COM1
COM3 COM3
SEG3 SEG3
SEG5 SEG5
SEG7 SEG7
SEG9 SEG9
SEG11 SEG11
SEG13 SEG13
SEG15 SEG15
SEG17 SEG17
SEG19 SEG19
SEG21 SEG21
SEG23 SEG23
SEG25 SEG25
SEG27 SEG27
SEG29 SEG29
SEG31 SEG31
SEG33 SEG33
SEG35 SEG35
SEG37 SEG37
SEG39 SEG39
SEG41 SEG41
*. LCD NET
*. EUART NET
6
7
8
9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
R17
0
VSS_i
LCD2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
JP11
RS232
CON1
U4
1N4001
1
2
3
4
A11022-1
5 Dec2011
Number
HY11S14 Target Board
COM0 COM0
COM2 COM2
SEG2 SEG2
SEG4 SEG4
SEG6 SEG6
SEG8 SEG8
SEG10 SEG10
SEG12 SEG12
SEG14 SEG14
SEG16 SEG16
SEG18 SEG18
SEG20 SEG20
SEG22 SEG22
SEG24 SEG24
SEG26 SEG26
SEG28 SEG28
SEG30 SEG30
SEG32 SEG32
SEG34 SEG34
SEG36 SEG36
SEG38 SEG38
SEG40 SEG40
C19
1uF
16
15
14
13
VSS_i
12
RXD_PC
11
TXD_PC
10 TXD
9 RXD
4 PT1.4 TXD
3 PT1.3 RXD
Title
Size
A4
Date:
APD-HYIDE005-V04_EN
page25
© 2009-2012 HYCON Technology Corp
www.hycontek.com
II C_ S C L
V LC D
C OM 0
C OM 1
S E G 0/C O M 2
S E G 1/C O M 3
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S E G 10
S E G 11
S E G 12
S E G 13
S E G 14
S E G 15
S E G 16
S E G 17
S E G 18
S E G 19
S E G 20
S E G 21
S E G 22
S E G 23
S E G 24
S E G 25
S E G 26
S E G 27
S E G 28
V P P /RS T
P T 1 .0/I N T 0/ CP A I 6/P S C K
P T 1 .1/I N T 1/ CP A I 7/S CE /P S D I
P T 1 .2/I N T 2/ S D I/S V S IN
P T 1 .3/T S T /I N T 3/R X
P T 1 .4/I N T 4/ TX
P T 1 .5/I N T 5/ S D O / P S D O
P T 1 .6/I N T 6/ S C K
P T 1 .7/I N T 7/ BZ
P T 3 .0
P T 3 .1
P T 3 .2
P T 3 .3
P T 3 .4
P T 3 .5
P T 3 .6
P T 3 .7
NC
IC E _ V C C
IC E _ V S S
IC E _ S D I
IC E _ S D O
IC E _ S C K
IC E _ CS
IC E _ CS 0
IC E _ RD
IC E _ W E
IC E _ D A 0
IC E _ D A 1
IC E _ D A 2
IC E _ D A 3
IC E _ D A 4
V IN
V IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
_V S S _ ra m 20
_S D I
21
_S D O
22
_S C K
23
IC E C S 24
_C S 25
_R D 26
_W E 27
_D A 0 28
_D A 1 29
_D A 2 30
_D A 3 31
_D A 4 32
12 9
13 0
V PP
P T 1 .0
P T 1 .1
P T 1 .2
P T 1 .3
P T 1 .4
P T 1 .5
P T 1 .6
P T 1 .7
P T 3 .0
P T 3 .1
P T 3 .2
P T 3 .3
P T 3 .4
P T 3 .5
P T 3 .6
P T 3 .7
1
2
3
4
5
6
2
1
VSS_i
VSS_i
9
8
7
6
5
4
3
2
II C_ S D A
II C_ S C L
1
2
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S EG 10
S EG 11
S EG 12
S EG 13
S EG 14
S EG 15
S EG 16
S EG 17
S EG 18
S EG 19
S EG 20
S EG 21
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S EG 2
S EG 3
S EG 4
S EG 5
S EG 6
S EG 7
S EG 8
S EG 9
S E G 10
S E G 11
S E G 12
S E G 13
S E G 14
S E G 15
S E G 16
S E G 17
S E G 18
S E G 19
S E G 20
S E G 21
VSS_i
RP
470
1
Figure 28
HY11S14
HY-IDE Hardware User’s Manual
5. Simple Error Detection
5.1. ICE cannot connect to software

Simple error correction is described as follows when ICE cannot connect to software:
Hardware configuration, IDE mode error detection:
 Options =>Interface Setup =>Interface Mode defaults as USB
 IDE Mode is emulate and Debug
.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page26
HY11S14
HY-IDE Hardware User’s Manual

Power System Debug：



This action is to testify whether HY-IDE USB Control Board is completely
connected to PC through USB port and the regulated 3V voltage output functions
normally.
Options =>ICE Test => Click CK ALL and confirm VCC voltage is close to 3V.
When Control Board only connects to USB port, the voltage of VPP closes to 5V;
when Adapter 9V of J4 is connected, VPP voltage will close to 6.3V.
.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page27
HY11S14
HY-IDE Hardware User’s Manual

ICE Power Debug:
 When using USB to supply power, a few switches must be inspected to ensure
ICE chip operates normally.
 ICE Board S1, switching VIN, VDD_bat to ON

Target Board. Short J2 PIN1-2 and J1, switching S2 to ON
.


Use DMM to inspect whether 3V voltage exists in VDD(PIN98)-VSS(PIN128)
and ICE_VCC(PIN19)-VSS(PIN128);
 If voltage is absent, please refer to procedures of ”Power System Debug”
and ”ICE Power Debug” chapter;
Using external power supply, inspects some switches:
 ICE Board S1, switching VDD_bat to ON, other switches turns OFF
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page28
HY11S14
HY-IDE Hardware User’s Manual

Target Board JP4 is inputted from external voltage, making J1 short, PIN1-2
of J2 short, (if > 3V is needed, short PIN2-3 of J2), S2 ON

Using voltmeter to inspect, whether 3V voltage exists in
VDD(PIN98)-VSS(PIN128) and ICE_VCC(PIN19)-VSS(PIN128);
If voltage is absent, please refer to procedures of ”Power System Debug”

and ”ICE Power Debug” chapter;
5.2. Program Memory Loading Fail
.

ICE SRAM Debug:
 Check whether ICE Board J1 & J2 is correct; when emulating HY11S14 (16K), J1
PIN1-2 and J2 PIN1-2 must be short circuit.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page29
HY11S14
HY-IDE Hardware User’s Manual

SRAM Data, Program ROM Data Debug:
 Options =>ICE Test =>SRAM Data
 Key in 80 in Address and AA in Write Data respectively. Click Write button,
data will be written in SRAM;
 Click Read button, readout data; the filled in data will display in Read Data
location.
 Options =>ICE Test => Program ROM Data
 Key in 80 in Address and 5AA5 in Write Data respectively. Click Write button,
data will be written in ROM;
 Click Read button, readout data; the filled in data will display in Read Data
location.
.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page30
HY11S14
HY-IDE Hardware User’s Manual
6. Revision History
Major differences are stated thereinafter:
Version
Page
V01
ALL
V02
26~30
V04
ALL
28
Revision Summary
First edition
Add Chapter 5 Simple Error Detection
Add the description related to DK03
Correct the description of ICE power debug
.
© 2009-2012 HYCON Technology Corp
www.hycontek.com
APD-HYIDE005-V04_EN
page31