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Cortex-M-series
Since the Cortex-M-series seems to be best suitable to be used as a basis for WSN nodes,
especially for SNs, the following sections discuss this CPU family in more detail.
Inside the
Cortex-M-series, ARM implemented a couple of techniques that are shortly described in the
following.
Thumb technology:
Since memory in WSN nodes is very limited, all operations on these
platforms have to be optimised for code size. The ARM Thumb technology [ARMe] is an extension of the 32-bit ARM-Architecture and a possible solution to solve this code size issue. The
Thumb instruction set features a subset of the most commonly used 32-bit ARM instructions
compressed into 16-bit wide opcodes. On execution, these 16-bit instructions are decompressed
transparently in the instruction pipeline to full 32-bit ARM instructions in real time. Designers
can use both 16-bit Thumb and 32-bit ARM instructions sets and therefore have the exibility
to emphasise performance or code size on a sub-routine level as their applications require.
Thumb-2 technology:
In addition to the reduced code size realised by the Thumb technology,
Thumb-2 [ARMc] reduces the code-size even more. Thumb-2 core technology adds a mixed mode
capability to the CPU, dening an additional set of 32-bit instructions that execute alongside
traditional 16-bit instructions in Thumb state. This reduces or removes the need for balancing
ARM and Thumb code in a system, since the 32-bit Thumb-2 instructions do not need to
be decompressed.
Thumb-2 technology is a superset of Thumb technology and is backwards
compatible with existing ARM and Thumb solutions.
NVIC:
The Nested Vectored Interrupt Controller (NVIC) ([ARMd], Chapter 5, page 47) is an
integral part of Cortex-M processors and provides the processors' interrupt handling abilities.
The Cortex-M processor uses a vector table that includes the address of the function to be
executed for a particular interrupt handler.
the address from the vector table.
On accepting an interrupt, the processor fetches
To reduce gate count and enhance system exibility, the
Cortex-M processor uses a stack based exception model. When an exception takes place, critical
general purpose registers are pushed on to the stack. Once the stacking and instruction fetch are
completed, the interrupt service routine or fault handler is executed, followed by the automatic
restoration of the registers to enable the interrupted program to resume normal execution. This
approach removes the need to write assembler wrappers that are required to perform stack
manipulation for traditional interrupt service routines based on the programming language C,
which reduces code size and thus saves memory in WSNs. The NVIC supports nesting (stacking)
of interrupts, allowing an interrupt to be serviced earlier by exerting higher priority.
WIC:
The Wake-up Interrupt Controller (WIC) provides a low power interrupt detection logic
that can emulate the full NVIC behaviour when correctly primed by the full NVIC on entry to
very-deep-sleep.
For low power applications, it is desirable to reduce the dynamic and static
power-consumption of the processor while in deeper sleep modes.
This can be achieved by
stopping clocks, removing power from the processor or both. When powered o, the NVIC is
unable to detect interrupts, so that knowing when to come out of sleep becomes problematic.
Unlike the NVIC, the WIC has no prioritisation logic.
It implements a simple interrupt
masking system, signalling for wake-up as soon as a non-masked interrupt is detected. The WIC
is invisible to end users of the device.
Cortex M0 processor
For the purpose of this study, we focus on the ARM Cortex-M0 processor with its low gate count,
an energy ecient processor based on the ARMv6M architecture that is intended for microcon-
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