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ADA2000User'sManual
ffi
RearTimeDevices,rnc.
"AccessingtheAnalog World'.,*
ISO9001 and AS9100 Certified
ADA2OOO
User'sManual
ffi
REALTIMEDEVICES,
INC.
820 NorthUniversity
Drive
PostOfficeBox906
StateCollege,Pennsylvania
16804
Phone:(814)234-8087
FAX:(81a)234-5218
Pubtishedby
RealTime Devices,Inc.
820N. UniversityDr.
P.O.Box 906
StateCollege,PA 16804
CopyrightO 1991by RealTimeDevices,Inc.
All rightsreserved
Printedin U.S.A.
Rev.C 9291
TABLE OF CONTENTS
Pagg
INTRODUCTION
How to Use This Manual.......
When You Need Help.
...-..-..........i-2
.........i-2
CHAPTER r - QUICK START-GETTING YOUR ADA2000 RUNNING
WhatComesWith YourADA2000
.............1-1
The Hardware.............
...........1-l
Functions
You CanSet.....,.......
..........1-l
Setting the Base I/O Address
.............1-2
DigitalI/O Circuitry
......... 14
Installingthe ADA2000 in Your Compurer....
.............1-?
TheSoftware
........l-8
DemoDisk
.....................1-8
Backing
Up YourDisk...........
.............
1-8
InitializingYour ADA2000...........
.........1-9
Selectingan Analog Inpur Channe1................
............1-10
Setting the Input Gain...........
...............1-11
Takingan A,/DReading......
....1-L2
Controlling
theD/A Convener
..................1-13
LoadingtheD/A Convener
Data...........
.................1-13
Output Voltage Rangeand Reso1ution...............
.....................1-14
CHAPTER 2 - FUNCTIONAL DESCRIPTION
Analog-to-DigiralConversionCircuitry..............
Multiplexers................
GainControlCircuirry.....
Sample
andHoldCircuirry......
A / DC o n v e n e r . . . . . . . . . . . . . . .
Digital-to-AnalogConversionCircuirry.....
D/A Converrer...............
OutputAmplifiers...
Programmable
PeripheralInterfaces.
ppl1..........
.........2_2
....2-z
PPI2..........
Programmable
IntervalTimer(PIT)
...-.........2_z
............-.......2_2
..................2-3
....................2_3
.........2-3
.........2-3
....................24
....................24
.............24
CHAPTER 3 - JUMPER SETTINGS
Sl - AnalogInputSignalTypeDIP Switch........
P2- BaseVO Address
Header
Connector....
P3 - Programmable
IntervalTimer @lT) I/O HeaderConnecror....
..........3_z
...................3_2
.......................3-2
Page
P4, P5, P7, and Pll - IntemrptHeaderConnectors..
P4 - EXTINTI and PPI1 INTRA Interrupts....
P5 - PIT Output [nterrupts....
P7 - AID End-of-Convert(EOC) Interrupt......
Pll-EXTINT2andPPI2INTRAandINTRBInterrupts....
(EOC)MonitorHeaderConnector..........
P6- End-of-Convert
Voluge RangeHeaderConnector....
P9 AiD Converter
VolrageRangeHeaderConneclor.
PlO - D/A Converter
Pl2- Diginl I/O HeaderConnector....
DigitalIlO - Buffers,Shunts,andResistorNetworks....
Mode 0 Operation...
Mode 1 Operation...
Mode 2 Operation...
Resistor
Networks.....
CHAPTER 4 - PROGRAMMING YOUR ADA2OOO
Selectingan Analog Input Channe1................
Setting the Input Gain...........
Takingan A./DReading. ... ..
ConrollingtheD/A Converter....
Programming
theProgrammable
PeripheralInterfaces
Programming
theProgrammable
IntenralTimer.........
llardware
Inemrpts.....
(EOC)Signal.........
AID End-of-Converr
PPIInenuprs
PlTlnemrps
CHAPTER 5 - CALIBRATION PROCEDURES
Required
Equipment.........
A/D Calibration..............
UnipolarCalibration..
BipolarCalibration...
GainCircuitryCalibration
D/A Calibration.............
UnipolarCalibration..
BipolarCalibration...
......................34
.....3-5
.........3-5
......3-5
.........36
............36
....................3-7
.....-...............3:7
.......3-7
.....................3-8
........3-9
.......3-9
.......3-9
......3-10
.............4-1
.................4-1
. .... 4-1
...............4-1
.......4-l
......4-3
............4-3
..................44
..................44
..................44
.......5-f
.......5-l
.......5-2
........5-z
.......5-3
........5-3
.......5-3
........54
APPENDIX A - ADA2000 Specifications....
.....A-l
APPENDIX I] - Connector Pin Assignments................
......81
APPENDIX C - ComponentData Sheets........
....................C-1
APPENDIX D * Configuring the ADA2000 for SIGNAL*MATH.........................D-l
APPENDIX E - Configuring the ADA2000 for ATLANTIS
................8-1
A P P E N D I XF - W a r r a n t y . . . . . . . . . . .
......F-l
tl
LIST OF ILLUSTRATIONS
Figure
i-l
1-l
L-2
1-3
l4
1-5
16
2-l
t3
3-1
3-2
3-3
34
3-5
34
3-7
3-8
3-9
3-r0
3-l l
3-r2
3-13
3-r4
+l
5-l
Page
.......i-1
Typical LaboratorySetup..........
...........L'2
BoadLayout........
ADA2000
.................1'4
HeaderConnecw,n.
BaseVOAddrcss
..................1'4
8255PPI FunctionalBlock Diagram
...................16
PPI2FunctionalBlock Diagram......
......1-7
Pull-upResistorBlock Diagram
..........1-12
Word
Format
A/D Convenion
...................2-l
ADA200OFunctionalBlock Diagram.................
..................2-3
EOC Timing Diagram.
...........
3-1
Iayout........
ADA2000
Board
.................3-2
51..............
DIPSwirch
....3-3
P3.........
PITVOHeader
Connecor
..........34
PlTFunctional
BlockDiagram
P4
............3-5
IntemptHeader
Connecor
P5
............3-5
InteruptHeader
Connecor
htemrytHeaderConnecorF/
...........36
IntemrptHeaderConnector
P11.............
.............36
EOCMoniorHeaderConnecttrP6.......
...............3{
A/DConverterVoltageRangeHeaderConnectorP9 ..................3-7
D/A Converter
VoltageRangeHeaderConnector
P10...................................3-7
DigitalVOHeader
Pl2
Connecor
.......3-8
PPI2Circuitry
..............3-8
PPI2PortA Pull-uplhrll-down
Resislor
Circuitry
...................3-10
PPIModeDefinition
Format........
......4-2
ADA2000
Board
layout
...................
5-1
ul
tv
INTRODUCTION
technicaldataforRealTimeDevices'ADA2000multifunctiondata
Thismanualshowsyouhowtooperateandprovides
analog-o-digial
multichannel
differentialor single-ended
acquisitionboard.TheADA2000features12-bithigh-speed
your
IBM
PCDff/AT or
allows
versatile
interface
conversionand two channelsof digital-to-analogconversion.This
and
control
to senseand
compariblecomputerto effectivelyoperatein thereal-timeenvironmentof daa acquisition
for
PC
data
collection.
generare
bothanaloganddigiralsignals.Figurei-l showsa typicallaboratorysetupusinga
LRBOnBTORY
ltto$XsrnrlOil
SOFTUNNE
Signalconditioning
D acquisition,
data reduction,
graphics,
analgsis,
conlrol,dotasto169e
LflBOBRTOITRUTOF{RTI
ON
Fig. i-1 - TypicatLaboratorySetup
(12-bit)analog-o-digiulanddigial-to-analogconverrers,
TheADA2000featureshigh-resolution
digitalI/O,andtimer/
countersthatprovideflexibility for manyapplications.
Its sixJayerconstruction,includingseparate
powerandground
planes,enhances
boardperformance
andlow-noisecharacteristics.
It plugsdirectlyino any unusedexpansionslot in
thecomputer.All externalI/O connections,
includingPC bus-sourced
power, are accessibleat the rear panelof the
computerwhentheboardis insmlled.
Severalof theADA2000'sfunctionscanbereadilyadaptedfor yourspecificrequirements.
Tkough programmingand/
or jumperor switchsettingsmadeon theboard,you can:
. Selectthe baseI/O address,
. Choose8 djfferentialor 16single-ended
analoginputchannels,
. Selecttheactivechannel,
. Selectthechannelgain,
. Selectthe analoginput voluge rangeandpolarity,
. Selecttheanalogourpulvoltagerangeandpolarity,
. Control40 Tfl/CMoS-compatible digitalI/O lines,
. Controlthreel6-bit, 8 MHz timer/counter
circuits(he programmable
intervaltimer),
' Monitor theA/D conversionusingtheend-of-converr
(EOC)signal,
. Generarcincerruptsignals.
Many of thesefuncdonsare set up at the factory,basedon typical data collection requirementsand customer
whenordering.Therefore,
youcansuccessfully
specifications
installandrun theADA2000with minimalundersanding
changing
and
about
controllingthem.On theotherhand,youmaywantto understand
everythingaboutyour boardso
thatyou caneffectivelyuseeachfeature.With thisin mind,thismanualprovidesbasicinformationto get rheboardup
andrunning,as well asdetailedinformationfor a full understanding
of eachfunction.
i-l
How to UseThis Manual
whilealsoincludingsufficientdetail
Thismanualis designedrohelpyouinstallandgetyourADA2000runningquickly,
your
boardasquickly aspossible.This chapter
abouteachboardfuncrion.Begin by readingChapterI in order to use
your
ADA2000packagewill allow you to promptlyuse
softwareincludedwith
demonstration
andtheaccompanying
your interface.To fully undersuand
andcontrol theADA2000 functions,readChapters2 through4. Chapter5 contains
boardcalibrationprocedures.
in this manualaredescribedin detailbelow.
Thechaptersandappendixes
to
Chapter1, "Quick Start-Getting Your ADA2000Running,"providestheinstructionsnecessary
notcover
installtheboardanduseits basicfunctions.Theinformationcontainedin thischapterdoes
how to changethe boardsetup,exceptfor the baseI/O address.
Chapter2, "Functional Description," providesa block diagxamand a functional discussionof the
board.
Chapter3, 'Tumper Settings,"describeseachheaderor jumper circuit on the board and how it is
controlled.
Chapter4, "ProgrammingYour ADA2000," describeshow the boardcanbe programmedusingthe
demonstration
software.
providesinstructionsfor boardcalibration.
Chapter5, "CalibrationProcedures,"
AppendixA, "ADA2000 Specifications,"
conlainsa completelisting of boardspecifications.
"Connector
Pin Assignmens,"containsthe pinous of theexternalVO connecorsand
AppendixB,
thematingconnectors'partnumbers
Appendix C, "ComponentData Sheets,"containsmanufacturen'data sheetsfor major board
componenls.
AppendixD, "ConfiguringtheADA2000for SIGNAL*I{ATH," containsinformationaboutseuing
boardjumpersand andinitializing the boardto run the SIGNAL*MATH acquisitionandanalysis
program.
AppendixE, "ConfiguringtheADA2000for ATLANTIS," containsinformationaboutsettingboard
jumpersto run the ATLANTIS dataacquisitionandreal-timemonitoringprogmm.
AppendixF, "Warranty,"containsboardwarrantyinformation.
WhenYou NeedHelp
Whenyouareworkingwith theADA2000interfaceboard,thismanualandthedemosoftwareincludedin yourpackage
will providesufficientinformationto properlycontrrol
all of theboard'sfunctions.If, however,aftercarefullyreviewing
themanual,youareunablen obain properresponses
fromttreboard,RealTime Devices'technicalstaffisreadyo assist
you.For assislance,
call (814)234-8087duringregularbusinesshours,easternstandard
time or easrerndaylighttime,
or senda FAX requestingassistance
to (814) 234-5218.Be sureto inctudeyour company'sname,your narne,your
telephonenumber,anda brief descriptionof theproblem.
i-2
CHAPTER 1
RUNNING
QUICK START-GETTING YOURADA2OOO
To get startedusing your ADA2000 interfaceboard,you musu
- Selecrby jumper a baseVO addresswhich doesnot contendwith any other peripheraldevice.
- Insrall the boardino your PC.
- Connecta signalto oneofthe analoginput channels.
- Run the ADA2000 software.
Unlessyou haveotherrequirements,thesestepsare all that arc necessary!o useyour ADA2000 board.
This chaprerexplainshow to install your ADA2000 and rse is basicfunctions.You will learn how to:
. Changethe baseI/O addresssening,
. lnstqll the boardin your pC,
. Initialize thebord,
. Selectttre analoginput channeland gain,
. Take an A/D reading,
. Generaleanalogoutputs.
This chapterallows you to immediatelystart rsing the basic functions of your ADA2000 board for daa collection
apptications.This chapterdoesnot explainhow to conrrol themoreinricate boardfunctionssuchastheprogrammable
howochangehardware-connolled
intervaltimer,thevariousdigrtalVOconfigurations,orintemrp8,nordoesitexplain
secingsexceptfor thebaseVO address.The functionsnot coveredherearedescribedin Chapters2 through4.
Iilhat ComesWith Your ADA2000
The standardADA2000 boardpackageincludes:
I
1
ADA2000 10.4-inch(254mm)interfaceboard
ADA2000 de,modisk
I
user'smanual
Additional items, suchas the ADA2000 cable set (order numberXK4O-2),exlenderboardsor SIGNAL*MATH c
ATLANTIS applicationsoftware,areavailablefor this boardand are irrcludedon an as-orderedbasis.
AII signalson your boardare madeeasily accessiblewith Real Time Devices' XB4O VO extenderboardand XC40
expansioncable.Theextenderboardhastwo 20-pinterminalsrips andaprototypeareatosupportany specialcircuitry
you mayrequireto conditionttresignals.Forexample,if you areprototypingsolid-sae relaysoropoisolators, this can
easily be done with an XB40. The expansioncable terminatesin a 40-pin wire-wrap headerconnectorsuitablefor
installationin sandard 0.1 inch spacingperf-boardmaterialavailablefrom mostelecronic disribuors.
The Hardware
The ADA2000 interfaceboardis shownin Figure 1-1. A complelelisting of the board specilicationsis containedin
AppendixA. The ADA2000 hasseveralfeanres which areuser-controlledthroughhardwareor software.Most of the
hardware-controllable
featuresarejumper-conuolled;$reremainingare switch<ontrolled
Alloftheboardcomponentsare
mountedona10.4-inchprintedcircuitboardwhich
fits inanyunusedfull-sizeexpansion
in
IBM
slot an
PCIXTIAT or compatiblecomputer.Three4Gpin connectorson the board,Ptl, Pl4, and P15,
accommodale
all of theboard'sexternalI/tC.In operation,theseconnecorsarecabledsothatall 120linesareaccessible
at therearpanelof thecomputer(seethe boardinsallation instructionshter in this chapter).
FunctionsYou Can Set
To allow theADA2000 interfaceboardto be adaptedto your needs,severalfunctionscanbe setup to perform specific
tasksby changingthe hardwareconfigurationor throughsoftware.Table 1-l liss eachfunction you can control, the
facory (or default) settingif applicable,and wherein this muural you canfind information aboutits seuings.
1-l
I
r"lI
:flln
:l lF
illi
tl
lt
tl
tl
ll
.O
tl
l
tl
LJ
;
n
ll
It
ll
Fig. 1-1 -ADA2000 Board Layout
The functionswhich you cancontrolthroughhardwareare:
- BaseI/O address,
- Analoginput channeltype,
Analoginput channelvolage rangeandpolarity,
- End-of-convert.
monitor,
- Analogoutputvolragerangeandpolarity,
- Digital I/O (hardwareandsoftware),
- PIT timerrcounters
(hardwareandsoftware),
- Interrupts.
The functionswhich you cancontrolthroughsoftwareare:
- Analoginput channelselection,
- Analoginputgainselection,
- Digital I/O (softwareandhardware),
- PIT timer/counters
(softwareandhardware),
- Boardinirialization.
Settingthe BaseVO Address
Startingwith the baseI/O address(BA), the ADA2Offi uses28 consecutive
addresslocationsin your computer'sI/O
space.Tablel-2lists theI/O mapfor theADA2000.Itis importanttorecognize
thatsomeof yourcomputer'sI/O address
locationswill alreadybeoccupiedby internalI/O andotherperipherals.
If yourADA2000boardries to useI/O address
locationsalreadyin useby anotter devicein your system,addresscontentionwill result"Hence,the board will not
operate,or at bestwill operareenatically.
I/O addresscontentionis one of the most commonproblemsencountered
whenaddingan interfacedevice to your
computersystem.To avoid this problem,a baseI/O addressjumpercircuir is providedon the ADA2000 board.By
(ocatedjusttotherightofcenter,nearthebottom
changingthepositionof thejumperontheheaderconnecrcrlabeledP2
of theboard),the baseI/O addresssettingcanbe changedto anyoneofeight locations.
t-2
Table 1-1-ADA2000 Board Functions and Settlngs
FUNCTION
FACTORY SETTING
USER INFORMATION
Basel/O Address
300 hex(768decimal)
To changethis setting,see
"Settingthe Basel/O
Address,"Chaptert
AnaloglnputChannelType
8 differential
channels
To select16 single-ended
channels,see Sl discussion,
Chapter3
AnaloglnputChannel
Selection
lable
Software-control
See "Selectingan Analog
Chapter1,
InputChannel,"
and demodisk
AnalogInputGainSelection
Sottware-co
ntrollable
See "Settingthe lnputGain,"
Chapter1, anddemodisk
AnaloglnputVoltageRange
and Polarity
ied whenordering To changethesesettings,see
User-specif
51 and P9 discussions,
Chapter3.
(EOC)Monitor Connectedto PA7
End-ol-Convert
Chapter3.
See P6 discussion,
AnalogOutputVoltageRange Voltagerangefactory-setto
samepolarityas analoginput
and Polartty
To changethesesettings,see
Chapter3.
Pl0 discussion,
D(Titall/O
16 l/O LinesfromPPll
(unbuffered)
Ilable
Software-contro
the PPls,"
See "Programming
Chapter4 and demodisk
24 VOLinesfromPPl2
Bufferedinputs;
software-controIlable
See"Digitall/O Circuitry,"
l/O
Chapter1: P12anddi,gital
Chapter3;
discussions,
the PPls,"
Programming
Chapter4; anddernodisk
Modes
lable
Software-control
See"Programming
the PlT,"
Chapter4 anddernodisk
l/O Configuration
ClockInput:5MHz
GateInput:+5 V
ClockOutput:To P8
See P3discussion,Chapter3
Disabled
See P4,P5, P7,and P11
Chapter3, and
discussions,
"lnterruptConsiderations,"
Chapter4
Programmable
lnvervalTimer
(PlT)Circuitry
Interrupts
Figgre 1-2 showsthebaseVO addressheaderconnector,P2, with thejumper installedat the factory-setlocationof 300
VOaddress
acrossoneof theeightpairsof pinsonP2.Thehexadecimalbase
hei. Thelumpermustbeinsralledvertically
seningcorresponding!o eachpair of pins, from left to right, is as follows:
200
240
280
2C0
300
340
380
3C0
Forexample,if thebaseVO addressis changedo 280hex,thenfor the28 operationslistedin Table 1-2,BA equals280.
Thus, to sendthe channelselectionandgain datato pon B of PPII, its addressof BA + I becomes281 hex.
If thefactory seuingof 300hexwill causecontentionin your system,positionthejumperto thedesiredbaseVO address
anoteof itsvalueonthetableinsidethebackcoverofthismanual.
seuing.OnceyouhavesetthebaseVOaddress,make
programs.
You will needto know this settingfor usein your
3C0
200
P2
P2
Fig.1-2- Basel/O AddressConnector,
DigitatUO Circuitry
provide40
I/O lineswhich
canbe
TTL/CMOS-compatibledigital
Two8255programmableperipheral
interfaces
@PIs)
EachPPIhas24digitalVOlines,asshownin the8255block
configrredby theuserfor a widerangeof I/O functions.
functionandarenot
inFigure1-3.EightoftheselinesonPPll
supporttheboard'sanalog-to-digitalconversion
diagram
availablefor otheruse.Theremaining16linesfromPPI1and24linesfromPPI2areavailableto theuser.
PORTA
PORTB
PORTC
Fig. 1-3 - 8255 PPI FunctionalDiagram
Ttrc A lines of PPI2canbe setas bufferedor shuntedlines usingon-boardDIP switches!o supportindividualuser
requiremens.All24lines arefactory-setasbufferedinpu6, andthisis thesettingwhich will be usedin this chaprcr.
buffer ICs and DIP switchesarelocatedon the left-handportionof *re board(nearl/O
PPI2,UZA,and its associated
connectorPl4).TheboardisshippedwithbufferICsinstalledandwiththeDIPswitchessettotheOPEN(OFF)position.
P12is jumperedso thattheI/O linesareconfiguredasbufferedinpus. All of thesesettingsareexplainedin Chapter3.
T4
Tabfe 1-2-ADA2000 l/O Map
FUNCTION
A4
A3
A2
A1
AO
R/W
BA + HEX
PortA
PortB (ChannelSel&Gain)
Poil C
ConlnlWord
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F|/w
0
1
1
1
0
1
R/W
w
2
3
0
0
0
0
0
0
0
0
1
1
1
1
x
x
x
x
0
1
0
1
W
W
R
R
4or6
5or7
+or6
5or7
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
W
W
8
I
A
B
0
1
0
1
0
x
x
x
x
w
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
R/W
R/W
R/W
W
14
15
16
17
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
R/W
B/W
R/W
W
18
19
1A
1B
PPIl
w
1
IVDConversion
Circuitry
Start 12-bitConversion
Start8-bitConversion
ReadMSB
ReadLSB
D/AConversionCircuitry
ProgramAOUT1LSB
ProgramAOUT1
MSB
ProgramAOUT2LSB
ProgramAOUT2MSB
Convert/Update
AOUTl/AOUT2
ClearAOUT1/AOUT2
w
w
W
C,D,E,OTF
10,11,12,of
13
Programmable
IntervalTimer
Counter0
Counter1
Counter2
ControlWord
PP'2
PortA
PortB
PortC
ControlWord
NOTE:x = don'tcaresetting
1-5
Note that if you changeany DIP swirchsecingsto the CLOSED(Ol9 position as describedin that chapter,you must
removethe correspondingbuffer ftromtheboard.Figure l-4 showsthe operationof PPI2.
8255PPI
DIP
SWITCH
SHUNTS
GROUPA
CE
o
F
o
[!
GROUPB
z
z
o
o
o
GROUPC
(LSB)
GROUPC
(M38)
OPTIONAL
&
PULL.UP/
PULL-DOWN
RESISTORS
Fig. 1-4 -
PPl2 FunctionalBfock Diagram
SingleinJine resislornetworkscanbe installedat thefactory(if orderedasanoption) or by theuserin IC locationsRNl
throughRN4 on theleft sideof theboard.Thesenetworksallow thePPI2digital VO lines o bepulledup or pulled down
for certainapplications.Thesenetworksareconnectedlo a voltagesource(pull-up) or ground(pult-down) by jumper
seningsonheaderconneclorPl3.
Figurel-5showsatypicalpull-upresisorapplication.DetailsonconfiguringthePPl
circuitry are includedin Chapter3.
l-6
PAO
PA1
Pla
PA3
PM
PA5
PA5
PA7
_J_-
L__
Fig. 1-5 -
Pull-UpResistorBlock Diagram
InstallingtheADA2000in Your Computer
Beforeinstalling the ADA2000 in your computer,makesuretlat rhebaseI/O addresshasbeenproperly selectedand
all the hardwareseEingshavebeenconfrguredto supportyour requirements.This chapterexplainshow !o control the
baseVO address.Otherhardwaresecingsaresetu thefactory,aslistedin Table 1-l , andremainat their facory secings
unlessyouchangethem.Theintemrps generatedby yourADA2000aredisabled(not connected)whenyou receiveyour
board.If you intendto usetheintemrpts,theymustbeconfiguredappropriatelybeforeinsalling theboard.Information
abouttheseand other functionsnot coveredin this chapteris providedin Chaprcrs2 through4. Use thesechaptersas
necessaryto configr:reyour boardbeforeinstallation.
To install your ADA2000, follow thesestep-by-stepprocedures:
1.TURN OFFTIIE POWERTO YOUR COMPUTERFIRST.Refero theowner'smanualfor vour
computer,and removethe top cover.
2. Selectan unusedexpansionslot in which to installyourboardandremoveits conespondingblank
bracketfrom the rear panelof the computerby removingthe suew at the op of the bracket.
3. Beforeplacingtheboardino thecomputer,threeribboncableassemblies
mustbe installedon
boardconnectonP8,P14,andP15.If you havepurchased
theADA2000cableset,first install
thetwistedpaircableanalogl/O
connecbrP8.TheninstallthesandardcablesonPl4
andPl5.
Eachcableis a 40-lineextemalVO cablewhichextendsthroughthe connectorslot in therear
panelof thecomputer.All threecablesrun througha singleslotwhererheyprovide120linesof
external I/O to the board.This configuration allows substantialboard VO through a single
expansionport in your computer.Appendix B liss the signal carried on eachpin of these
connectors.To install the cables:
a. Removethe strainrelief clamp attachedo the ADA2000 bracketlocatedon the righr side
of the board.
b. Connectthesocketconnectorto boardconnectorfor eachcable.Wheninstalling,observe
theconnectorkeying
andpressfirmly o makesurethateach
socketconnectoris
fully seated
on the board.Each cable providedis labeledwith the connector'sP numberfor easy
1a
t- I
identification. The cableshavestrainreliefs on one connectorand not on the other. The
connecbrwithout thestrainrelief is to beinsalled on theboard.After thecablesareinstalled
on the board,position themso that they pilssover the flange in the board's bracket.
c. Re-attachrheclampto thebracketusingthehardwaresuppliedwith yourADA2000, securing
the ribbon cablesin place.
4, After checkingthat the cablesarecorrectly insalled on the board,orient the boardinside the
computersothat the cablesextendthroughfte rearpanelopeningand the cardedgeconnector
lines up wittr the expansionslot connector.Then,pressdown on he metalbrackettab and the
top of the boarduntil the boardis firmly seatedin the expansionslot conneclor.
5. Securethe bracketback in placewith the screwandput the cover back on your computer.
Now your boardis readyto beconnectedvia theexternalconnectorsat therearof thecomputer.After theseconnections
havebeenmade,the boardis readyfor operation.
The Software
The ADA2000 operat€sunder softwarecontrol. Programmingincludesthe analoginput channelselectionand gain,
control of the the AID and D/A conversions,the prognmmable peripheral interfaces @PIl and PPI2), and the
programmableinterval timer. The analoginput channelandgainselections,takingan AID reading,and controlling the
D/A converterarecoveredin this chapter.Digial VO conrol throughPPII andPPI2 andcontrol of the programmable
interval timer aremorecomplex,andare describedin Chapter4, "hogramming Your ADA2000."
Regardlessof what programminglanguageyou use,you can write programsthat control the ADA2000 board. The
demonstrationdisk which accompaniesyour ADA2000 containsexamplesin Turbo C, Turbo Pascal,and BASIC.
Nearly all modemMS-DOS-basedPC languagestavellO referenceinstructions.Theseare theinsructions !o control
thedatatransfento andfrom theVO ports.Consultyourprogramminglanguagereferenceto find theseinstructionsfor
your favorite langunge.Listed below are the VO referenceinstructionsusedby somecommonlangneges.
inpufi
BASIC
INP
outpur ouT
TURBOPASCAL
Pon
Pon
TI,JRBOC
inportb
ouFortb
DemoDisk
Included with your ADA2000 is a demo disk which providesprogramminginstructionsand exampleprogramsfor
connolling the functionsof your interfaceboard.This demodisk is divided into directories,eachof which is named
accordingo the languageused to write the programsit contains.The files within each direcory contain example
programsanda documenationfile with generalinformation.In addition, your demodisk conrainsa READIvIE.DOC
file which providesprogramminginformationfor your board.
Eachexampleprognm showsyou how to controla particularboardfunction, suchasselectingan input channelor input
gain,controlling the A/D and D/A converters,controllingdigital dauatransfers,andseuingthe timer/countercircuitry.
Theseprogramsshouldbe usedto becomefamiliarwirh thesefunctions.
Also included in your ADA2000 packageis the ATLAI.ITIS dataacquisition softwaredemo disk. ATLANTIS is a
powerfulsoftwarepackagewritten exclusivelyfor RealTime Devices'A/D conversionboards.More informationabout
this easy-o-usesoftwareis availablefrom RealTime Devices,Inc.
Backing Up Your Disk
The demodisk providedwith the ADA2000is a double-sided
formatwhich canbe readby all DOS versions1.1and
above.Before using the softwareincludedwith your board,makea backupcopy of ttredisk. You may makeas many
backupsasyou need.To copytheoriginalto anyotherDOS-formatted
disk, insertthedisk to becopiedinto drive A of
your computer,and from DOS enter:
COPY A:*.* B: (or otherdestinationdrive specifier)
InitializingYour ADl2ooo
time you startup, reset'
Beforeyou canoperatethe ADA2000, it mustbe initialized.This stepmust be executedevery
If theboardis not
circuiury.
ppl
A/D
converter
the
with
properly
communicate
I to
or rebootthe computer.This setsup
your system'
you
reboot
to
requiring
probably
lock
up,
j1
will
iniriali2sd, will not respondo thesofwareiommandsand
Theseaddres
As describedearlier, the ADA2000 uses28 consecuriveaddresslocationsin thecomputer'sI/O space.
-2
I/c map,
provides
the
ADA2000
I
(hex).
Table
+
18
go
BA
(BA)
through
and
locarionsstarrwirh thebaseI/o address
hex. On
at
300
is
factory-set
addre'ss
base
rhat
the
Recatl
VO
conuols.
defining what function eachof the 28 addresses
I/O
address
base
conect
the
to
use
Remember
"board."
variable
in
the
sored
meOernoAish thebaseVOaddressis usually
in the
address
I/O
base
the
change
o
how
disk
explains
programs.
The
demo
your
own
in the demodisk prognms or
programs.
TheADA2000 is initialized by simptywriting a conrol byte to thePPIl control registermappedat theI/O locationbase
address+ 3 Oex). The conuol byte mrst conform !o this generalform:
lxxx x00x
wherex = don'tcare
circuitry'
tharrheeightVOlinesmakingupportBofPPIl, whichareusedtocontrolthemultiplexerandgain
Thisensures
[nes
available
areconfiguredasoutpurs.Thedon'r care(x) positionscontrolthedirccdonof theremaining16&gil€.IAO
configurations.
more
complex
in
other
or
inpus,
outputs,
as
can
configured
These
lines
be
PPII.
on
For example,when the control byte bit pauernis:
100000000(decimal128)
theADA2000is initializedasfollows:
I 28
out base-address+3,
Whenthis value is usedto inirialize theADA2000, theeight port C lines of PPI1will all be configuredasoutputs.You
can transferdatato theselines with the command:
outbase-address+2,data
If instead,
rhedecimalvalue13?(10001m1)isusedtoinitializetheADA2000,theportC lineswill besetupasinputs.
Youcaninputdatafrompon C with thecommand:
data= inp0ase-address+2)
signal.PPIImustbeprognmmed
NotettratponA,bitT (PA7)ofPPIl isfacory-settomonitortheend-of-convert(EOC)
so thatport A is an input if you aregoing to monitor theEOC signalthroughPA7. The conuol byte mustthenconform
to the generalform of lxx! x00x, wherethe underlinedI is thedatabit which ses up port A asan input
A functional descriptionof thePPIsis conained in Chapter2, "Functional Description,"andhardwareconfigurations
'TumperSettings."Informationabouthow you cancontrolthe digial VO linesis contained
aredescribedin Chapter3,
in Chapter4, "ProgrammingYour ADA2000," andis not coveredherebecauseof is complexity.
ThefourlSBs,
As mentionedearlier,tleeight linesofportB onPPIl areusedto selecttheanaloginputchannelandgain.
PB (for Port B) 0 throughPB3,controlthe channelselection,andthe four MSBs,PB4 throughPB7,controlthegain
of thisport is:
selection.The bit assignment
l-9
MSBs
7654
+/_,
gainselect
0000= 1x
0001= 2x
0010= 4x
0100= 8x
1000= 16x
LSBs
3210
PPIPortB (BaseAddress+1)
channelselect
0000= channel1
0001= channelz
0010
0011
0100
0101
0110
0111
1000
1001
1010
1 0 11
11 0 0
11 0 1
1 1 1 0= c h a n n e1l 5
1 1 1 1= c h a n n e1l 6
AftertheADA2O00is initialized,theportBregisterisloadedwith thedefaultsettingof00000000.This selectschannel
1 as the input channelwith a gain of l. To changethis value, for example,to a gain of 2x on channel16,enter these
commands:
BA + I (hex)
0001 111r
selecs port B
setsgainto 2x andchannelo 16
Recall that the board'sdefaultchannelsettingis eight differential channels.Therefore,only the channelselectbinary
valuesfor channelsI through8 apply.Channels9 through 16 are usedin the single-enCedihannelmodeonly.
Nowyourboardisinitializedandready
tooperate.
Thefollowingsecdonsdescribehow
to selecttheanaloginputchannel,
set the input gain, take an A/D reading,andconrol the D/A converter.Masteringtheseoperatio^ *ilt.llo*
you to
effectively useyour boardfor daa acquisitionapplications.
Selectingan AnalogInnut Channel
After the ADA2000 hasbeeninirinlizedyou canselectthe analoginput channel.The analoginput channelis
selected
by writing to PPI1porr B, mappedar I/O locarionbaseaddress(BAj + 1.
The input channelandtheinputgaincanbe setindividuallyby settingonly thefour LSBs (channel
select)or only the
fourMSBs(gain)of theeight-bitconrolwordsenttoPPI1portB. Beforeyouchangeeithertheinputchannel
ortheiain,
you MUST preservethe curent scateof port B. Failureto do so will result in changingboth
the ctrannelselectand the
gainwhenyou intendedrc changeonly oneof thesetwo settings.
Thegeneralalgorithmfor seuingthechannel(changingj ustthe four LSBs of thecontrol word while preserving
thefour
MSBs)is:
l-10
1. Readthe current stateof Port B:
1)
cunent-state- inp(base-address+
2. Preservethe upperfour bits sincethey containgain data:
curent-state = current-stateAND $F0
3. Ingicaly OR the current-statewittr ttredesiredchannelnumberminus l:
cunent_surte= curent_stateoR (channel- 1)
4. Write it back out !o port B:
l,current-state
out base-address+
A BASIC progranrn selectchannel2 is:
100BASE-ADDRESSTo= 768
ll0 CIIANNELTo= 2
+ l)
120STATUSTo= INP(BASE*ADDRESSVo
l30STAruS% = STATUSToAND &HFO
140STATUSZa= STATUSToOR (CHANNELTo-l)
+ I,STATUSTo
150OUT BASE-ADDRESSTo
settingthe Input Gain
Thegain is setby writing to the upperfour bits of PPII pon B at BA + 1. Thebit parem for eachof the five gain values
supportedby the hardwareare:
0000 = gain of I
0001= gainof2
0010= gainof 4
0100= gainof g
1000= gainof 16
It is recommendedthat no other bit patternsbe usedwhensettingthe gain.
The generalalgorithm for settingthe gain is:
1. Readthe current strateof port B:
gulgnr_State= inp(base_address+
l)
2. Preservethe lower four bits sincethey containchannelinformation:
current_state= curent_stae AND $0F
3. Iogically OR the currentjtate with a bit parternthat activatesthe desiredgain:
qs191r-St3t9= Curent_State
oR gain bit pattern:
1x bit pattern= 0
2x bitparern = 16
4x bit pauern= 32
8x bit pauern= 64
l6xbitpanern=
128
4. Write the current_statebackto port B:
l,current_state
out base_address+
l-i I
A BASICprogram!o seta gainof 2 is:
= 768
100BASE-ADDRESSTo
11966llrf/a = 2
120STATUSTo= IM(BASE-ADDRESSTo+ 1)
130STATUSTo= STATUSToAl'{D &HOF
l40IFGAINTo=1GOTO160
150STATUS%= STATUSTo
OR (GAINVo* 8)
160OUT BASE-ADDRESSTo
+1,STATUS7o
TakingSn A/Il Reading
After you haveselectedan analoginput channeland setthe gain, you €n take an AID reading.It is imporunt to note
that oncethe gain and channelareset,they stayat thoseseuingsuntil you changethem; that is, they are latched.You
do not haveto set the gain or channelevery time you takea reading.
Eachtime an A/D conversionis completed,an end-of-convert(EOC) signal is genented to signify the end of the
conversion.This signalcanbeusedinanumberofways.Oneway is o usethis line o monitortheA/D conversionstatus.
Sering up the EOC signal to be moniored involves configuring bit 7 of PPII port A or port C as an input line and
connectingthe EOC signalo it. This procedureis detailedin Chapter3, 'Tumper Secings."TheEOC signalis facorysetto be moniored throughPA7 on headerconnectorP6.
The generalalgorithm fontakingan A/D readingis:
1. Start a l2-bit conversionby writing to base_address
+ 4 (or 6):
out base_ad&ess+4,0
(Note that the valueyou sendis not importanl The act of writing to this I/O location is the key
to startinga conversion.)
2. Delay at least20 microseconds
or monitor PPI1Port A or C, bit 7 for a transirion.Polling
permitsthe fastestdataacquisition.
3. Readthe leastsignificantbit from base_address
+ 5 (or 7):
lsb%o= inp(base_address%o
+5)
4. Readthe mosrsignificantbit from base_address
+ 4 (or 6):
= inp(base_address%o
msb%o
+4'l
5. Combinetheminlo the 12-bitresultby shiftingtheLSB four birs o theright. TheMSB must
also be weightedcorrectly:
resultTo= (msb7o* 16)+ (lsb%ol
L6\
For a l2-bit conversion,theAlD datareadis left justified in a l6,bir word, with the leastsignificant fourbia equalto
zero,asshownin Figure l -6. Becauseof ttris,lhe two bytesof A7Ddatareadmustbe scaledo obtaina valid A7Dreading.
Onceit is calculated,thereadingcanbecorrelatedo a voltagevalueby scalingit, in thecaseof bipolarinput ong"s (tS
oril0 vols), andthenmultiplyingby theappropriatebir weighr,asshownin the able at theop of ttrefottowingpage:
MSB
D 1 s D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D8 D7 D6 D5
D4
D B 1 2D B 1 1D B l O ID B g DB8 D87 D86 D85 D84 D83 D82 DB1
Fig.1-6- A/D Conversion
WordFormat
I.T2
D3
0
02
0
Dl
0
LSB
D0
0
Input Range
5 volts
110 volts
0 to+10 vols
ScaleFactor
Subract2Ol8
Subract2048
None
Bit Weight
2.4414mY
4.8828mV
2.4414mY
For example,if the A/D readingis 1024andthe input rangeusedis t5 volts, theanaloginput voltage is calculatedas
follows:
(1021- 2048)birs * 2.414 mV/bir= -2.49999vols.
For a +10 volt input range,the voltageis calcularedasfollows:
QOA - 2M8) birs r'4.8828mV/bit= -4.99999volts.
For a 0 to +10 volt input range,no scalingis requiredandthe volage is calculatedasfollows:
1024birs* 2.4414mV/bit= 2.49999vots.
The input voltagerangeandpolarity arefacory-set accordingto customerspecificationswhenordering the board.If,
afterreceivingyourboard,youwishtochangetheinputvolage,seeChapter
3,'TumperSeoings."Wheneverthe
voltage
polarity is changed(unipolarto bipolar or vice versa),theA/D convertershouldberecalibratedasdescribedin Chapter
5, "Calibnationhocedures."
Note that eight-bit AiD conversionscanalsobeperformed.This is accomplishedby writing to I/O location BA + 5 (or
7). While an eight-bit conversionhasa lower resolutionthanthe 12-bitconversion,it is performedmuch morerapidly,
in about13microseconds.
A 12-bitconversion
takesabout20microseconds.
Therefore,
whenspeedisessential,youcan
usethe eight-bit conversioncapability.
Controlling the D/A Converter
The two analogouput channels,channelAOLITI andchannelAOUTZ, canbe independentlyprogrammedby writing
to internalregistersof the AD7537DIA converter.The ouputs canbe seto oneof four possibleouput voltageranges,
twounipolarandtwobipolar.Theseranges
arc0 to +5 volts,0to+10 volts,t5 volts,or+10 vols. Therangeofthefullscaleouput voltage is conrolled by the facory-installed voltagereferenceat IC location U15. The voltage rangeis
specifiedwhenorderingtheboard"REF-01providesa +IO-volt,reference
andREF42providesa+5-voltreference.If,
after receiving your berd, you wish to changethe voltagereferencefor theanalogoutputs,you must changetheIC in
locationU15.ReplacetheIC witlr PMI REF02or equivalentto setupa +5 voltreferenceorPMI REF01 o setupa+10
volt reference.
Theanalogouput channelscanbe independentlyconfiguredfor unipolaror bipolaroutputranges.Jumpersinsalled on
headerconnectorPlO selecttherangedesiredfor eachoutpur Both outputsarefactory-setto the samepolarity asthat
specifiedfor the AID inputs.Chapter3, "JumperSettings,"details how to changethesesettings.Noti ttrat only one
jumpershouldbeinstailedforeach
channel.Wheneverthe
voltagerange
orpolarityischanged,theD/Aconvertershould
be recalibratedasdescribedin Chapter5,'Calibrationprocedures."
Loading the D/A ConverterData
EachD/A channelhastwo eight-bitinternalinputregisterswhich receivethedatafor theD/A conversion.The channels
areprogmmmedindependentlyby writing daa to theseregisters.The D/A convert€rsusedon theADA2000 boardhave
a resolutionof 12 bits.Two write operationsarerequiredo loadthe 12-bitdau field into theseregisters.Oneregister
loadstheleastsignificantbyte
of thedatafieldandtheotherregister
loadsrhemostsignificantbyre
of rhedaa field"-Each
byteconrainsbits 0 through7, with bit 0 beingtheleastsignificantbit andbit 7 beingthemostsignificantbit in rhebyte.
Databis DBOthroughDB7 ue loadedinto theleastsignificantbyte,anddatabis DB8 rhroughDB I I areloadedinto
bits0 through3 of themostsignificantbyte.Thesettingof bits4 through7 of themostsignificantbytedoesnormatter
sincethey are not used.A sampleTurbo Pascalprogramfor generatinga channelAOUTI outputis:
l-13
Begrn
board:=$300
Write(Daa for channelAOUTf :);
Readln(a);
amsb:=(a div 256);
alsb:= (a - (amsb*25O);
Port[Board+$8]:= alsb;
Port[Board+$9];= amsb;
Port[Board+$C]:= 0;
erd.
The VO locationsthat control the D/A converterfturctionsare listed below from Table 1-2.
Function
PogramAOUT1LSB
ProgramAOUT1MSB
ProgramAOUT2LSB
ProgramAOUT2MSB
Conved/Update
AOUTl/AOUT2
ClearAOUTI/AOUT2
A4
0
0
0
0
A3
0
1
A1
AO
R/W
1
1
1
1
A2
0
0
0
0
0
0
1
1
0
1
0
1
w
w
w
1
0
1
0
x
x
x
W
W
x
W
BA + HEX
I
I
A
B
C,D,E,OTF
10,11,12,of
13
The inputregistersfor eachD/A converterareloadedby usingthecorrespondingbaseaddress+ hexvalueslistedabove.
To starta D/A conversion,a wrile operationto VO locationbaseaddress+ C, D, E, or F (selectone of theselocations)
mustbe executed-It doesnot matterwhat is writren; the act of writing to one of thesefour VO locationswill initiate a
D/A conversionin bothchannels.To clearthe ouputs of bothchannels,simply write to VO locationbaseaddress+ 10,
Ll,12, or 13.Again,theact of writing to any oneof thesefour locationswill clearthe outputs;the datawrittenis not
importanl Note tha theseouputs arealso clearedevery time a hardwaresystemresetoccus.
Output VoltageRangeand Resolution
The voltagerangeand bit weight (resolution)of the analogoutputsdependon thereferenceIC usedand whetherrhe
channelis setup for unipolaror bipolar outpus. The referenceIC canbe 5 or 10volts for both channels,dependingon
the IC type installedon the board.Eachchannelcan be individually controlled ro havea unipolar or bipolar outpur,
dependingon the settingof thejumperson headerconnectorPlO. The referencevoltageis customer-specifiedwhen
ordering,and theoutputdefault seuingfor both channelsis &e samepolarity as thatspecifiedfor ttreAID converter.
The possiblerangesand rheir conespondingbit weighs are:
Range
0 to +4.9988V
0 o +9.9976V
4.9976 o +5.0000V
-9.9951o+10.0000V
Bit lVeight
I.22mY
?.44mY
2.44mY
4.88mV
Thedaa writtentoeachpairof D/A channelinputregistersrepresenral2-bitdigitalvalueof thedesiredourput
voltage.
When theoutputis unipolar,a datavalueof zeroconespondsto zerovolts, anda full-scalevalue(all ones)corresponds
l-14
to ttre positive full-scale volage, either4.9988 volts or 9.9976volts. Intermediatevolage values are determinedby
multiplying rhe D/A daa by the appropriatebit weight, 1.22millivols or 2.M millivols.
In bipolar operation,the direction of the voluge changesfrom positiveto negativeasthe data value incteases.A dan
valueof zeroconespondsto the positivefull-scaleouput voltage,+5.0000vols or +10.0000volts. A full-scale value
(all ones) correspondso the negative full-scale output voltage, 4.9976 volts or -9.9951 vols. An algorithm for
determiningthe bipolar output voliageis given by the following equation:
Analog ouput voltage= +FS voltage- (Dle value)(bitweight)
+FS volage is the positive full-scale volage (+5 or+10 vols)
D/A value is the digital dataconvertedby the D/A converter
Bit weightis either2.44mY or 4.88mV.
The correladonof the D/A datavalues!o the outputvoltagesis summarizedbelow:
Analos Output
Unioolar
D/A Data
+5V
Bioolar
+10V
000000000000
100000000000
0
+2.5000
0
+5.0000
llll
{4.9988
+9 9976
llll
lr11
r-15
15v
+5.0000
0
4-9976
110V
+10.0000
0
-9.9951
l-16
CHAPTER2
FI]NCTIONAL DESCRIPTION
the
This chapterdescribesthe major functionsof the ADA2000 interfaceboard.Figure 2'1 showsa blak diagramof
board.The furrctionsdiscrssedin the following sectionsare:
. Analog-to-digial conversioncircuitry
. Digital-to-analogconvenion circuitry
. hogrammableperipheralinterfaceI (PPII)
. Programmableperipheral
interface2 ePI2)
. Programmableinterval timer @f$ circuitry
la A| LCi IrlFUng
{V lO.gt/
0 TO 116,
-lOv lO +loV
Fig.2-1- ADA2000Functional
BlockDiagram
2-r
Analog:to-TtigitalConversionCircuitry
One of the main fimctions of ttre ADA2000 interfaceboard is to provide high-speedanalog-to-digial conversion
capability fu daa acquisition.The analog-todigital (AlD) conversioncircuitry receivesinputsfrom eightdifferential
or 16 single-endedanalogchannels,selectsone active channel,and performsan analog-todigial conversionof the
voltagevalue readat that channel.The conversionthroughputrate is typically 38 kIIz.
Multiplexers
Two eight-bit analogmultiplexels areusedro connecteitheroneof 16 single-endedor one of eightdifferential analog
channelso thegain circuitry. The leftmostthreeswircheson DIP swirchSl setup the multiplexerat IC locationU9 o
receiveeither single-endedor differential inpus. Whenthesettree swirchesare up, the multiplexeris configuredfor
singlecndedinprts, andwhentheyaredown, themultiplexeris configuredfor differential inpus. Note that thesethree
swirchesare alwaysset as a goup to the sameposition (see"S1 Swirch Settings,"Chapter3). A channelis selected
throughsoftwarecontrol, by uniting tl Port B of PPII, asdescribedin Chapter1.
Gain Control Circuitry
Theprogrammablegaincontrolcircuitry
canprovideagainfactuof1,2,4,8,or 16.Thegainselectionismadebywriting
to Port B of PPI1,asdescribedin Chapterl. Thegain facor is conrolled by the seuingof four analogswirches.For a
gainof 2,4,8, o 16,thiswrite operarionwill closeoneofthefourswitches;fora gainfaclorof 1,allswirchesareopen.
Note thatprogramminggain facon other than0re five listed hereis notrccommended.
Sampleand Hold Circuitry
A sampleand hold (S/H) amplifier is usedbetweenthe gain control circuiry output and the A/D input to ensurethat
dynamicanalogsignalsareaccuratelydigitizedby theA/D converter.The .001pF hold capacitq usedin this circuit is
apolystyrenetneselectedforitslowdielectricabsorption.Islowvalueminimizestheacquisitiontime(6microseconds,
typical),andminimizesholdstepvolhgeanddroop.
Thesampleandholdtimeutdntearc&terminedbytheEOCsignal
generatedby the A/D converterand fed backino the S/H circuit WhentheEOC signalis high (logic l), the amplifier
samplesthe analoginpuq when the EOC signatis low Qogic0), the amplifier holdsthe input
A/D Converter
TheA/D conveneris a high-speedl2-bit convenionIC whichperformsconversionsin approximately20 microseconds.
Eight-bit conversionscanalsobe performedwhenspeedis morecritical thanresolution.An eight-bitconversiontakes
about 13 microseconds,allowing rapid conversionsof dynamicanaloginputs.The convertersupports10- or 2O-volt
analoginput signals;however,it cannotsupporta2O-voltunipolarinputrangebecause
is supplyvoltagein theADA2000
ap'plication
isonly+12 volts.Theanaloginputvoltageranges
supportedbytheADA2OCIarelistedin thespecifications
in Appendix A. Calibrationcircuiry is includedfor unipolarandbipolar catibrationof the A/D converter.Calibration
proceduresaredescribedin Chapter5.
An 8- or l2-bit conversionis initiated by a write operationto theaprpropriate
VO address.Oncea conversionis begun,
theconversionstatuscan be monitoredby readingtheA/D converterstatus(STS)signalwhich is ouput from the AID
converterIC andinvertedbeforebeingmadeavailableto othercircuitry on theboardastheend-of-convert@OC)signal.
TheEOCsignalcanbemonitoredbyoneofnvodigitalinputlinesonPPIl,PATorPC7.Notethatifeitherlineisselected
astheEOC monitor, a jumper mustbe installedfor the selectedline on P6 andthat line mustbe configuredasan input
The EOC signalis factory-setto be moniored throughPA7 on P6.TheEOC signalis low (logic 0) duringa conversion.
Figure2-2 showsthe EOC timing diagram.Also, the three-stateA/D outputbuffersremainin a high-impedancestate,
and,*terefore,datacannotbe read.While a conversionis in progress,any &ansidonsof thedigial inputswhich control
theconversionwillbe ignored,sothattheconversioncannotbeprematurely
terminatedorrestarted
Oncetheconversion
is complete@OC is now high, or logic 1), theAID datacanbe readin two bytes,the MSB and he LSB, in any order.
For a l2-bit conversion,the daa is left-justified in a lGbit word. In the caseof an eight-bit conversion,the data is
completelycontainedin theeight-bitMSB.
Referto Chapterl, 'Taking 4 d1D Reading,"as6 the demodisk for moreinformationaboutusingtheAID converter.
2-2
R/C
(ruwr-t
f f_
r-
1--
A/Dcs
*
ror
ll
Data
ff
*
Ftg.2-2 -EOC Timing Diagram
Digital-to-Analog ConversionCircuitry
inrerfaceboardcanouputthedigitizeddata
Byprovidingadigital-o-analog(D/A)conversioncapability,theADA2000
asanalogvoltageso be displayedon srip charts,oscilloscopes,andothersuchdevices.The datacanbe outputslow or
fast o supportspecificrequiremens.The D/A conversioncircuitry receivesl2-bit digital words (mappedinto a rightjustified nrobyte datafield) in its two independentchannelsand convertsthem to volage outpuB.
D/A Converter
TheD/A converterconsistsof two closelymarchedI 2-bit currentouput D/A convertersin onemonolithicIC to provide
twoanalogouputchannelsavailableatextemallr0connectorPS.
By usingduatconverters
in asinglepackage,excellent
thermalracking andmonoonicity acrossthe 12-bitrmge are mainained.Bottr D/A converterchannelsare internally
double-bufferedandcanbe updatedsimuluneouslyn preventvolage glircheson the outputs.Both convertersslryport
a 5- or lGvolt, umpolaror bipolar ouput voltagerange,dependingon the boardconfiguration.
The two convertersare identical l2-bit multiplying D/A oonverters,eachwith two pairs of input registen o allow
simultaneousupdatingof bothchannels.A conversionis initiatedby first loadingdatainto the first pair of registers.This
datais containedin two bytes(eight bits in the LSB and four bits in the MSB) which are \pritten into tlre registen as
describedin Chapterl, "Conrolting theD/A Converter."After theinputregistersareloaded,anupdatecommandwritten
to theD/A converterstars theactrul conversionprocess.Theoutputof theconverteris a currentvaluewhich accurately
represenbhe lz-bitdata word. Both channelscanbe clearedby writing o the appropriateVO addresslocation.
Output Amplifiers
The D/A converter'scurrent outputfrom eachchannelis fed througha high-speedprecision monolithic operational
amplifierwhereitis convertedintoaproportionalvoltageforoutputonexternalVOconnecorP8.Thisvoltageiseither
a unipolaror bipolarvalue,dependingon theconfigurationof theboard.Both op ampsarecontainedin oneIC prckage,
providing excellentslew rateand racking characteristics.
ProgrammablePerioheralfnterfaces
Two 8255prognmmableperipheralinterfaces@PIl andPPI2) provide40 TTIJCMOS digital VO lines which canbe
configuredin a numberof waysto supportuserrequiremens.EachPPI has24 digial VO lines.Theselires aregrouped
into threeeight-bit ports,port A, port B, andport C. Port C is furtlrer subdividedinto two four-bit porB, port C lower
(rcO-PC3) andport C upper(PC4-PC7)in certainmodesof operarion.The PPI datasheetis includedin Appendix C.
ThePPI is capableof threemodesof operation:
Mode 0 - Basic input/outpur Providessimple input and output operationsfor eachpon Daa is
'rniuen !o or read from a specifiedport.
Mode I - Snobedinput/output"hovides a meansfor transfeningVO daa o or from port A or pon
B in conjunctionwith snobesor handshakingsignats.
Mode2-Srobedbidirectional input/outputhovides abidirectionalmeansof communicaring
with
anotherdevice
ona singleeight-bitbw.Handshaking
signalsaresimilarto model. Thismodeapplies
to port A only.
2-3
In mode0, all fourpors (A, B, C lower, andC upper)areavailableasVO lines. Sixteenconfigurationsae possiblein
this mode,andanyport canbeconfigruedasan inputor anoutpuLTheoupus arelatched. r:ut theinputsarcnot latched.
'tataport (port A a pon B) and
In mode 1, ttrefogr ports aregroupedinto two groups.Fachgroupcontainsoneeight-bit
onefour-bit conuoVdauporr(port C lower or porr C upper)which is rsedfor conrol andsanrsof the eigtrt-bitporr The
eight-bit dataport in eachgroupcanbe configuredasan input or an outpuLBoth inpua andoutpus arelatched.
busandportCisa five-bitcontrolporl PortB cannotbeusedinthismode,
In mode2,portAisaneight-bitbidirectional
but is availablefor usein mode0 or mode I while port A is in mode2.Both inputsandoulputsare lalched.
EachPPI is configuredby writing a control word to the appropriateI0 addresslocation,as describedin Chapter4,
"ProgrammingYour ADA2000."
The conrrol word canalso be usedo individualty setorreset theport C biB. This feanre allowsany bit of pon C to be
setor resetwittrout affecting the otha pon C bits. The datasheetincludedin AppendixC explainsthis feaurc.
ThePPIcanalsobersed o generateintemrps in modeI or mode2 operation.In thesemodes,theintemrptenable(INTE)
maskis us€d!o enablettre INTRA urd INTRB intemrpt signals.Noa that the INTRB signalfor PPI1 cannotbe used
sinceport B of this PPI is alwaysconfiguredas mode0 outputandis reservedfor channelselectionand gaincontrol.
Intemrpt functionsare further explainedin the datastreetin AppendixC.
PPIl
PPI1 provides 16 digiral VO lines at extemalVO connecor Pl5 (seeTable B-4, AppendixB). The lines availablefor
digital VO areport A andport C. The eightbis of port B arereservedfor A/D channelselectionand gain control, and
cannotbe confignredfor VO use.Pore A andC cur beconfiguredin anyof the threeoperatingmodesdescribedabove.
The ADA2000 boardprovidesa headerconnecorwhichcanjumpertheAID converterend-of+onvert@OC)signal o
a PPII bit whereit canbe moniored to provideAID convenionstarus.The EOC signalcanbejumperedo eitherPA7
(port A, bit 7) or PC'7(port C, bit 7). Thedefaultsettingof thejumper is PA7. The port tsed to monitor theEOC signal
mustbe configuredas a mode0 input porc
PPIZ
PPI2hassomespecialcircuitry on 0reADA2000boardwhich enhancesits capabilities.All24 VO lines availablefrom
PPI2canbebufferedor shunted,aswell aspulledupor pulleddown.Thesesignalsareprovidedat externalVOconneclor
Pl4 (seeTableB-3, AppendixB).
The buffer circuitry allows PPI2to drive long cableswith ouput signalsandprovidesnoiseimmunity fc input signals.
However,bufferscannotbe rsedfor somepors whenoperatingin modesI or 2, or whendynamicallyctunging theport
directionthroughsoftwareconuol.On-boardDIP swirchesareincludedloblpassthebuffen. When*reseDlPswitches
areclosedandtheir correspondingbuffen areremoved,thenthe Il0 linesconrolled by themare shunted.Eachof the
four ports, A, B, CL, or CH, is conrolled by one DIP switch and buffer. The circumsuncesunder which shuns are
requiredin placeof the buffers are detailedin Chapter3,'Tumper Settings."
Resistornetworksarealsoprovidedo allow any or all of theportsto be pulled up or pulled down.Thesenetworkscan
inChapter3,'Tumper
asinpus.Resistornetwork
useisexplained
beusedonly whentheassociatedportsareconfigured
Settings."
ProgrammableInterval Timer (PIT)
Theprogrammableinterval timer (PIT) canbe configuredfor a varietyof timing andcountingfunctions.This versatile
IC containsthree independentlyclocked l6-bit timer/countercircuits, TC0, TCl, and TCZ, which opente as down
This circuit's most common
counte6. Thesedown counterscan resolvetime incremens down o 125 nanoseconds.
application is o provide accuratetime delays under softwarecontrol. Upon command,the PIT can count out a
programmeddelayandintemrpt thePCwhenit hasfinishedis asks.All &reecounteroutputsarebroughtout to external
VO connectorPl5.
The three l6bit timer/countersareeachloadedby two one-bytewrite operationsto the appropriatgl;ru*location.The
star$.Thecountdown
bytesarelatchedinto a l6-bit internalcountregister,wheretheyaresoreduntil thecountsequence
startswhen the countregistercontenBareransferred(in parallel)to the down counter.The timer/countercircuis can
be programmedfor binary or BCD countdowns.
24
A 5 MIIz crystal oscillaroron the ADA2000 can be usedto clock any timer/countercircuiL Or, the timer/countercan
be clockedby a sourceexternalto the boardthroughextemalI/O connectorPl5. Ratesof dc o 8 MlIz canbe usedto
clockthetimer/counters.
Eachtimer/countercanbe configuredfor oneof six modesof operation.Thesemodesare:
Mode 0 - Inrerupt on endof count.The OUT signalchangesfrom low o high whenthecountdown
is completed.
Mode I - Re-riggerableone-shot.A low-levelpulsetriggeredby theGT inputis outputon theOUT
pin.
Mode2-Rategenerator.
Mode 3 - Squarewavegenerator.
Mode 4 - Software-triggeredstrobe.
Mode 5 - Hardware-triggered
snobe(re-triggerable).
Thetimer/countercount,modes,
aswell asthecounttype@inaryorBCD),read/writemode,andcounter/timerselection
mode,areall part of thecontrol word which is written o thePIT control registero initialize the circuit When the PC
is poweredup, thetimerrcountercircuits arenot defineduntil theappropriatecontrol wordsarewritt€n to thecircuits to
programthemforoperadon.Initialization
isrequiredonlyonceafterapower-up
resetoccurs.
Detailedinformation
about
thePIT, includinghe controlword format,is given in thedatasheetin AppendixC
ThethreetimerrcountercircuitsareindependentHowever,tley canbe cascadedfor countdownswhich arelongerthan
one l6-bit field cansupporlFor example,TC0's OUT signalcanbe connecedto TCI's CK signal,andTCl's OUT
signalcan be connectedrc TC2's CK signal.When configuredttris way, the PIT can accommodate
extremelylong
countdowns.
Oneof thethreetimer/counter
outputs,TCOOUT, TCI OUT, or TC2 OUT, canalsobe usedasa PC intemrpLThese
signalsarebroughtoutto boardheaderconnecbrP5 whereone(andonly one)canbeselectedfor connectionto anyone
IRQ channel,IRQ2 throughIRQ7. Chapter3, "JumperSettings,"and Chapter4, "ProglammingYour ADA2000,"
describetheseinemrptsin moredetail.
2-5
2-6
CHAPTER3
JUMPERSETTINGS
This chapterdescribesthe ADA2000 boardseuingsyou canconrol on DIP switchesSI through54 andvariousheader
connectors.You canrse this chaptero tailor your board'sfunctionsto your specificapplicationbeforeinstalling it in
yourcomputer,or to changetheboard'sconfigurationasyou leammoreaboutits operationandspecialfeatures.In this
chaprer,you will learnabouteachsettingandhow !o setswitchesor installjumpersto achievethe desiredoperationof
yogr board"Beforechangingany senings,you shouldhavea functionalknowledgeof ttrecircuit you aresering up (see
Chapter2). Rememberthat all of the secingsdescribedin this chapterhavebeenfacory-set, or, as in the caseof the
intemrptsignals,aredisabled.Therefore,you do not haveto do any furtherset-upof theboardin orderfor it o opente
settings,ortotailor
in Chapterl.Thedescriptionsinthischapterallowyouo changefactory
inyoursystemasdescribed
your boardto takefull advanageof its built-in versatiliry.
Therearea DIP switch andseveralheaderconnecmrswhich allow you to control variousboardfunctions.In addition,
therearebuffers, threeshuntDIP switches,andresistornetworksassociatedwith oneof the programmableperipheral
interfaces,PPI2,which enhancethec4pabilityof this device'sdigital I/O. Theseareshownin theboardlayoutof Figure
3-1 andarepresentedas follows:
Sl - Analog Input SignalType DIP Swirch
Y2-Bas I/O AddressHeaderConnecor
P3- ProgrammableInterval Timer efD VO HeaderConnector
P4,P5, P7,and Pl l - Intemrpt HeaderConnectors
P6 - Endof-Convert (EOC) Monior HeaderConnecnr
P9- A/D Crnverter VoltageRangeHeaderConnector
PlO - D/A ConverterVoltage RangeHeaderConnector
P12- Digital VO HeaderConnector
Digital VO - Buffers, Shunts,and ResistorNetv/orks
;ni
'H!ffitr!
ltl
$n=fffi
nI
tl ! !
UJ=
i-""'rqhn'rrffin-
ILJi tUl
sl
-,'
3 l |l- -D-;:*
tl
:l lmP
L_l
n
-O
"rlr(-l--rc=-
iI
I|j
;LJn
=
tl
U
Fig.3-1- ADA2000BoardLayout
3-l
l._uo-
'34
.cl-
Sl - AnalogInput SignalType nIP Switch
DIP swiah Sl, shownin Figure 3-2, configuresthe muldplexersfor single-endedor differential inputs and selectsa
unrpolaror bipolar input voltagerange.The fint threeswitcheson S1 operateas a group. When theseare in the UP
position,themultiplexersareconfiguredforsingle-ended
inpus; whentheyareintheDOWNposition,themultiplexers
areconfiguredfor differential inpus. Notethat thesettueeswitchesmustall be setto the sameposition (UP or DOWN)
for the multiplexers!o function properly.The remainingswitch, S1-4,controls ttre input volbge polarity. When this
swirchis in theUP posidon,the input voltagerangeis unipolar;whenit is in the DOWN position, the voltage rangeis
bipolar. This switch, coupledwith thevoltagerangeselectionseton headerconnectorP9, determinesthe analoginput
voltagessupportedbytheAlDconverter.Nole thatwheneverthepolarityis changed,theAID convertercircuitry should
be calibratedas describedin Chapter5. The swirch seuingsareclearly labeledon the board o eliminate errors when
configuringS1.
TYPE
s.e
DIFF.
POL
nnnn
+l-
Fig.3-2- DIP Switch51
Hl - Baser/O AddressHeader Connector
HeaderconnectorP2controlsthe28 computerVO addresslocationsusedby the board.The baseI/O addresslocation
is setbyjumperingoneof theeightpositionson rheP2headerconnecror.The baseI/O addressis factory-setto 300 hex
(768decimal), with thejumper installedacrossthepair of pinsfifth from theleft on rheconneclor.Thebaset/O address
seningis fully explainedin Chapterl, "BaseI/O AddressSetting,"andis nor repeatedhere.Note the importanceof ttris
setringwith respectto thepossibilityof addresscontentionwith otherdevicesin your computer.Be sureto examinethis
possibility if you experienceboardfaihue when you frst auemptto operarethe board in your compurcr.
P3 - ProgfiammableInterval Timer (PIT) V0 HeaderConnector
HeaderconnectorP3, shownin Figue 3-3, controlsthe pr,ogrammable
interval timer @IT). The PIT containsthree
independentl6-bit timer/countercircuits,asdescribedin Chapter2. Eachtimer/counterhasthreeI/O signalsassociated
with iu a clock, a gale,and an output.P3 canbe configuredin a numberof ways to provide maximum versatility in
applying this deviceto your particularapplication.Eachdmer/counreris facrory-setfor XTAL clock input, +5V gate
input, and CO output. Figure 34 showsa block diagnm of rhePI?.
For easein configuring this circuitry, the headerconnectoris partitionedinto threefunctional $oups: TC0, TCl, and
TC2, whichcorrespondO timer/counter
0, timer/counterl, andtimer/counter
2, respectively.Thesedesignations
also
conespondto the manufacturer's
designations,
asshownon thedatasheetincludedin AppendixC. Srartingfrom the
top of P3, thefirst groupof pins on theright sidearelabeledCK0, GTO,andOIJT0, the tfueeVO signalsforTC0. The
signalson the left sidefor TCOarelabeledXTAL, EC0,+5V, EG0,COO,andedb ltnis signalhasa bar over rop of the
signalnameon theboardastheinversedesignation).Thegroupsof signalsfor TC 1andTC2 areidenticalo TC0, except
that eachhasa CK input on theleft sideof $e headerconneclor.Note thateachsignalnane on the right sideof the
connector(CK, GT, andOUT) spansa groupof two or threepins.Eachgoup canhaveonly onejumperinstalledat any
time.Thefollowing pamgaphsdescribehow thesesignalscanbe usedin thePIT circuit. An "x" is usedin placeof d,
1, or 2 in thesignalnarneswhenevertheapplicationcanbeappliedro anyor all of the threetimer/countercircuis.
3-2
P3
[:lta
-ll3
XTAL
EC0
+5V
EGO
|
co0
c-oT
Ells
cKl
l:llx
-lls
XTAL
EC1
+5V
EG1
|
co1
e6i
l_ll:
cKz
l:1l*
XTAL
EC2
+5V
EG2
l-lls
l-lls
co2
crc2Fig.3-3 -
PIT l/O Header Connectorp3
Counter Inputs:
XTAL - This input to all threetimer/countercircuis is from the5 MlIz crystaloscillator,labeledY I , locatednearrhe
centerof the board By connectingXTAL o the CIft input on the right side of rhe conneclorwith a jumper ptaced
horizontallybeween the pins,the 5 l,tfr{zclock is appliedto the timer/countercircuit. If requiredby yogr applicarion,
theXTAL frequencycanbechangedby installing a differentcrystaloscillaor at Y I . Note, however,that thema:rimum
frequencyat which ttrePIT will operareis 8 MIIz.
ECx-Thisinputallowsanexternalclochotherthan treXTALsignat,!ocontrolthetimingof thecorrespondingtimer/
countercircuir This pin canbe horizonally jumperedo theCKx input on theright sideof theconnector,in placeof the
xrAL source.The ECx sigrals are brought onlo ttre board through externalvo connectorpl5 (seetuub g+ in
Appendix B).
GateInputs:
+5V - This input' if connectedto the GTx input by placing a jumper horizontallybetweenthe two pins, placesthe
associatedtimer/countercircuit in an enabledstateat all times.
EGx - This input canbehorizontallyjumperedto theGTx inputon ttreright sideof theconnectorto provideanexrcmal
gateinput insteadof the +5 vols input The EGx signalsarebroughtono theboardttrough external connectorpl5
VO
(seeTable B-4 in Appendix B).
Counter Outputs:
jumpered
COx- Thisoutputcanbehorizonally
to theconeqponding
OUTpinontherightsideof ttreconnecror
so
that the clock ouput signalcanbe routed to extemal VO connectorpl5 (seeTabte84 in Appendix B).
COx - This output can be horizontallyjumpered to the correspondingOUT pin on the right sideof the connecbr to
provide tle inverseof ttreclock ourpursignal o externalVO connectorpl5 (seeTableBj in AppendixB).
3-3
CKx - This input connectstheouput of onetimer/countero ttreclock input of thenexttimer/counter.CIk is provided
for TCI and TC2 only, andis connectedto theoutputof the previoustimer/counter(tC0 or TCI) by placing ajumper
horizontallybetweenthepirs. Theseconnectionsareusedo cascadethe rimer&ountersfor longer time delaysthanare
supportedby a singletimer/countercircuir
Pl5
P3
8255 PIT
U5
;11--to
EC0
EGO
co0
XTALIO
DO
EC1
+sv-aQ
EG1
co1 <-To
o
"o1l
CK2I G
XTALrO6s2 -*fO
|
*5y-{
EG2
co2 -Tv,
t'o
I
I GT2
t
c-or;_o_
l
Fig. 3-4 -
PIT FunctionalBlock Diagram
P4. P5. P7. and Pll - Interrupt HeaderConnectors
HeaderconnectorsP4, Ps,Yl , andP1I areusedto jumper varioussignalsgeneratedby the ADA2000 circuity o the
PC's intemrpt channels.The intemrpt channelsavailableon the board are IRQ2 through IRQ7. Note that only one
intemrpt in the computersystemcanbeconnectedto an intemrpt channelat any given time.
Beforeattemptingto useinterrupts,you shouldbe familiar with theprocedurefor initiatizing the intemrpt vectorsand
the PC's intemrpt controller,and settingup the intemrpt handlingrourines.Theseproceduresare beyondthe scopeof
this manual,but mustbe understoodo effectively useintemrptsin you computersystem.
Becarefulto avoidcontention
whenselectingtheintemrptchannelsused,both
with thesignalson ttreADA2000aswell
as with other deviceswithin yor:r computer.To avoid contention,usethe table insidethe back cover of this manualto
recordthe intemrpt channelsyou usewith theADA2000 board.
It is also very importantto notethu ttreADA2000 intemrpt sorncesareTTL totem-pole@ushftull) type oupurs: they
arenot open-collector.Therefore,do not atrmpt to connectoneof theseintemrptsto any other intemrpt ouput.
The following paragraphsdescribethe intemrps availableon yotu ADA2000 board.
34
P4 - EXTINTI and PPII INTRA Interrupts
Headerconn@torp4 is usedto selectEXTINTI or PPII INTRA for connectionto one of the computer'sinternrpt
channelsIRQ2 through IRQ7. EXTINTI is provided to accommodatean intemrpt signal generatedexternal o the
ADA2000 androutedonto rheboardthroughextemalVO connecorP15(seeTableB-4 in AppendixB). PPII INTRA
gabeled lpC3 on the board)is generaredby PPII. This intemrpt is generatedduring PPI mode 1 or mode2 operation
only. Oneof thesenro signalscanbejumperedo oneof theavailablecomputerintemrpt chumelsIRQ2 thrcughIRQT
by ftrstplacing ajumper horizontallyacrossthepinsof the signalchosenandthenplacing a secondjumperhorizontally
acrossthe pins of the selectedIRQ channel.Figure3-5 showsheaderconnectorP4 with jumpen installedso that PPI1
INTRA is connectedto IRQ2.
EXTINTl
1PC3
tRoT
IRQ6
tR05
tR04
P4
rRo3
tR02
Fig.3-5- InteruptHeaderConnectorP4
PS- PIT OutputInterrupts
Headerconnector
P5,shownin Figure3{, is usedtojumperoneof thet}ueePIToutputs,OUT0,OUTI, or OUT2,o
IRQ2throughIRQ7.As in thecaseof P4,twojumpersmtst b installedo
oneof thecomputer'sintemrptchannels
across
thepinsof thePITouputselected.
First,installajumperhorizontally
connectaPIToutputtoanintemrptchannel.
jumperacross
Figure
intemptchannel
36
showsjumpersinsalledsothat
thepins
of
the
selected.
Theninsall a second
is
IRQ3.
OUT2 connected
to
IRQT
IRQ6
IRQ5
IRQ4
tR03
P5
tRo2
OUTO
OUTl
OUT2
Fig.3-6- lntemrptHeaderConnectorPS
(EOC)Interrupt
n - ND End-of-Convert
(EOC)signalo one
Headerconne*torHl, shownin Figure3-7,is usedtiojumpertheAID converter's
end-of-convert
IRQ2ttuoughIRQ7.TheEOCsignalis connected
inlemrptchannels
to anIRQchannel
of thecomputer's
by installing
Figure3-7showstheEOCsignalconnected
a singlejumperhorizonullyacrossthepinsof theIRQchannelselected.
to IRQ4.
3-5
T
o
P7
o
o
u,
7
6
5
4
3
2
E
P7
Fig.3-7- IntemrptHeaderConnector
Pll-EXTINT2
and PPI2INTRA and INTRB Interrupts
HeaderconnecorPllisusedoselectEXTINT2,PPI2INTRA,oTPPDINTRB forconnection!ooneof thecomputer's
an intemrpt signalgeneratedextemalto
intemrptchannelsIRQ2 throughtRQ7.EXTINT2 is providedto accommodate
(seeTableB-3inAppendixB).PPDINTRA
theADA2000androutedonotheboardttroughexternalVOconnectorPl4
(labeled2PC3on the board)andPPI2INTRB (labeled2PC! on the board)are generatedby PPI2.One of thesetlree
throughIRQTbyfirstplacingajumper
signalscanbejumperedtooneof
theavailablecomputerintemrptchannelslRQ2
horizonally acrossthe pins of thesignalchosenand thenplacing a secondjumper horizontally acrossthe pins of the
selectedIRQ channel.Figure3-8 showsheaderconnectorPl I with jumpersinstalledso that PPD INTRB is connected
toIRQ5.
Pl1
IRQT
tRo6
tRos
IRQ4
tRos
tRo2
2PC0
2PC3
EXTINT2
Fig.3-8- Intemrpt
HeaderConnector
P11
P5 -
End-of-Convert(EOC) Monitor HeaderConnector
As describedabove,the.{/D converterend-of-conven(EOC) signalcanbe used!o genente an intemrpt If this signal
is not usedasanintempt, it canbeusedasa statusmonitorof theAID conversionprocess.HeaderconnecorP6provides
two linesthroughwhich theEOCcanbemoniored, PPII PA7 or PPI1PC7. Oneof thesetwo digital VO linesis selecred
forEOC monicoringby insallingajumperhorizontallyacross
theappropriatepahofpins.
Thedigial VOlineselected,
PA7 or PC7,mustbe configuredasa mode0 input (seeChapter4, "ProgrammingYour ADA2000"). Figurc 3-9 shows
P6 with a jumper insalled in the factory-setposition for EOC monitoring throughPA7.
!
o
!
{
Fig.3-9- EOCMonitorHeaderConnectorP6
3-6
A/D Converter VoltageRangeHeaderConnector
Headerconnectorp9, shownin Figure 3-10, is usedto selectthe uralog input volage rangeof the AID converter.A
jumper is insalled vertically acrossthepins marlcedlOv to supporta lO-volt range(0 o 10volts or -5 o +5 volts), or
the pins marked20V o supporta 2Gvolr range(-10 0o+10 volts). The settingof thisjumper, coupledwith the
jelectsa unipolar or a bipolar range,determinesthe input voltagerangeof the A7D
"ooir
setringof Op swiah Sl-4 which
p9
factory
accordingo thecuslomer'sspecifrcationsfor theinputvoltagerange.Thevalid
conveiter. is configgredat the
serings of P9 and S14 are summarizedin the able below:
Pa -
Range
F9 Settlng
51-4 Settlng
-5 to +5 rohs
10V(right)
DOWN(bipolaQ
0 to +10volts
10V(right
UP (unipolar)
'10 to +10vohs
20V (left)
DOWN(bipolar)
Pg
VoftageRangeHeaderConnector
Fig.3-10- A/DConverter
PlO - D/A Converter Voltage RangeHeaderConnector
ofeachof thetwoD/Aconverter
showninFigure3-l l,isused toselecttheouputvoltagepolarity
HeaderconnectorPl0,
channels,AOUTIandAOUT2.Eachchannelcanbeindependentlyconfiguredasaunipolarouput(+)orabipolarouput
(+/-). To selectthepolarity for eachchannel,install ajumpervertically acrosseithertheunipolar(+) pins or thebipolar
(+/-) pins for tlre correspondingchannel.Note ttrat eachchannelmusthaveonejumper installedin order o function
inputpolarity.Ifyoureconfiguretheboardforadifferent
properly.Theouputsarefactory-set!omatchthespecifiedelD
outputrangethan that qpecifiedwhentheboardwasordered,thenyou mustrecalibratethe D/A converterfor the new
rangeaccordingo the instructionsin Chapter5.
AOUT1 AOUT2
++
+ +
P10
Fig.3-11- D/AConverterVoltageRangeHeaderConnector
Pt2 - Digital I/O HeaderConnector
Asdescribed
of thebuffereddigitalVOlinesofPPl2.
HeaderconnecorPl2,showninFigure3-12,controlsthedircction
in Chapter2, the24PPD digital I/O linesaregroupedinto nvo eight-bitgroups,port A @A0 throughPA7) andport B
(PB0 throughPB7), and two four-bit groups,port C low (PCOttrough PC3)and port C high (PC4 throughrcT.PIz
is labeledA, B, CL (port C low), and CH (port C high) on the right sideto conespondwith thePPI's groupstructue.
For eachgroupof lines to be buffered,a jumper mustbe installedhorizontally to selectthe directionthat the buffer is
to be configured:output (O) or input (I). To selectthedirectionof the dataat a port with respecto thePPI, position the
3-7
jqrnperhorizontallybesidetheO or theI for eachbufferedpst. Theboardis facory-setfor bufferedinputson all24
i'priogit"rVO[nes.Ifaparticularportisshuntedbyusingtheport'sDlPswirchandremovingthecomespondingbuffer'
Chapter2 andthesectionbelowaboutshunB,buffers,andresisom
thejumperonPl2 for thit portstrouldberemoved.
networksfurttrerexplainthePPI'spossibleconfigurations.
P12
o
l"
I
o
lp
I
o
I
o
I
Fig. 3-12 Digital r/O -
ls
E I,
Digitall/O HeaderConnectorP12
Ruffers.Shunts.and ResistorNetworks ( Figure 3-13)
hogrammableperipheralinterfacePPI2hasbuffersfor theinputor outputlineswhenoperatedin mode0. Whenoperated
in modeI or mode2, cerain PPI2port C lines functionashardshakingsignals;someareoutpub while othen areinputs.
52, 53, and54 allow
buffen cannotbeusedforsomeports,andDlPswirches
Therefore,whenoperatedin
thesemodes,
otre struntedTtpseswirchesareshowninFigure3-13,whichis ablowupof thePPI2circuitryon theboardtheseports
I,
ls
a
iil IJ
I
I
l8
l-
Pt2
6
*(-
OFig.3-13- PPlzCircuitry
3-8
Table3- I liss thecomponentlocationandtlpe of devicetsed for bufferinga port configruedfor mode0 operation.The
L and H listed for porr C refer !o the least significant (pon C lower) and most significant (port C upper) four bits,
respectively.Also listed in Table3-l arethe DIP swiah shuntlocationsfor eachof ttrepors. The numberslisted after
DIP switch 53 are the switchnumbersof ttreindividual shuns usedfor thetwo four-bit grorrysof port C. For buffered
theassociatedDlPswirches
VOs,rheassociatedDlPswitchesmustbeintheOFForOPENposition,andforshuntedlrOs,
from
theboardfor all shunted
removed
should
be
position.
buffe(s)
The
conesponding
musrbe in theON or CLOSED
VOs.
Table&1 - PPl2Buffers and Shunts
DIPSwitch
Shunt
Buffer
Locatlon
Buffer l}evice
PorlA
u21
7415245
PortB
74LS24s
Poil CL
u24
u23
s2
s4
74Ls'243
s3,5-8
PortCH
un.
74L5243
s3, 1-4
Port
To buffer the input or outputlines of a port' first be certainthatthe DIP switchfor thoselines hasall of is switchesset
to the OPENposition.Thenverify that thebuffer is insulled acccding o Table3-1.Finally, makesurethat thejumper
on conn@r(r P12 is positionedto correspordwith thedirectionthat thebuffer is o be configured.
The following sectionsdescribetheconditionsforeachmodewhenDIP swirchshuntsmustbeus€dinplace of thePPD
buffers.
Mode 0 Operation
If thedirection of a pon configuredfor mode0 operationis changeddynamicallythroughsoftware,all of the swirches
on thecorrespondingDIP swirchmrst besetto theCLOSEDpositionandthebuffer mustberemovedfor that porr This
usinga jumpr arPl2. Thereforetheir
isrequiredbecausethebuffersarehardware-configuredforaparticulardirection
direction cannotbe changedthroughsoftware.
buffer fromtheprintedcircuirboard.LocatethePPI2
After closingtheDIP swiahes,carefullyremovethecorresponding
port that requiresa DIP swirchshuntin Table3-1, thennotethecomponentlabelsof both thebuffer and the associated
DIP switch to verify that all settingsare asdesired.
In theeventthat shuntsarerequiredfor only onehalf of port C, the swircheson DIP switch 53 canbe closedin groups
of four. Determine their positions from Table 3-1, then close the appropriategloup of swirches.Only the buffer
correspondingto the half of port C that requiresshuntsmustbe removed(refer o the table for its location).
Mode l Operation
signals.Therefore,thebuffers
Whenoperatingagroupof linesin mode1,someof theportCbitsareusedashandshaking
that areinstalledar locationsU22 andU23 mustberemovedandDIP swirch53 musthaveall swirchesclosedo allow
for thetransmissionof thesesignalsin bottrdirections:botho andfrom port C. Buffersmay still beusedfor portsA and
B, input or outpul
As with mode0 operation,bufferscannotbe usedfor port A or port B if the modeI direction is changeddynamically
undersoftwarecontrol. In this case,the appropriateDIP swirchesmustbeclosedfor thesepots andthe corresponding
buffers removed.
Mode 2 Operation
This modealso usessomeof the port C bits for handshakingsigrnls. In addition,port A servesasa bidirectiond data
bus.Therefore,the buffers for pors A and C mustbe removedandreplacedby DIP swirch shunts.Refer to Table 3-l
for the locationsof the buffersand shuns for thesepors. Buffers may still be usedfor port B.
3-9
ResistorNetworks
The ppl2 circuitry alsoincludesprovisionsfor pull-up or pulldown resistornetworts for eachof tlrefour ports (A, B,
CL, andCII); however,re,sistoncanonly be usedwhen theport is configuredasan input porr The boardprovidesIC
forPPI2'sdigitalVO.RNl andRN4are10-pinSIPs,
locarionsRNlthroughRN4toaccommodateSlPresisornetworks
andRN2 andRN3 aresix-pin SIPs.Pin I is commono all resisors. Any valueresisor canbe used;lnwever, for pullup applications,resistorsof 10 kilohms or higherare recommended.
Table 3-2- PPl2 ReslsilorNetworks
Gomponent
Locatlon
Numberof
Plns
PortA
RN1
10
Poil B
RN4
10
PortCL
RN3
6
PortCH
RN2
6
Port
When uing resistornetworks,you must first determinewhich lines ytxr want !o pull up or down and theninstall the
resistornerworksaccordingto Table 3-2.\\e PPI2 port tabel is stampedon the printed circuit board next to its RN
componentlocationfor easein determiningthecorrectresistornetwork socket.
After theresisorpacksareinstalled,you mustconnectthemino thecircuitaspull-ups orpull-downs. Locatethethreeholepadson theboardneartheresisor pacls. Theyarelabeled+5V qr oneendandGND (for ground)on theotherend.
The middlehole is common.One ttree-hole pad is locatednext to eachof the four SIP IC sockets.Figure l-14 shows
a blowup of ttrepadsfor Port A. To operateaspull-ups, soldera jumper wire betweenthe commonpin (middle pin of
the three)andthe +5V pin. For pulldowns, soldera jumper wire betrveenthe commonpin (middle prn) and the GND
pin.
I
I
ResistorCircuitry
Fig.3-14- PPl2PortA Pull-up/Pull-down
3-10
CHAPTER4
PROGRAMMING YOUR ADA2OOO
All communicationwith the ADM000 interfaceboardis doneby strobing datato and from the board using the I/O
referenceinstnrctions.Most operarionsinvolve the transferof data to or from the componenB' internal registers.
However,someqerations requireonly that a particularVo addressbe written to; the datawritten is irrelevant These
I/O locationsarereferencedtothe ADA2000 baseL0 address(BA) determinedby thejumper settingof connectfiP2'.
and configuation'
ChapterI describesthe baseIr0 addressconsiderations
through
softwareinclude the analoginput channelselectionand
controUed
functions
The datacollection and support
peripheralinterfaces@PIl and PPI2)' and the
programmable
the
D/A
conversions,
gain, control of the ttre ep and
of theboard,theanaloginput channeland
operation
ba.sic
integral
!o
the
are
they
Because
progammableinte6raltimer.
gain selections,takingan AyD reading,andconfolling the D/A converterarecoveredin Chapterf . Digital IIO contol
throughppll and pplZ anCcontrol of the programmableinterval timer are more complex, and are describedin this
chapter.
yoru ADA2ffiO containexamplesin Turbo C, Turbo Pascal,andBASIC.
The demonstationrlisk which accompanies
Nearly all mgdernMS-DOS-basedPC languageshaveIr0 referenceinstructions.Theseare the instructionsto control
Oe Oararansfen o andfrom ttreVO pors. Consultyourprogramminglanguagereferenceo find ttreseinstmctionsfor
your favorite language.
Selectingan AnalogInput Channel
Seethis sectionin Chapterl.
Settingthe Input Gain
Seethis sectionin Chapterl.
Taking an A/rr Reading
Seethis sectionin Chapter1.
Controllingthe D/A Converter
Seethis sectionin Chapter1.
hogramrning the ProgrammablePeripheralInterfaces
Eachprogrammableperipheralinterface@PI) hastlueeeight-bit parallelVO ports, port A, port B, and port C, which
canbeconfiguredfor a varietyof applications.PPII has16linesavailableatextemalVOconnectorPl5 for VO use;the
eightbis ofport B (PB0-PB7)are usedfor channelselectionandgain control andcannotbe usedfor otlrerfunctions.
PPI2has^1124VO lines availableat externalVO connecorP14.
ThePPI pors canbe operatedin oneof threemodes.Themodeof operationandthe signaldirectionof eachport (input
oroutput) arecontrolledby aneight-bitcontrol wordwritten o anintemalregister.Two bits definethe modeselection:
mode0, mode1, or mode2. Four bits configuretheI0 direction:onebit to control PA0-PA7,onebit !o control PBG
PB7,onebito controlPC0-f€3,andonebittoconsolPC4-PC7.PortC is dividedino two four-bitfieldssothatitcan
provide statusand control for pors A and B if desiredin your application.The conrol word is defined in Figure 4-1.
EachPPI is configuredby writing a control word to the PPI's internalcontrol register.Upon power-up,all ports are
configuredasmode0 inputs.PPI1 is uritten o duringboardinitialization so thatport B is setup asa mode0 output to
configureit for channelselectionandgain connol functions.Chapterl, "Initializing Your ADA2000," describesthis
procedure.
4-l
D7 D6
D5 D4
D3 D2 D1 DO
J
GROUPB
PORTC (LOWER)
I = TNPUT
O= OUTPUT
PORTB
1 = INPUT
0 = OUTPUT
MODESELECTION
0 = lroDE0
1 = lvlODE'l
GROUPA
PORTC (UPPER)
1 = INPUT
O= OUTPUT
PORTA
1 = TNPUT
O= OUTPUT
MODESELECNON
00 = MODE0
01 = MODE1
lX = MODE2
MODESETFI.AG
1 = ACTIVE
Fig.4-1- PPIModeDefinition
Format
TheVOlocationsthatconuolPPII andPPIZue listedbelowfromTablet-2.
FUNCTION
A4
A3
A2
A1
AO
R/W
BA + HEX
PortA
PortB (ChannelSel&Gain)
PortC
0
0
0
0
0
0
0
0
0
0
0
0
R/W
1
0
Fvw
0
1
2
1
1
1
'l
1
1
1
1
0
0
0
o
0
0
PPIl
1
w
PPI2
PortA
PortB
PortC
ControlWord
1
1
0
ww
1
0
R/W
R/W
1
w
18
19
1A
1B
Becausethe PPI can be configuredfor a wide rangeof operatingmodesand programmingrequirements,it is heavily
dependenton correctly understandinghow to usethepropercontrol byte to configurethePPI for your application.The
demodisk includesexampleprogams that show how to selectthecommonoperatingmodes.Readingthesourcecode
is highly recommended.
The following examplesshow how to configure PPI2 for the most commonoperatingmodes.PPI1 can be similarly
configuredby using is VO locationsin placeofPPI2's locations,exceptftat port B canneverbeconfigrnedasaninput.
4-2
All linesdigital input:
= 768
10BASE-ADDRESSTo
20 CONTROL-BYTEVo= &H9B
+ 2T,CONTROL-BYTETo
30 OUT BASE-ADDRESSTo
+24)
40 A-DATATo = INP(BASE-ADDRESSVo
50 B-DATATo= IM@ASF-ADDRESSTo+ 25)
+ 26)
60 C DATATa= INP(BASE-ADnRESSTo
All linesdigial outpuc
=768
10 BASE-ADDRESSTo
20CONTROL BYTETo=&H80
30 OIJI BASE-ADDRESSTo
+ 24,A-DATAVo
40 OI-rf BASE-ADDRESSTo
+ 25,8-D N AVo
50 OUT BASE-ADDRESSTo
+ 26,C-D ATAVo
For morc informationaboutthe operationof thePPI, seethe dau sheetincludedin Appendix C.
Programmingthe ProgrammableIntervalTimer
The programmableinterval tirner (?IT) can be configuredfor a variety of timing and coundngfunctions.The PIT's
versatility is supplementedby the useof headerconnectorP3 for jumpering variousVO options.Chapter3, "Jumper
Senings,"describes
this conneclor.
ThePIT consissof threeindependentl6-bit downcounters.Thecountersareinitialized for operationin anyof six modes
by writing datato theappropriateconrol wordfor eachcounter.Counterdatais thenwritten o or readfrom eachof the
countersby accessingthree additionalinternalregisten. The daa is set up in a two-byte format, eachbyte serially
accessible
on thedaa bus.The I/O locationsthatcontrolthePIT arelistedbelowfrom Tabte t-2.
PITFUNCTION
Counter0
Counter1
Counter2
ControlWord
A4
1
1
1
1
A3
A2
A1
AO
R/W
0
0
0
0
1
1
1
1
0
0
0
1
1
0
R/W
R/W
H/W
1
1
w
BA + HEX
14
15
16
17
Your specificrequirements
will determinehow the individuattimer/countersshouldbe configured.The datasheet
includedin AppendixC providestheinformationrequiredto controlthe PIT.
The softwareincludedon thedemodiskshowsexampleprogramsfor conrolling someof thePIT operatingmodes.
Thesignalsgenerated
by 0reOUT pinsfor anyof thecountersmaybe connectedto oneof thePC's intemrptchannels
usingjumpersinstalledatconnectorP5.
Referto the"Hardwarelnterrupts"
sectionbelowformoreinformationonusing
theOUT signalsto generateinterrupts.
HardwareInterrupts
Fourjumperconnectors,
labeledP4,P5,P7 md Pll, areprovidedon the ADA2000 to enableintemrptsgenerated
by
theA/D converter,
thePIT,thePPIs,andtwoexternalsources
to thePC'sintemrptchannels
IRQ2throughIRQZ.Chapter
3,'TumperSettings,"explainshow theseheaderconnectors
canbe configured.
Beforeyouattemptto useinterrupts,besureyouarefamiliarwith theprocedurefor initializingtheintemrptvectorsand
thePC's interruptcontroller,andsettingup theinterrupthandlingroutines.
4-3
A"/DConverterEnd-of-Convert(EOC) Signal
theselected
TheA/D converterEOC
signalcanbeusedtogenerate
anintemrpttothePC.Anintemrptwilloccur(through
intemrpt channel)to indicatea convenion is completeapproximately20 microseconds
after theconversionis initiated.
The EOC signal is invertedbeforebeingappliedto the intemrptchannel.It makesa low-o-high transitionat the
ThetimingoftheEOCsignal
completionofeachconversioncycle,andremainshighuntilanotherconversionisinitiated.
is shownin Figure2-Z,Chapwr2.
PPI Interrupts
The intenups generatedin PPI mode I andmode2 operationcanbejumperedo any of thePCintemrptchannelsIRQ2
through IRQ7. The timing of theseintemrps is shownon the PPI datasheetincludedin AppendixC.
The PPI interruptsmustbe enabledby writing a "1" to the INTE maskbit of theparticularPPIasdescribedin the data
sheetunder"Intemrpt ControlFunctions."TheINTE maskbits aredisabledduringpower-upresetandwheneverfie PPI
modeis changed.
PIT Interrupts
One of the OUTO,OUTI, or OUT2 signalsgeneratedby the PIT can be jumpered o a PC intemrpt channelusing
connectorP5.
When using a PIT OUT signalas an intemrpt, you mustbe very careful !o ensurethat the PC system'sprogrammable
interruptconroller @IC) is properly configuredto ignoreintemrptson theselectedintemrptchannelimmediatelyafter
power-up.This is necessarybecausethePIT mustfust be inilialized o definethedesiredmode(s)of operation. Prior
to initialization,themode,count,andouput of all countersareundefined.If thesystemintemrpsarenotdisabled,the
counteroutputsmaycauseenatic systembehavior.
CHAPTER5
CALIBRATION PROCEDT]RES
This chaptercontainscalibrationproceduresfor the A/D converterinput voltagerange,theA/D convertergain,andthe
theADA2000AID andD/Aconvertersare
Theoffsetandfull-scaleperformanceof
D/Aconverteroutputvoltagerange.
your
given
when
orderwasplaced.The gaincircuitry is also
facory-calibratedaccordingo thespecificatiorsthatwere
verify theaccuracy
of these
shipped.Thefollowingprocedureallowsyoutoquickly
facory-calibratedbeforetheboardis
readings
are
suspected,
inaccurate
whenever
circuis. This procedureshouldbe doneapproximatelyeverysix months,
or wheneverthe voltagerangesarc changed.
Calibrationis performedwith a properly configuredADA2000 installedin the PC. Apply power to the computerand
allow the ADA2000 circuitry o sabilize for 15 minutes.
RequiredFluipment
Thefollowing equipmentis requiredfor calibration:
. PrecisionVoltageSource:0 o +10 volts
. Digital Voltmetec 5-ll2 drgit
. 4" JumperWire
. Small Screwdriver(for rimpot adjustment)
Figrye5-l showstheboardlayouf The fimpos referencedin the following proceduresaregroupedin theuppercenter
areaof the board.
ift
I
il
tl I
L]
rqmnffi[ffin-
rl,,_,,--i%m*."
nlllril
=UryM? M:.y$.ilEl
!tl
-]$'nt:Pk="n=*
'tJY"=Un llE
=:'
lllJ"r-r:-$.
0-'[
:l
ljfF
:'!_:;l
'
li;
ul lll Es=
,fli-;l li,I ln"g,'E,ci:€,[
ns--rJ li;|il tl
r-i
-r
F
-1
-
-E=-El-'
r-, E
n n-
I
r..
qL_3
:|lt
ql*jr
lFq
.O
nllffi
I lU uo-
tl:
i-rull ft-rft-r
\J-lz-
PQ.O-
Fig. 5-l - ADA2000 Board Layout
A/D Calibration
During this procedure,connectionsmustbe madeto someof the analoginpuS on externalVO connectorP8, available
at the rear panelof the computer.The pin assignmentsfor this connectorare given in TableB-2, Appendix B.
to completelycalibratetheA/D converterfor unipolaror bipolar operation.Theseaffect
Two adjustrnentsarenecessary
usinguimpoaTR5
theADA2000circuitry.Bothcalibrationstepsareperformed
rheoffsetandfull-scaleperformanceof
andTR6 or TR6 and TR7. Trimpot TR5 or TR7 is usedo zero the offset error of the AID converterand trimpot TR6
is usedfor full-scaleadjustmenrIn the following procedure,useanaloginput channelI and set it for a gain of 1. This
is accomplished
by writing all zeroesto I/O addresslocationBA + l. Be certainthatposition4 of switchS1 is setfor
thedesiredpolarity and 8rejumper on connectorP9 is set for l0V.
5-1
Unipolar Calibration
Two adjustmentsare necessaryto calibratethe A/D converterfor the unipolarvoltagerangeof 0 o +10 volts, one for
offset and one for full scale.To adjusttheoffset,a very low analoginput voltage,shownunderthe "Offset" headingin
the following table,is connectedo thechannel1 inputof themultiplexer(P8-1).The groundreferenceof this sigrul
shouldbe connectedto P8-2. While continuouslydisplaying 12-bit A/D conversions,adjustTR7 until the AID dala
flickers betweenthe two valueslisted in the tableunder"Offsel"
value.Whilethefull-scaleinputvoltagelisted
made,thenTR6isusedtoadjustthefull-scale
Aftertheoffsetadjustmentis
in the able is not the actualfull-scale voltagefor an ideal 0 !o +10 volt range,it is the maximumvoltage at which the
A/D conversionis gruranteedo be linear.Any valueabovethis voltagemaynot belinearandthusmay adverselyaffect
calibration. After connectingthe full-scalevoltagelisted in the table o the ctriannelI input, adjust TR6 until the daa
flicken benveenthe two valuesin the able under "Full Scale."
Inout Voltase
A/D Data
Unipolar Calibration
(0 to +10 volts ranse)
Offset ffR7)
+I-2?n70millivolts
00000m00000
0(m0(mffnr
Full ScaleffR6)
+9.49829volts
111r00lt 0010
1lll00l1mll
Bipolar Calibration
Whetheryouareselectingthebipolarinputvoltagerangeof-5 to +5 volrsor -10o +10 volts,thefollowingcalibration
procedurecan only be performedwith &e boardconfiguredfor a -5 to +5 volt input voltragennge. This meansthat the
jumperonheaderconnectorP9
mustbeinstalledacross
the10Vpins.If youareusingthe-10to+10 voltrange,reposition
jumperon
you
pins
perform
P9 acros the 20V
the
after
thecalibrationproceduresbelow.
Two adjustmentsarc necessaryto calibratetheA/D converterfor bipolarvoltageranges,onefor offset and onefor full
scale.To adjusttheoffset,connectthevoltageshownunderthe"Offset" headingin theable belowto the channelI input
of the multiplexer. While continuouslydisplaying 12-bit A/D conversions,adjrstTR5 until the data flickers benveen
the two valueslisted in thetableunder"Offset." Next, connectthe full-scalevolage listed in the able o the channelI
input and adjust TR6 until thedataflickers beween the two valuesin thetableunder"Full Scale."
Bipolar Calibration
(.5 to +5 volts or -10 to +10 volts ranse)
Offset ffR5)
InputVoltase
4.99878vols
NDData
000000000000
000000000001
Full ScalemR6)
+4.9963 volts
t11l1il1lll0
l l l l 1 1 1 11 1 1 1
Table5- I providesa referencefor theidealinput voltagefor theA,/Dconverterfor eachbit weight in eachvoltagerange.
This able showstheidealfull-scale(all ones)valuein thefirst line anddecrements
by onebit weight eachline thereafter.
Note that thesevaluesarefor l2-bit A/D conversions,andarenot valid whenusinglhe convertero perform morerapid
Notethatthevoltagevaluesin thetablearein millivolts.
eight-bitconversions.
Table5-l - AID ConverterBit weiqhts
A/DBitWeisht
a095(Full-Scale)
2M8
lv24
512
256
r28
&
32
16
8
4
2
I
0
t5 Volts
+4;997.6
0000.0
Ideal Inout Voltase (millivolts)
+10 Volts
+9995.1
0000.0
-s000.0
-7500.0
-87s0.0
-9375.0
-9687.5
-9843.8
-992r.9
-99ffi.9
,9980.5
-9990.2
-9995.r
-25m.0
-3750.0
4375.0
46n.5
4843.8
492r.9
49ffi.9
4980.5
49n.2
4995.r
4997.6
-5(m.0
0 to +10Volts
+9997.6
+5000.0
+2500.0
+1250.0
+625.00
+312.50
+156.250
+78.125
+39.063
+19.5313
+9.7656
+4.8828
+2.44L4
offm
Gain Circuitry Calibration
circuitry,oneforeachof thegains2,4,8,and16.Tocalibrate
Fourrimpots,TRl throughTR4,areusedtoadjustthegain
this circuiry, apply ur input voltageof +39.063millivolts to the input of channell. Next, by writing the conect word
to the BA +l I/C location,set thegain to 2 andadjustuimpot TRI to obain the 12-bit AID converteroutput for your
board'svolage range,aslisted in Table 5-2. Then,repeatthis procedurefor eachof the remainingthreegain settings,
adjustingthe appropriatetimpot until achievingttrecorrectvalue listed in the table.
Tabfes2 - A/D ConverterReadinostor GainCalibratlon
Gain
2
4
8
16
Trimoot
TRl
TR2
TR3
TR4
Inout VoltaeeRanse
t10 Volts
+5 Volts
100000100000
100001000000
100010000000
100100000000
100000010000
100000100000
100001000000
100010000000
0 to +10 Volts
000000100000
000001000000
000010000000
0(nr ffxnoffx)
DiA Calibration
The D/A convertercanbe usedin eithera unipolaror a bipolar configuration.Eachhasa different calibrationprocedure.
Both D/A converterchannels
arefacory calibratedfor outputswhichareset!o matchthespecifiedAID inputpolarity.
If you are verifying unipolar output accruacy,follow the unipolar calibradonprocedurebelow. If you havebipolar
outputs,follow the bipolar calibrationprocedurebelow.
Unipolar Calibration
Two adjustmentsarenecessaryto calibratetheD/A converterfor full-scaleunipolaroperation,onefor eachof the two
converterchannels.This procedureusesrimpos TR8 andTR9 to makethe adjustments.
fortheanalogoutputs.
Thefull-scaleadjustmentcalibrates
thereferencevoltageusedby
theD/Aconvertertocompensate
by monitoringtheoutputvoltageofeachchannelatexternalVOconnectorPS
andadjusting
Calibrationisaccomplished
the appropriarcrimpot" The analogoutput, its P8 pin assignment,and is associatedtrimpot are:
Output
AOUTl
AOUT2
Trimpot
P8 Pin Assignment
33 (SIGNAL),34(GND)
36(GND)
35(STGNAL),
TR9
TR8
5-3
Prognm ttreD/A converterto output a full-scalevoltageby writing )GFF o baseVO addresslocationsBA + 8 and
present
BA+9 forAOUTI,and BA+ AandBA+ B forAOUT2. Usethedigitalvoltmetertomonitortheoutputvoltage
betweenthe appropriateP8 signal and groundpins. Using Table 5-3, adjust the appropriatetrimpot until the voltage
equalsthe full-scalevoltagein Table 5-3 asmeasuredby the voltmeter.
Table5-3 liss themaximumD/A unipolaroutputvoltagefor eachbit weight in a 12-bitconversionfor +5- and+ l0-volt
references.Note that the voltagevaluesin the tableare in millivolts.
Iable 5.3 - D/A ConvenerBii Welohts(Unioolar)
Ideal Output Vottage(miilivolts)
0 to +10 Volts
0 to +5 Volts
D/A Bit Weisht
4095(tull-scaleoutput)
2M8
4998.8
2500.0
r250.0
625.00
312.50
156.250
78.r25
39.063
19.5313
9.7656
4.8828
2.4414
t.2207
rou
512
256
r28
&
32
t6
8
4
2
I
o
oofiY)
9997.6
5000.0
2500.0
1250.0
625.00
312.50
r56.250
78.r25
39.063
19.5313
9.7656
4.8828
2.Mr4
oilm
Bipolar Calibration
Calibrationof theD/A outputswhenconfiguredfor bipolar operationinvolvesboth a mid-scaleadjustmentand a fullscaleadjusrnentfor eachouput channel.The trimpotsassociatedwith eachadjusrnentand the analogoutput P8 pin
assignmenBfor measuringthe outputvoltageare:
Output
AOUT1
AOUT2
Mid-Scale
Trimpot
TR9
TR8
Full-Scale
Trimpot
TR10
TRll
Pt Pin Assignment
33 (SIGNAL),34 (GND)
35 (STGNAL),36(GND)
Programthe D/A converterto output a mid-scalevoltageby writing X800 to baseI/O addresslocationsBA + 8 and
BA + 9 for AOUT I , andBA + A andBA + B for AOUT2. Usethedigital voltmeterto monitor the outputvoltagepresent
betweentheappropriateP8signalandgroundpins.Adjust theappropriatetrimpot sothattheouput voltageis zerovolts.
Next, calibratethefull-scale voltageoutpur For full-scalecalibration,prognm theD/A convertero outputa full-scale
voltagebywritingXFFFtobaseVOaddresslocationsBA+8andBA+9forAOUTI,andBA+AandBA+Bfor
AOUT2. Use thedigital voltmeterto monitortheoutputvoltagepresentbetweentheappropriateP8 signalandground
pins. Adjust the appropriatetrimpot until the voltage equalsthe full-scale voltage in Table 5-4 as measuredby the
voltmeter.Table5-4 liss themaximumD/A bipolaroutputvoltagefor eachbit weightin a l2-bit conversionfor +5- and
+IO-volt references.
Note thatthevoltagevaluesin theuble arein millivols.
54
Table 5-4 D/A Bit Weicht
4095(full-scaleoutput)
20/8
rca
5r2
E6
r28
&
32
t6
8
4
2
I
0
D/A Converter Blt Welshts (Blpolar)
Ideal Output Voltage (millivolts)
+5 Volts
t10 Volts
4997.5
m00.0
+2500.0
+3750.0
+4375.0
+4687.5
+4843.8
+4921.9
+4960.9
+4980.5
+4990.2
4995.1
+{;997.6
+5000.0
-9995.r
0000.0
+5000.0
+7500.0
+8750.0
+9375.0
+9687.5
+9843.8
+9921.9
+9960.9
+9980.5
+9990.2
+9995.1
+10000.0
APPENDIX A
SPECIFICATIONS
ADA2OOO
ADA2OOO
SPECIFICATIONS
Gypical at25"C)
Interface:
IBM PCDff/AT compatible
Jumper-selecablebaseaddress,VO mapped
intemrps
Jumper-selectable
AnalogInputs:
8 differential or 16 single+ndedinpus, swirch-selectable
..... >10 megohms
eachchannel
Input impedance,
I,2,4,8, or 16
Gains,softwareselectable
0.5VotYP,lVomax
Gainerru
Input options: lGvolt range*(Option 1)..........Bipolart5V
Linearity...............15V
Guaranteed
lGvolt range*(Option2)..........Unipolar0 to +lOV
0 to +9.5V
Linearity...............
Guaranteed
2O-voltrange*(Option3)..........BipolartlO V
Linearity...............19.5V
Guaranteed
..........Jumper-selectable
Range..........
Switch-selectable
Polarity
3 Usecmax
Sealingtime .............
-.-,....+10V
Commonmodeinputvoltage
+35 Vdc
Ovenroltageprotection
*Erratic readingscanoccurbeyondspecifiedinput volage ranges.
A"/DConverter:
Successive
approximation
Type............
12bits
l0-voltrange...........
Resolution:
Q.44mYhit)
20-voltrurge
........ lzbis (4.88mVibit)
Chip-selectableconvenion speed: Option 0 .... 20 Usectyp, 25 Usecmax
Option| .... 12 Usectyp, 15psecmax
typ,9 Usecmax
Option2 ....8 prsec
tl bit typ
Linearity
psecmax
acquisitiontime ......................6
Sample-and-hold
kHz
...............38
Throughput
Counter/Timer:
Three l6-bit 8 MHz down counlers
DigitalVO Lines:
40 TryCMOS-compatible(24buffered,16rnbuffered)
D/A Converter:
Anatogoutputs
.........2
Resolution...
12bits
Relativeaccuracy
..... tl bit max
+3 bis max
Full-scaleaccu:tcy
11 bit max
Non-linearity
td;;;::::::::.:::::::::::::::::::..a, o" ryp
channel-o-channel
AnalogOutput:
Option 1 .... 0 to +5V;
jumper-selecable
to t5V
Option2 ....0 !o +l0V;
jumper-selectableto + I 0V
Settlingtime,to 0.017oFSR
..........1.8psectyp, -3.3psecmax
+1/2 bit typ
7*ro enor....
90 dB typ
Crossalk.....
.........l0mA
Ouputcurent,max..............
outputrange:
Chip-selectable
MiscellaneousVOs:
!12V, +5V, PC bus-sourced
Ground,PC bus-sourced
Two exlernalintemrpt inputs
Resetouput
Power Requirenents:
+5 Volts
+12Vols
-l2Vols
VO Connectors:
Three40-pin box headers(one dedicatedo analogsignalsonly)
All 120signalsexit throughonerearpanel slot in the PC
Environmental:
Operatingtemperature.
Soragetempenfire.
Humidiry.....
Size:
260 mA
30 mA
35 mA
0o+70oC
. 40 to +85"C
0a907o non-condensing
3.875"(99mm)
10.40"Q& mm)
Herght
Widrh...........
A-2
APPENDIX B
CONNECTOR PIN ASSIGNMENTS
CONNECTOR
Table B-l-Mating
ASSIGNMENTS
External VO Connectors for P8, P14, and P15
Connector No.
Manufacturer
Part Number
P8
P14
P15
3M
RobinsonNugent
Mil c-83503
yn-1ua
IDS.C4OPK.C.SR-TG
M83503t-09
Table B-2-P8 Connector Pin Assignments
Pin No.
I
3
5
I
9
lt
13
15
t7
19
2l
23
25
27
29
31
33
35
37
39
Signal Name
Pin No.
Signal Name
DIFF / SE
AINI+ / AINI
AINI. / AIN9
AIN2+/ AIN2
AIN2. / AIN1O
AIN3+ / AIN3
AIN3- / AINll
AIN4+ / AIN4
AIN4. / AINI2
AIN5+ / AIN5
AIN5- / AINI3
AIN6+ / AIN6
AIN6. / AINI4
AINT+ / AINT
AIN7. / AIN15
AINS+ / AIN8
AINS- / ArNl6
AOI.JTI
AOUT2
+12 VOLTS
-12 VOLTS
)
4
6
8
10
t2
t4
16
l8
20
22
24
26
28
30
32
34
36
38
40
GND
GND
GND
GND
GND
GND
GND
GND
GND
GI.{D
GND
GND
GND
GI{D
GND
GND
GND
GND
GND
GND
Table 8.3-P14
Connector Pin Assignments
Pin No.
Signal Name
Pin No.
Signal Name
I
GI{D
+5 VOLTS
Gl{D
GND
GI{D
EXTINTz
2PA7
2PA5
2PA3
2PA1
2PC7
2PC5
2PC3
2PCr
?PB7
2PB5
2PB3
2PB1
+12VOLTS
-12vol-Ts
)
+5 VOLTS
GND
GND
GND
GND
GND
2PA6
ZPA4
2PA2
2PAO
2PC6
2PC4
2PC2
2PC0
2PB6
zPV
2PB2
2PBO
RESETDRV
GI{D
J
)
7
9
1l
13
15
t7
l9
2l
23
25
27
29
31
JJ
35
37
3g
Table 8.4-Pl5
A
6
8
10
t2
t4
16
18
20
22
24
26
28
30
32
34
36
38
40
Connector Pin Assignments
Pin No.
Signal Name
Pin No.
Signal Name
I
3
5
7
9
11
13
l5
t7
19
2l
23
25
27
29
GND
1PA7
1PA5
1PA3
IPAI
GND
1PC7
)
EXTINTI
IPA6
1PA4
3r
JJ
35
5t
39
lPc5
lPc3
lPcl
GND
EXTCLKO
CLKOUTO/ CLKOUTOEXTCLKl
cLKOLrrl /cLKOrJrlEXTCLK2
CLKOUT2/CLKOUT2.
+5 VOLTS
GND
+12VOLTS
6
8
l0
t2
14
l6
18
20
)J
.A
26
28
30
32
34
36
38
40
rPA2
lPAO
GND
lPc6
1PC4
LPC2
1PCO
GND
EXTGA1EO
GND
EXTGATET
GND
EXTGATE2
GND
+5 VOLTS
GND
-12volTs
APPENDIX C
COMPONENT DATA SHEETS
InterualTimer
Intel82C54Programmable
DataSheetReprint
intel'
82C54
TIMER
INTERVAL
CHMOSPROGRAMMABLE
I Compatlblewlth all Intelandmost
other microprocessors
r High Speed,"Zero WaitState"
Operationwlth 8 MHz8086/88and
80186/188
I HandlesInputsfrom DCto 8 MHz
- 10 MHzlor 82C54-2
r AvallableIn EXPRESS
- StandardTemperatureRange
- ExtendedTemperatureRange
I Three independent16-bitcounters
I Low PoweTCHMOS
- lcc = 10 mA @8 MHzCount
frequencY
I CompletelyTTL ComPatlble
CounterModes
I Six Programmable
r Binaryor BCDcounting
I StatusReadBackCommand
I AvalfableIn 24-PlnDIP and 28-PlnPLCC
whichis
CHMOSversionof the industrystandard8254counter/timer
The fntel82C54is a high-performance,
systemdesign.lt providesthree
designedto solvethe timingcontrolproblemscommonin microcomputer
clockinputsup to 10 MHz.All modesare sottware
16-bitcounters,
eachcapableof handling
independent
pin
programmable.
with
the
HMOS
8254,andis a supersetof the 8253.
The 82C54is
compatible
timer modesallowthe 82C54to be used as an evenl counter.elapsedtime indicator,
Six programmable
programmable
one-shot,andin manyotherapplications.
The 82C54is tabricatedon Intel'sadvancedCHMOSlll technologywhichprovideslow powerconsumption
HMOSproduct.The82C54is availablein 24-pinDIP
equalto or great€rthanthe equivalent
with performance
(PLCC)
packages.
plastic
leaded
chip
carrier
and 28-pin
r.osr
co$rER
tP
oa
t
Or
6
02
,
Or
I
*
t212tn?3
t
ctr0
tac
o
fi
tl{rSifto
231241-3
PTASTICLEAOEDCHIPCARRIEB
Dt
I
Dr
a
03
0.
I
O!
231211-l
Flgure1.82C54BlockDlagram
a
(
o? a
Dr ,
Oo I
clr 0 I
our 0 r0
OAIEO il
cr{D
i2
2a
t3
a,
21
t0
rt
Ycc
ll
ctt 2
t7
ou7e
z
t3
rg
ta
tt
in
tu
63
lr
lo
cll'l
cltE r
ottr
Diagramsarefor pin referenceonly.
Packag€sizesare not to scal€.
n12u-2
Flgure2.82951Pinout
S.ptGrnbcr 1989
Otrlrr l{umDc|: 23 12a{.{rc5
intef
82C54
Table 1. Pln Descrlption
Symbol
Dz-Do
CLK O
OUTO
GATEO
GND
OUT1
GATE 1
CLK 1
GATE2
OUT2
CLK2
Ar,Ao
DIP
1-8
PlnNumber
PLCC
2-9
I
10
11
10
12
13
12
13
14
16
17
18
19
20
14
15
16
17
18
20-19
21
Function
t/o
I
Data:Bidirectionaltri-state
data bus lines,
connectedto svstemdata bus.
Clock0: Clockinputof Counter0.
o
Output0: Outputof Counter0.
I
Gate0: Gateinputof Counter0.
Ground:Powersupplyconnection.
o
1
Out1:Outputof Counter
I
Gate 1: Gateinputof Counter1.
Clock1:Clockinputof Counter1
I
Gate 2: Gateinputof Counter2.
o
Out2: Outoutof Counter2.
Clock2: Glockinputof Counter2.
I
23-22
6
21
24
m
22
26
WR
23
27
Vcn
24
NC
TyPe
Address:Usedto selectone of the three Counters
or the ControlWordRegisterfor read or write
operations.Normallyconnectedto the system
addressbus.
As
Ar
Selects
0
Counter0
0
1
0
Counter1
1
0
Counter2
1
Reqister
1
ControlWord
ChipSelectA lowonthisinputenablesthe82C54
to respondto FiDandWFisignals.FIDandWF are
ignoredothenrise.
ReadControl:Thisinputis low duringCPU read
operations.
WriteControl:Thisinputis low duringCPU write
operations.
Power * 5Vpowersupplyconnection.
No Connect
28
1 ,1 1 ,1 5 , 2 5
sireddelay.After the desireddelay, the 82C54 will
int€nuptthe CPU.Softwareoverheadis minimaland
variablelengthdelayscan easilybe accommodated.
FUNCTIONAL
DESCRIPTION
General
The 82C54is a programnableintervaltimer/counter
designedfor use with lntel microcomputersystems.
It is a generalpurpose,multi-timingelementthat can
be treated as an anay of llO ports in the system
software.
The 82C54 solves one of the most common problems in any microcomputersystem,the generation
of accurate time delays under software control. Insteadof settingup timingloopsin software,the programmerconfiguresthe 82C54to matchhis requirementsand programsone of the countersfor the de3-84
Someof the othercounter/timerfunctionscommon
to microcomputers
which can be implementedwith
the 82C54are:
o
r
r
r
o
r
r
o
Realtime clock
Even counter
Digitalone.shot
rate generator
Programmable
Squarewave generator
Binaryratemultiplier
Complexwaveformgenerator
Complexmotorcontroller
inbr
82C54
CONTFOLWORDREGISTER
Block Diagram
The ControlWord Register(seeFigure4) is selected
by the Read/WriteLogicwhen Ar, Ao = 11. lf the
CPU then does a write operationto lhe 82G54,the
data is stored in the Control Word Registerand is
interpretedas a Control Word used to define the
operationof the Counters.
DATABUSBUFFER
8-bitbufferis usedto in'
This3-state,bi-directional,
tertacethe 82C54to the systembus(seeFigure3).
The ControlWord Registercan only be writtento;
status informationis availablewith the Read-Back
Command.
6D
9t
cs
l-o+
FI
z,31214-4
Flgure 3. Block DlagramShowlngData Bus
Buffer and Read/Wrlte Loglc Functions
231214-3
READ/WRITELOGIC
The Read/Write Logic accePtsinputsfrom the system bus and generatescontrol signalsfor the other
functionalblocks of the 82C54.A1 and As select
one of the three countersor the ControlWord ReE
ter to be read from/written into. A "low" on the RD
input tells the 82C54 that the CPqjg readingone of
the counters.A "low" on the WR input tells the
82C54that the CPU is writing eithera ControlWord
or an initialcount.Both RD and WFIare qualifiedby
6; ffi and WFI are ignored unlessthe 82C54 has
been selectedby holdingCS low.
Flguretf. Block DiagramShowing ControlWord
Registerand Counter Functlons
'1,
couNTER O,COUNTER COUNTER2
These three functionalblocks are identicalin operation, so only a singleCounterwill be described.The
internalblock diagramof a singlecounteris shown
in Figure5.
The Countersare fully independent.Each Counter
may operatein a differentMode.
The ControtWord Registeris shown in the figure;it
is not part of the Counter itself, but its contents determine how the Counteroperates.
3-85
intef
82C5{
storedin theCRandlatertransfenedto the CE.The
ControlLogicallowsone registerat a time to be
loadedfromthe intemalbus. Both bytesare transfenedto the CE simultaneously.
CRy and CRLare
clearedwhen the Counteris programmed.
In this
way,if the Counterhas been programmed
for one
bytecounts(eithermostsignificant
byteonlyor least
significantbyte only) the other byte will be zero.
NotethattheCEcannotbe writteninto;whenevera
countis wriften,it is writteninto the CR.
TheControlLogicis alsoshownin thediagram.CLK
n, GATEn, andOUTn are all connectedto the outsideworldthroughthe GontrolLogic.
82C54SYSTEMINTERFACE
231241-6
Figure5.InternalBlockDiagramof a Counter
The status register, shown in the Figure, when
latched,containsthe cunent contentsof the Control
Word Register and status of the output and null
count flag. (See detailed explanationof the ReadBack command.)
The actualcounterlslabelledCE (for "CountingEl+
ment"). lt is a 16-bitpresettablesynchronousdown
counter.
OLy and OLs are two 8-bit latches. OL stands for
"Output Latch"; the subscripts M and L stand for
"Most significantbyte" and "Least significantbyte"
respectively.Both are normally refsrred to as ona
unit and calledjust OL. Theselatchesnormally"follow" the CE, but if a suitable Counter Latch Command is s€nt to the 82G54,the latches"latch" th€
presentcount until read by the CPU and then retum
to "following" the CE. On€ latch at a time is enabled
by the counler's Control Logic to drive the internal
bus. This is how the 16-bitCountercommunicates
over the 8-bit internal bus. Note that the CE itself
cannot be read; wheneveryou read the count, it is
the OL that is beingread.
Similarly,there are two 8-bit registers cailed CFty
and CR1 (for "Count Register").Both are normally
refened to as one unit a,rd calledjust CR. When a
new count is written to the Counter,the count is
3-86
The82C54is treatedby the systemssoftwareas an
l/O ports;threearecountersand
anayol peripheral
the fourthis a controlregisterfor MODEprogramming.
Basically,
theselectinputsAo,A1connectto the A9.
41 addressbussignalsof the CPU.TheC-Scan be
deriveddirectlyfromthe addressbususinga linear
selectmethod.Or it canbe connectedto the output
of a decoder,suchas an Intel 8205for largersystems.
&
to
Cl
bOr
fU
tlel.
couirtt
cot ttft
counEt
ott
oul oltc ctr' 'ot t oatc clr' 'our cltt cu'
Figure6.82C54SystemInterface
intet
82C54
DESCRIPTION
OPERATIONAL
Programmingthe 82C54
General
by writinga ControlWord
Counters
areprogrammed
forrnatis
andthenan initialcount.Thecontrolword
shownin Figure7.
After power-up,the state of the 82C54 is undefined.
The Mode, count value,and outputof all Counters
are undefined.
How each Counteroperatesis determinedwhen it is
programmed.Each Counter must be programmed
beforeit can be used.Unusedcountersneed not be
programmed.
All ControlWordsare writteninto the ControlWord
whichis selectedwhenA1,Ao : 11.The
Register,
ControlWorditselfspecifieswhichCounteris being
programmed.
By contrast,initialcountsare writtenintothe CounTheA1,Ag inters,not the ControlWordRegister.
putsare usedto selectthe Counterto be written
by
into.Thetormatof the initialcountis determined
the ControlWordused.
Control Word Format
A1,As=11 G:0
R-D=1 WFi:0
D7
D5
sc1 sc0
D5
Da
sco
0
0
0
D6
lr - iloDE:
]i2
ill
Irl0
SelectCounter0
0
0
Mode0
1
SelectCounter1
0
0
0
't
1
0
SelectCounter2
X
1
0
Mode2
1
1
Read-BackCommand
(SeeReadOperatlons)
x
1
1
Mode3
1
0
0
Mode4
1
0
I
Mode5
RW - Read/Write:
RWI RWo
0
D1
RW1 RWO M2 M 1 MO BCD
SC- SelectCounter:
scl
D2
D3
0
Mode1
BCD:
CounterLatchCommand(see Read
Operations)
0
0
1
Read/Writeleastsignificantbyteonly.
1
0
Read/Writemostsignificantbyte only.
1
1
Read/Writeleastsignificantbytefirst,
then mostsignificantbyte.
1
BinaryCounter16-bits
BinaryCodedDecimal(BCD)Counter
(4Decades)
NOTE: Don't care bits (X) shouldbe 0 to insure
compatibilitywith future lntel products.
Figure7. ControlWordFormat
3-87
intef
82C54
structionsequenceis required.Any programming
aboveis acsequencethat followsthe conventions
ceptable.
WriteOperations
procedurefor the 82C54is very
The programming
flexible.Onlytwo conventionsneed to be remembered:
1) For each Counter,the ControlWord must bE
writtenbeforethe initialcountis written.
2) The initialcount must tollow the countformat
specifiedin the ControlWord (leastsignificant
byteonly,mostsignificant
byteonly,or leastsignificantbyteandthenmostsignificant
byte).
A new initiatcount maybe writtento a Counterat
any time without atfecting the Counter's programmedModein anyway.Countingwill be affected
The newcount
in the Modedefinitions.
as described
countformat.
mustfollowthe programmed
to readlwritetwo-byte
lf a Counteris programmed
applies:A program
counts,the followingprecaution
must not transfercontrolbetweenwritingthe first
andsecondbyteto anotherroutinewhichalsowrites
intothat sameCounter.Othenrise,thE Counterwill
be loadedwith an inconectcount.
Sincethe ControlWord Registerand the three
Countershaveseparateaddresses(selectedby the
Ar, Aoinputs),andeachControlWord
the
specifies
Counterit appliesto (SC0,SCl bits),no specialinCounter
0
Counter
0
Counter
0
Counter1
Counter1
Counter1
Counter2
Counter2
counter2
A1
11
00
00
11
01
01
11
10
10
Ao
ControlWordLSBof countMSBofcountControlWordLSBof countMSBof countControlWordLSBof countMSBof count-
Counter0
Counter1
Counter
2
Counter
2
Counter1
Counter
0
Counter
0
Counter1
Counter
2
A1
11
11
11
10
01
00
00
01
10
A6
ControlWordCounterWordC,ontrolWordLSBof countLSBof countLSBof countMSBof countMSBof countMSBof count-
ControlWordControlWordControlWordLSBof countMSBof countLSBof countMSBof countLSBof countMSBof count-
Counter2
Counter1
Counter0
2
Counter
Counter2
Counter1
Counter1
Counter0
Counter0
- Counter1
ControlWord
- Counter0
ControlWord
LSBof count- Counter1
GontrolWord- Counter2
LSBof count* Counter
0
MSBof count- Counter
1
Counter2
LSBof countMSBof count- Counter
0
MSBof count- Counter
2
A1
11
11
11
10
10
Aq
o1
01
00
00
A1
11
11
01
11
00
01
10
00
10
Ao
NOTE:
In all four examples,all countersare programmedto readlwritstwo-bytecounts.
Thesears only four of manypossibleprogramming
sequences.
Figure 8. A Few PossibleProgrammingSequences
ReadOperations
It is often desirableto read th€ value of a Counter
withoutdisturbingthe countin progress.Thisis easily done in the 82C54.
There are three possible methods for readingthe
counters: a simple read operation, the Counter
Latch Command,and the Read-BackCommand.
Eachis explainedbelow.The first method is to perform a simple read operation.To read the Counter,
which is selectedwith the A1, A0 inputs, the CLK
input of the selectedCountermust be inhibitedby
usingeither the GATE input or external logic. Otherwise,the count may be in the processof changing
when it is read,givingan undefinedresult.
3-88
intef
82C54
grammingoperationsof other Countersmay be in'
serted betweenthem.
COUNTERLATCH COMMAND
The second method uses the "Counter LatchCommand". Like a ControlWord,this commandis written
to the Control Word Register, which is selected
when A1, Ao : 11. Also like a ControlWord,the
SCO,SC1 bits select one of the three Counters,but
two other bits, DS and D4, distinguishthiscommand
from a ControlWord.
D5
sc1 sc0
D5 Dl
D3 D2 D1 Ds
0
X
0
X
X
lf a Gounter is programmedto read/write two-byte
counts, the followingprecautionapplies;A program
must not transfer control between readingthe first
and second byte to anotherroutinewhichalso reads
from that same Counter. Othenrise, an inconect
count will be read.
X
SC1, SCO- specifycounterto be latched
scl
1. Read leastsignificant.bYte.
2. Writenew leastsignificantbyte.
3. Readmost significantbyte.
4. Write new most significantbyle.
0 ; F D= 1 ;W F : 0
A r ' A o : 1 1 ;6 :
D7
Another feature of the 82C54 is that reads and
writes of the same Countermay be interleaved;for
example,if the Counteris programmedfor two byte
counts,the followingsequenceis valid.
sco
Counter
READ.BACKCOMMAND
0
1
2
Read-BackCommand
The third method uses the Read-Backcommand.
This commandallowsthe user to check the count
value, programmedMode, and cunent state of the
OUT pin and Null Gountflag of the selectedcounter(s).
D5,D4 - 00 designatesCounter Latch Command
X - don't care
NOTE:
Don'tcare bits (X) shouldbe 0 to insurecompatibility
withfutureInlelproducts.
The commandis written into the GontrolWord Register and has the format shown in Figure10. The
command applies to the counters selected by setbits D3,D2,D1= 1.
ting their corresponding
Figure 9. Counter Latchlng CommandFormat
A 0 , A 1: 1 . t
The selected counter's outputlatch (oL) latchesthe
count at the time the Counter Latch Commandis
received.This count is held in the latch untilit is read
by the CPU (or until the Counteris reprogrammed).
The count is then unlatchedautomaticallyand the
OL returnsto "following"the countingelement(CE).
This allows reading the contents of the Counters
"on the fly" withoutaffectingcountingin progress.
MultipleCounterLatch Commandsmay be usedto
latch more than one Counter.Each latchedCounter's OL holds its count untilit is read.CounterLatch
Commands do not affect the programmedMode of
the Counterin any way.
lf a Counter is latched and then, some time later,
latched again before the count is read, the second
Counter Latch Commandis ignored.The count read
will be the count at the time the first CounterLatch
Commandwas issued.
With either method, the counl must be read according to the programmedformat; sPecifically,if the
Counter is programmed lor two byte counts, two
bytes must be read.The two bytes do not haveto be
read one right after the other; read or write or pro-
I
I
I
I
I
I
6:o
FD:1
WF=o
D5: 0 = Latchcount of selectedcounter(s)
Da:0 : Latchstatusof selectedcounter(s)
D3: 1 = Selectcounter2
D2: 1 : Selectcounler1
Dr: 1 : Selectcounter0
Dq: Reservedfor fulure expansion;mustbe 0
Figure 10.Read-BackCommandFormat
The read-backcommandmaybe usedto latchmultiple counter output latches (OL) by setting the
COUNT bit D5:0 and selectingthe desiredcounte(s). This single commandis funclionallyequivalent to several counter latch commands,one for
each counter latched.Each counter'slatchedcount
is held until it is read (or the counter is reprogrammed).That counter is automaticallyunlatched
when read, but other counters remain latched until
they are read.ll multiplecount read-backcommands
are issued to the same counter withoutreadingthe
3-89
irrbf
82C54
count all but the first are ignored;i.e.,the count
whichwill be readis the countat the timethe first
read-back
commandwasissued.
THISACTION:
A. Writ€to the control
wordregister:ht
B. Writeto the count
r"gitt"i(cR);t2l
C. Newcountis loade_d
inrocE (cR -+ cE);
TherEad-back
commandmayalsobe usedto latch
stalusinformation
ot selectedcounter(s)by setting
ffifG
bit D4-0. Statusmust be tatcfr6O
to be
read;statusof a counteris accessEdby a readfrom
thatcounter.
CAUSES:
Nullcount= 1
Nullcount= 1
Nullcount=0
tll Onty th€ counterspecifiedby the control word will
hav€ its null count set to 1. Null count bits of other
countersare unaffectad.
t2l lf th€ counter is programmedfor two-byte counts
(least significantbyte then most significantbyt6) null
count goes to I wh€n the secondbyte is written.
Thecounterstatusformatis shownin Figure11.Eits
D5 throughDOcontainthe counter'sprogrammed
Modeexactlyas writtenin the last ModeControl
Word.OUTPUTbit D7 containsthe cunentstateof
the OUTpin.This allowsthe usErto monitorthe
counter'soutputvia sottware,possiblyeliminating
somehardwarefroma system.
Flgure 12.Null Count Operatlon
lf multiplestatuslatch operationsof the counter(s)
are performedwithout readingthe status, all but the
first are ignored;i.e.,the status that will be read is
the status of the counter at the time the first status
read-backcommandwas issued.
D1
NULL
RW1 RW0 M2 M1 MO BCD
@UNT
OUTPUT
Dzl:OutPinisl
0: OutPinis0
D5 | = Nullcount
0 : Countavailablefor reading
Ds-Do CounterProgrammecl
Mode (SeeFigure7)
Flgure 11.Statue Byte
NULL COUNTbit D6 indicateswhen the last count
writtento the counterregister(CR)has beenloaded
into the countingelement(CE).The exacttime this
happensdependson the Modeof the counterand is
describedin the ModeDefinitions.
but untilthe count
is loadedinto the countingelement(CE),it can't be
readfrom the counter.lf the count is latchedor read
befoi'etnis tirne,the countvalue wilt nct reflectthe
new count just written.The operaticncf Null Count
is shownin Figure12.
Both count and status of the selected counter(s)
may be latched simultaneously by setting both
COUNTand STATUSbits D5,D4:0. This is functionallythe sam€ as issuingtwo separate read-back
commandsat once, and the above discussionsapply here also. Specifically,if multiplecount and/or
status read-backcommandsare issued to the same
counter(s)withoutany interveningreads,all but the
first are ignored.This is illustratedin Figure 13.
lf both count and statusof a counter are latched,the
first read operationof that counter will return latched
status,regardlessof which was latched first. The
next one or two reads (dependingon whether the
counteris programmedfor one or two tyDe :ountsl
return latchedcount. Subsequentreads re:,:'n unlatchedcount.
Command
DescrlPtlon
D7 D5 D5 Da D3 D2 D1 D6
1
1
0 0 0 0
1
0 Readbackcountand statusof
Counter0
t
1
0 0
1
0 0 Readbackstatusof Counter1
1 1
1
1
0 0 Readback statusof Counters2, 1
I
Results
Countand statuslatched
for Counter0
Statuslatchedfor Counter1
Statuslatchedfor Counter
2, but not Counter1
1
0
1
1
0
0
0
Readbackcountof Counter2
Countlatchedfor Counter2
{
I
1
0
0
0
1
0
0
Readbackcountand statusof
Counter1
Countlatchedfor Counter1
but not status
1
1
1
0
0
0
1
0 Readbackstatusof Counter1
I
Command
ignorad,
status
alreadylatchedfor Counter1
Figure 13.Read-BackGommandExample
3_90
int€f
CS
0
0
0
m
1
I
't
0
0
0
0
0
0
0
0
0
1
X
0
1
1
82C54
WR A r Ao
0
0 0 WriteintoCounter0
0
0 1 WriteintoCounter1
0
1
0 Writeinto Countsr2
0
1
1 WriteControlWord
1
0 0 ReadfromCounter
0
1
0
I
ReadfromCounter1
1
1
0 ReadfromCounter2
1
1
(3-State)
1 No-Operation
x X X No-Operation
(3.Staie)
1
(3-State)
X x No-Operation
Flgure14.Read/WrlteOperatlons
Summary
Thisallowsthe countingsequenceto be synchronized by software.Again,OUTdoes not go high untilN
+ 1 CLKpulsesafier the new count of N is written.
lf an initialcount is writtenwhile GATE : 0, it will
still be loadedon the next CLK pulse.When GATE
goes high,OUT will go high N CLK pulseslater;no
CLK pulseis neededto loadthe Counteras this has
alreadybeendone.
Ct.
!0
LSlra
.a
Out
l.l:iil:l?i
Mode Definitions
Cl r l0
The followingare definedfor use in describingthe
operationof the 82C54.
CLK PULSE:a risingedge,then a fattingedge,in
that order, of a Counter'sCLK input.
TRIGGER:a risingedge of a Counter'sGATEinput.
0 ltrirFl
o lfriFEl
Ltl r!
Frlrl,
a*
otn
*t
COUNTERLOADING:the transferof a countfrom
the CR to the CE (refer to
the "Funclional Description")
l-l,l.l.l3
Clrr0
ltlrt
olololo
2lz
tt
l0
Ltlr2
tt
MODE 0: INTERRUPTON TERMINALCOUNT
Mode 0 is typicallyusedfor eventcounting.Afterthe
ControlWord is written,OUT is initiallylow,and will
remainlow untilthe Counterreacheszero.OUTthen
goes high and remainshigh until a new count or a
new Mode 0 Control Word is written into the Counter.
GATE : 1 enablescounting;GATE = 0 disables
counting.GATE has no eftect on OUT.
After the Control Word and initialcountare writtento
a Counter,the initialcountwill be loadedon the ne!.l
CLK pulse.This CLK pulse does nol decrementthe
count, so for an initialcount ol N, OUTdoes not go
high until N + 1 CLK pulsesafterthe initialcountis
written.
lf a new count is written to the Counter,it will be
loaded on the next CLK pulseand countingwill continue from the new count. lf a two-bytecount is written, the followinghappens:
1) Writingthe first bytedisablescounting.OUTis set
lovr immediately(no clock pulserequired).
2) Writing the second byte allows the new count to
be loadedon the nelrtCLK pulse.
3-91
aaa
-t
l-l"l-l',
lllll
0lo
,lr
l0
l!
l;Fl
lFFl
231244-8
NOTE:
The FollowingConventions
ApplyTo All Mode Timing
Diagrams:
1. Counters are programmedfor binary (not BCD)
countingand tor Reading/Writingteast significantbyte
(LSB)only.
2. The counteris alwaysselected(G alwayslow).
3. CW standsfor "ControlWord";CW : 10 meansa
conlrolword of 10, hex is writtento the counter.
4. LSB standsfor "Least SignificantByte" ot count.
5. Numbersbelowdiagramsare count values.
The lowernumberis the leastsignificantbyte.
The uppernumber is the most significantbyte. Since
the counter is programmedto Read/Write LSB only,
the mostsigniticantbyte cannotbe read.
N standsfor an undefinedcount.
Verticallinesshow transilionsbetweencounl values.
Figure15.Mode0
intef
82C54
IIODE 1: HARDWAREBETBIGGERABLE
ONE.SHOT
OUTwillbe initiallyhigh.OUTwill go low on the CLK
pulsefollowinga triggerto beginthe one-shotpulse,
and will remain low until the Counterreaches zero.
OUTwill then go high and remainhigh untilthe CLK
pulse atler the next trigger.
After writing the Control Word and initial count, the
Counter is armed. A trigger results in loading the
Counterand settingOUT low on the next CLK pulse,
thus startingthe one-shotpulse.An initialcount of N
will resultin a one-shot pulse N CLK rycles in duration. The one-shot is retriggerable,hence OUT will
remain low for N CLK pulses after any trigger.The
one-shotpulsecan be repeatedwithoutrewritingthe
samecount into the counter.GATE has no effect on
OUT.
lf a newcountis writtento the Counterduringa oneshot pulse,the current one-shotis not affected unless the Counter is retriggered.ln that case, the
Counteris loaded with the new count and the oneshot pulsecontinuesuntilthe new countexpires.
MODE 2: RATE GEIIIERATOR
This Mode functions like a divide'by-Ncounter. lt is
typiciallyused to generate a Real Time Clock interrupt OUT will initiallybe high.Whenthe initialcount
has decrementedto 1, OUT goes low for one CLK
pulse. OUT then goes high again, the Counter reloads the initiatcount and the processis repeated.
Mode 2 is periodic;the same sequenceis repeated
indefinitely.For an initialcount of N, the sequence
repeatsevery N CLK cycles.
GATE : 1 enables counting; GATE : 0 disables
counting.lf GATE goes low duringan output pulse,
OUT is set high immediately.A trigger reloads the
Counterwith the initialcount on the next CLK pulse;
OUT goes low N CLK pulsesafter the trigger.Thus
the GATE input can be used to synchronize the
Counter.
After writing a Control Word and initial count, the
Counterwill be loadedon the next CLK pulse.OUT
goes low N CLK Pulsesafter the initialcount is written. This allows the Counter to be synchronizedby
softwarealso.
,1" l3l: lill i::l3ll I
----o^r.
---t
n
- - --'.!
aa"
lolololol
lr
l5l.
3
|
231244-'tO
,i"l!ililifft[[lli3l
23'1244-9
NOTE:
A GATE transitionshould not occur one clock prior to
terminalcount.
Ffgurel7.Mode2
intef
82C54
Writing a new count while countingdoes not affect
the current counting sequence. lf a trigger is received after writing a new count but before the end
of the cunent period, the Counterwill be loadedwith
the new count on the next CLK pulse and counting
will continue from the new count. Othenrise, the
new count will be loaded at the end of the c-tlnent
counting cycle. In mode 2, a COUNTof 1 is illegal.
OUT will be highfor (N + 1)/2 counts and low for
(N -1)/2 counts.
*'---l-l
I-1
I-l
Ii l' l' l.l: l! l: l: l: i: i: l: l: l! I
MODE 3: SQUAREWAVE IIODE
Mode 3 is typicallyused for Baud rate generation.
Mode 3 is similarto Mode 2 exceptfor the dutycycle
of OUT. OUT will initiallybe high.Whenhalfthe initial count has expired,OUT goes low for the remainder of the count. Mode 3 is periodic;the sequence
above is repeatedindefinitely.An initialcount of N
results in a square wave with a period of N CLK
cycles.
aaa
GATE : 1 enables counting;GATE : 0 disables
counting.lf GATE goes low whileOUTis low,OUTis
set high immediately;no CLK pulse is required.A
trigger reloads the Counter with the initialcount on
the next CLK pulse. Thus the GATE input can be
used to synchronizethe Counter.
"aa
After writing a Control Word and initial count, the
Counterwill be loaded on the next CLK pulse.This
allows the Count€r to be synchronizedby software
also.
231244-11
NOTE:
A GATEtransitionshouldnot occurone clock priorto
terminal
count.
Writing a new count while countingdoes not affect
the current counting sequence.lf a triggeris received after writing a new count but beforethe end
of the current haltcycle of the square wave, the
Counter will be loaded with the new count on the
neld CLK pulse and countingwillcontinuefrom the
n€w count. Othenrise, the new count will be loaded
at the €nd of the current half-cycle.
Figure 18.Mode 3
MODE'l: SOFTWARETRIGGEREDSTROBE
OUT will be initiattyhigh. When the initial count expires,OUT will go low for one CLK pulse and then
go highagain.The countingsequenceis "triggered"
by writingthe initialcount.
Mode 3 is implementedas follows:
Even counts:OUT is initiallyhigh.The initialcountis
loadedon one CLK pulse and then is decremented
by two on succeedingCLK pulses.Whenthe count
expiresOUT changes value and the Counteris reloaded with the initialcount. The above processis
repeatedindefinitely.
odd counts: oUT is initiallyhigh.The initialcount
minusone (an even number)is loadedon one CLK
pulse and then is decrementedby two on succeeding CLK pulses. One CLK pulseafter the count expires, OUT goes low and the Counter is reloaded
with the initial count minus one. SucceedingCLK
pulsesdecrementthe count by two.Whenthe count
expires,OUT goes high again and the Counteris
reloadedwith the initialcount minusone. The above
process is repeated indefinitely.So for odd counts,
GATE : 1 enablescounting;GATE : 0 disables
counting.GATEhas no effect on OUT.
After writing a ControlWord and initial count, the
Gounterwill be loadedon the next GLK pulse.This
CLK pulsedoes not decremenlthe count, so for an
initial count of N, OUT does not strobe low until
N + 'l CLK pulsesafter the initialcount is written.
lf a new count is writtenduringcounting,it will be
loadedon the nextCLK pulseand countingwill continue from the new count. lf a two-bytecount is written, the followinghappens:
3-93
int€t
82C54
1)Wdtingthe firstbytehasno effecton counting.
2) Writingthe secondbyteallowsthe new countto
be loadedon the nextCLKPulse.
This allowsthe sequenceto be "retriggered"by
sottware.OUTstrobeslow N+1 CLK pulsesafter
the newcountof N is written.
la
A triggerresults in the Counterbeing loaded with the
initial count on the next CLK pulse. The counting
OUT will not strobe low
sequenceis retriggerable.
for N + 1 CLK putsesatter any trigger. GATE has
no effect on OUT.
lf a new count is writtenduringcounting,the current
counting sequence will not be atfected. lf a trigger
occurs atter the new count is written but before the
current count expires, the Countar will be loaded
with the new count on the next GLK pulse and
countingwill continuefrom there.
l.l"i.l.l:l
Clr
After writing the ControlWord and initial count, the
counterwill not be loadeduntil the CLK pulse atter a
trigger. This CLK pulse does not decrement tha
count, so for an initial count of N, OUT does not
strobe low until N + 1 CLK pulses after a trigger.
Lta.I
f-l
Crt
clrc
l"l"l.l"i:
'I
clr
c^fe
out
l" l.l"i-
! i | :l?i: l: l3 l::l
231244-12
Figure19.Mode4
MODE5: HARDWARETRIGGERED
STROBE
(RETBIGGERABLE}
OUT will initiallybe high.Countingis triggeredby a
risingedge of GATE.When the initialcount has expired,OUT will go low for one CLK pulse and then
go highagain.
aaa
l " i ,r
I
lrl"
" l oI lI
|
ol o I ol:rlFFlo,
|
|
tFFtt€l
2
|
0
3
o i
a
I
231244-13
Figure20. Mode 5
inbf
82C54
Slgnal
Statur
Modes
Low
OrGolng
Low
0
Disables
countinq
OperationCommonto All Modes
Rlrlng
Programming
Enables
countino
1) lnitiates
counting
2) Resetsouput
after next
clock
1
2
3
4
Hlgh
1) Disables
counting
2) Sets ouput
immediately
hioh
1) Disables
counting
2) Setsoutput
immediately
hioh
GATE
lnitiates
counting
Enables
counfng
Initiates
counting
Enables
counting
Disabl€s
counting
Enables
countinq
5
When a Control Word is written to a Counter, all
ControlLogic is immediatelyreset and OUT goes to
a knowninitialstate; no CLK pulses are requiredfor
this.
Initiat€s
countino
Figure21.GatePlnOperationsSummary
tAx
COUNT
The GATE input is always sampled on the rising
edgeof CLK.ln Modes0, 2, 3, and 4 the GATEinput
is level sensitive,and the logic level is sampledon
the rising€dge ot CLK. In Modes 1, 2, 3, and 5 the
GATEinputis rising-edgesensitive.In theseModes,
a risingedge of GATE (trigger)sets an edge-sensitive flip-flopin the Counter.This flip-flopis then sampled on the next rising edge of CLK; the flip-flop is
reset immediatelyafter it is sampled. In this way, a
triggerwill be detected no matter when it occurs-a
highlogicleveldoes not haveto be maintaineduntil
the next rising edge of CLK. Note that in Modes 2
and 3, the GATE input is both edge- and level-sensitive. In Modes 2 and 3, if a CLK source other than
the system clock is used, GATE should be pulsed
immediatelyfollowingWR of a new count value.
COUNTER
iIODE
MIN
COUNT
0
1
0
1
1
2
2
3
2
0
0
0
The largestpossibleinitialcount is 0; this is equivafent to 215 lor binary counting and 104 for BCD
eounting.
4
1
0
The Counterdoes not stop when it reacheszero. In
Modes0, 1, 4, and 5 the Counter"wrapsaround"to
the highestcount,eitherFFFF hex for binarycounting or 9999 for BCD counting,and continuescounting.Modes2 and 3 are periodic;the Counterreloads
itself with the initial count and continuescounting
frcm there.
NOTE:
0 is equivalentto 216 for binary countingand 10a for
BCD counting
Figure 22. Minimumand MaxlmuminitialCounts
New counts are loaded and Counters are decrementedon the fallingedge ot CLK.
intef
82C54
ABSOLUTEMAXIMUMRATINGS'
UnderBias... . . . .0'Cto 70'C
Ambient
Temperature
StorageTemperature ..... -65"to +150'C
-0.5to +8.0V
SupplyVoltage
+ 4Vto + 7V
Voltage
Operating
.GND-2V to +6.5V
Voltage
onanyInput..
Voltage
on anyOutput. .GND-0.5Vto V66 + 0.5V
...1Watt
PowerDissipation.
'Notice: Sfressesabovethoselisted under "Abso'
lute MaximumRatings"maycausepermanentdam'
age to thd device. Thisis a sf76ssrating only and
functionaloperationof the device at thes€ or any
otherconditionsabovethoseindicatedin the opera'
tionatsectionsof thisspecillcationis not implied.&'
posure to absolutemaximumrating conditionsfor
extendedperiodsmayaffect devicereliability.
D.C.CHARACTERISTICS
-4OC to *85'C for ExtendedTemperature)
CIA=0'C to 7O'C,V66:5V+ 10%, GND:0V) ftl :
T€t Condltlon!
Mln
ilax
Unltr
Parameter
Symbol
-0.5
V
0.8
vn
InputLowVoltage
y66 + 0.5
V
2.0
Vrs
InoutHiohVoltaqe
lnr : 2.5 mA
0.4
V
Vor
OutputLowVoltaqe
loH = -2.5 mA
V
3.0
vox
OutputHighVoltage
V
lns = -100 nA
Vee - 0.4
pA
Vrrv:Vcc to 0V
x2.0
Itt
InputLoadCunent
pA
to 0.0V
Vour=Vcc
t
1
0
lorl
Cunent
Float
Leakage
Output
20
mA
lcc
V65 SupplyCurrent
crkFreq= ,#yi;r?'rT;
lccsa
lccsBr
Ctr,t
9rc
Cour
10
V6c SupplyCunent-Standby
,,4
V6s SupplyCurrent-Standby
150
pA
InputCapacitance
l/O Capacitance
10
20
20
pF
OutputCapacitance
pF
pF
CLKFreq = 96
eS: Vcc.
All Inputs/Data
BusV66
AllOutoutsFloatino
CLKFreq : 99
eS = Vcc.AllOtherlnputs,
l/O Pins: VGrD,OutputsOpen
fc: 'l MHz
pins
Unmeasured
returned
to GND(5)
A.C.CHARACTERISTICS
(Tl:0"Cto70'C,Vcc:
5 V + 1 0 " / " , G N D- 0 V ) ( T A : - 4 0 ' C t o + 8 5 ' C f o r E x t e n d e d T e m p e r a t u r e )
(NOIE1)
BUSPARAMETERS
READCYCLE
Symbol
tnR
tsn
tRn
tRR
tRD
Mln
AddressStableBeforeRD-t
6 staoteBeforeR-Dt
AddressHoldTimeAfterFT 1
m Pulsewidth
DataDelayfromFD J
tno
Data Delayfrom Address
top
FE t to DataFloating
tnv
CommandRecoveryTime
NOTE:
1. AC timingsmeasuredat V66 : 2.0V,V4 = 0.8V.
82C54-2
Mar
82C54
Parameter
ilax
0
0
30
0
0
150
95
45
120
220
90
200
3-96
Unlta
Mln
ns
ns
85
185
5
165
65
ns
ns
ns
ns
ns
ns
inbf
82C54
A.C. CHARACTERISTICS(continued;
WFITECYCLE
Symbol.
tnw
lsw
twR
tww
tow
two
82C54
Parameter
Min
AddressStableBeforeWF J
llar
0
0
WFiJ
6 stauteBefore
AddressHoldTime After WF 1
WR PulseWidth
0
150
DataSetupTimeBeforeWR-f
DataHoldTimeAtterWF f
120
0
200
CommandRecoveryTime
82C54-2
Min
Mar
0
0
0
95
95
Units
ns
ns
ns
ns
ns
ns
ns
0
165
CLOCKAND GATE
Symbol
tclx
tplvH
tpwl
Tq
tp
tcw
tcl
tes
tcx
Ton
trcoe
twc
twe
two
tcu
Parameter
ClockPeriod
HiqhPulseWidth
Low PulseWidth
Clock RiseTime
ClockFallTime
Garewidth High
Gate Width Low
GateSetupTimeto CLKT
Gate HoldTimeAfterCLK t
OutputDelaylrom CLK J
OutputDelayfrom Gate J
CLK Delayfor Loadrng(4)
GateDetayfor Sampling(4)
OUT Delayfrom ModeWrite
CLKSet Up for CountLatch
82C54
Min
Max
125
DC
60(3)
60(3)
25
82C54-2
Min
Max
100
n
-5
-40
ns
25
25
50.
-40
ns
ns
100
100
55
40
240
40
ns
50(2)
0
-5
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
40
150
120
55
50
260
45
ns
ns
30(3)
50(3)
25
50
50
50
50(2)
DC
Units
NOTES:
2. ln Modes 1 and 5 triggersare samplec,on each risingclockedge.A secondtriggerwithin 120 ns (70 ns for the 92C54-21
of the risingclock edge may not be detected.
3. Low-goingglitchesthat violatetpWx,tpWt may causeenors requiringcounterreprogramming.
4. Exceptfor ExtendedTemp.,See EnendedTemp.A.C.Characteristics
below.
5. Samplednot 1000/"tested.Ts = 25'C.
6. It CLK presentat Tyvgmin then CountequalsN+2 CLK pulses,T976mar equalsfuunt N+1 CLK pulse.Tvv6min to
max,count will be eitherN + 1 or N + 2 CLK pulses.
T11y6
7. In Modes 't and 5, if GATEis presentwhen writinga new Countyalu€,at Tyy6 min Counterwill not be triggered,at Ty76
max Counterwill be triggered.
8. It CLK present when writinga CounterLatch or ReadBackCommand,at T6g min CLK will be reflectedin count value
latched,at T61 max CLK will not be reflectedin the countvalue €tched. Writinga Counter Letch or ReadBackCommand
betweenTg1 min and T671max will resultin a latchedcountvalluewhich is t one leasl significantbit.
o
40"c *85'CforExtendedTemperature
TEMPERA
EXTENDEDTEMPERATURE
[fn : -40"Cto
82C54
82C54-2
' Parameter
Symbol
Min
Mar
Min
Max
-25
-25
CLK Delayfor Loading
twc
25
25
twe
GateDelayfor Sampling
-25
3-97
25
-25
25
Unlts
NS
ns
intef
23't244-11
231241-15
231244-16
int€t
CLOCK AND GATE
n12u-17
' [rst byteof co0nttteingw'inon
A.C. TESTINGINPUT,OUTPUTWAVEFORM
INPUT/OUTPUT
A.C.TESTINGLOADCIRCUIT
l' -'*
I
*t
I
|
23121/-14
A.C.Testing:lnputsare drivenat 2.4Vlot a logic"1" lnd 0..15V
for a logic "0." Timingmeasurem€nts
8t€ mad€tt 2.0Vtot t loglc
"1" end0.8Vfor a logic"0."
uxDtr
I
dc,'urr
J
?
Gg - 15oPF
CL includesXgcepacitano
?3l2{/.-19
Intel82C55AProgrammablePeripheralInterface
DataSheetReprint
intel'
82Cs5A
INTERFACE
PERIPHERAL
CHMOSPROGRAMMABLE
r Control Word Read-BackCapability
r Direct Bit Set/ResetCaPabilitY
. 2.5 mA DC Drive Gapabilityon all l/O
Port Outputs
r AvailableIn 40-PinDIP and 44'PinPLCC
I Availablein EXPRESS
- StandardTemperatureRange
- Ertended TemperatureRange
I Compatiblewith all Intel and Most
Other Microprocessors
r High Speed,"Zero Wait State"
Operationwith 8 llHz 8086/88and
80186/188
| 24 Programmablel/O Pins
I Low PoweTCHMOS
r CompletelyTTL Compatible
The lnlel 82C55A is a high-performance,CHMOS version of the industry standard82554 general purpose
prograrnmablel/O devicJwhicn is designedlor use with att Intel and most other microprocessors.lt provides
programmedin 2 groupsof 12 and used in 3 majormodesof operationZA ltO pins whichmay be individually
The 82C55Ais pin compatiblewith the NMOS 8255Aand 8255A'5.
in MODE 0, each groupof 121/0 pins may be programmedin sets of 4 and I to be inputsor outputs.ln
to have8 lrnesof inputor outpui.3 of the remaining4 pinsare used
miy be programmed
lvlCDE1, each grou=o
bus conliguration.
for handshakingand intenuptcontrolsrgnals.MODE2 is a strobedbi-directional
The €ZC55Ais fabricatedon Intel'sadvancedCHMOSlll technologywhich provideslow powerconsumption
with performanceequalto or greaterthan the equivalentNMOSproduct.The 82C55Ais availablein 40-pin
DIP and 44-9inplastic leadedchip carrier (PLCC)packages.
r e3 3 i 3 r i 3 3 i r r
rtstl
5
do
F
DI
l0
,c,
rc
r2
rc6
rJ
rc
0a
t5
6
fcs
rca
fco
rcl
t6
1f
ooaoot6aoaa
-
!
d
t2cSsA
231256-1
Figure 1.82C55ABlock Diagram
z.31256-2
Flgure2. 82C55APlnout
Diagrams are for pin rGt€tenc€ only. Packag€
gz6s are not lo scal€.
3-124
S.plctnbcr t9t7
Odcr llunboe 23f236fi4
82C55A
Table1. Pln
Symbol
PAg-o
Pln Numbcr
PLCC
Dlp
2-5
1-4
FE
5
6
6
6
7
7
8-9
8
9-10
GND
Ar-o
Typc
NamcandFunctlon
ato
FORTA Pll{S0-3: Lowernibbleof an Stit dataoutputlatch/
butferandan 8-bitdatainputlatch.
READCOilTROL:Thisinputis lowduringCPUreadoperations.
A lowon thisinputenablesthe82C55Ato
CHIPSELECT:
respondto R'FandWF sgnals.RE andWR are ignored
othE]wise.
SystemGround
ADDRES$Theseinputsignals,in coniunctionR'6and WF[,
contol the selectionof oneof thethreeportsor ths control
wordreEisters.
lnput Operatlon(Read)
Ar
Ao
F6 WF 6
0
0
0
0
1
1
0
1
I
0
1
I
I
0
0
0
0
0
I
I
1
1
0
1
t
1
t
0
0
0
0
x
X
X
x
x
1
1
x
vo
POFT C, PINS4-7: Uppernibbleof an 8-bit data output latch/
bufferand an 8-bit data rnputbuffer(no latch for inpu$. This oort
can be d:vicedinto t*o A-srtportsuncertne 'noCecon::r. Each
4-bitport containsa 4-bit latchand it can be ,lsed for th€ control
signaloutputsand statussignalinputsin coniunctionwith ports
A and B.
16-19
)to
PIORTC, PINS0-3: Lowernibbleof Port C.
vo
PORTI, Pll{S0-7: An8-bitdatiaoutputtatch/bufferand an 8bit datainputbutfer.
PCz-r
1 0 - 1 3 1 1 , 1 31- 5
PCo-s
14-',t7
PBoz
18-25
Vcc
26
27-34
RESET
35
20-22,
24-28
29
30-33,
35-38
39
WF
36
40
PAt-t
37-40
41-44
Dz-o
NC
I
PortA-DatraBus
0
PortB-DataBus
0
PortC-DataBus
0
0 I ccntrolword- DataBus
OutputOperatlon(Wrltc)
DataBus- PortA
0
0
DataBus- PortB
0
DataBus- PortC
D
DataBus- Control
DlsableFunctlon
1
DataBus-3-Stat€
0
DataBus-3-State
1,12,
73,34
SYSTEII POWER:* 5V PowerSupply.
t/o
DATA 8US: Bi-directional,tri-stat€data bus lines,connected to
syst€m data bus.
RESET:A high on this inputclearsthe control registerand atl
ports ar€ set to th6 input mode.
WRITECONTROL:
Thisinputis lowduringGPUwrite
operations.
t/o
PORTA, PINS4-7: Uppernibbleof an 8-bitdataoutputlatch/
bufferand an 8-bit data inputlatch.
NoConnact
irfief
82C554
DESCRIPTION
82C55AFUNCTIONAL
General
The 82C55Ais a programmableperipheralinterface
device designedfor use in Intel microcomputersystems. lts functionis that of a generalpurposel/O
componentto interfaceperipheralequipmentto the
microcomputersystembus. The functionalconfigurationof the 82C55Ais programmedby the system
softwareso that normallyno externallogic is necessary to interfaceperipheraldevices or structures.
Data Bus Buffer
This 3-state bidirectional8-bit butfer is used to interface the 82C55A to the system data bus. Data is
transmittedor receivedby the bufferuponexecution
of input or output instructionsby the CPU. Conlrol
words and status information are also translerred
throughthe data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the
internal and external transfers of both Data and
Control or Status words. lt accepts inputs from the
CPUAddressand Controlbussesand in turn,issues
commandsto both of the ControlGroups.
Group A and Group B Controls
The functionalconfigurationof each port is programmedby the systems software.In essence,the
GPU "outputs" a controlword to the 82C55A.The
control word contains informationsuch as "mode",
"bit set", "bit resat", etc., that initializesthe functionalconfigurationof the 82C55A.
Each of the Controlblocks(GroupA and Group B)
accepts"cornmands"from the Read/WriteControl
Logic. receives "control words" lrom the internal
data bus and issuesthe proper commandsto its associated ports.
ControlGroupA - Port A and Port C upper (C7-C4)
ControlGroupB - PortB and PortG lower(C3-C0)
The control word register can be both written and
read as shownin the addressdecode table in the
pin descriptions.Figure6 shows the control word
format for both Read and Write operations.When
the controlwordis read,bit D7 willalwaysbe a logic
"1", as this impliescontrolword mode information.
Portg A, B, and C
The 82C55Acontainsthree8-bitports(A, B, and C).
All can be configuredrn a wide varietyof tunctional
characteristicsby the systemsoftwarebut each has
its own special features or "personality" to lurther
enhancethe powerand flexibilityof the 82C55A.
Port A. One 8-bit data output latch/butfer and one
8-bit input latch bufter. Both "pull-up" and "pulldown" bus hold devicesare presenton Port A.
Port B. One 8-bit data input/outputlatch/buffer.
Only "pull-up"bus hold devicesare presenton Port
B.
Port C. One 8-bit data outputlatch/bufferand one
8-bit data inputbuffer (no latch for input).This port
can be dividedinto two 4-bit ports underthe mode
control. Each 4-bit port containsa 4-bit latch and it
can be used{or the control signatoutputsand status
signalinputsin coniunctionwith portsA and B. Only
"pull-up" bus hold devicesare presenton Port C.
for
See Figure4 for the bus-holdcircuitconfiguration
Port A, B, and C.
3-126
intef
82C55A
id
il
a:rt
231256-3
Flgure3.82C55AElockDlagramShowlngDataBusBufferandRead/WrlteControlLoglc Funcilonr
IT{TERIIAL
o7
m
'NOTE:
231256-1
Port pins loadedwith rnorethan20 pF capacitancemay not have theirlogiclevel guarante€d following a hardware resEt.
Flgure4. Port A, B, C, Bus-holdConflguration
3-127
intet
82C55A
DESCRIPTION
82C55AOPERATIONAL
Ot
Mode Selection
oa
q
o.
Da
q
ot
%
J
There are three basic modes of operationthat can
be selected by the system software:
Mode 0 - Basicinput/outPut
Mode 1 - Strobed InPut/outPut
Mode 2 - Bi-directionalBus
/
IORT I
I . INPUI
0. OUltUt
roog s€r€c7lor
0. $OD€0
t . I,OOE I
/
EoG. +T
:
r9Gr
{y llll llll
'q'q
T,ts' T,f'
1
{9"
.'+q
llll
.D LE;6-
llll
reE SttEgflol
6. XOOE0
Ot-FOE t
ll.IOt
2
moc s€?fl 6
I . ACYIVE
J'u'oriEcnon^L
Any of the aightbits of PortC can be Set or Reset
This featurere'
usinga singleOUTputinstruction.
in frntrol'basedappli'
ducessoftwarerequirements
cations.
t^'t\
a312fi_s
lnterface
foi? a
t . lrtuT
0. Ottttur
SlngleBlt SeUResetFeature
t}'
''\'\
_c
m
\
The modedefinitionsand possiblemodecombinationsmayseemconfusingat firstbut atlera cursory
reviewof the completedeviceoperationa simple,
logicall/O approachwill surface.The designof the
82C55Ahastakenintoaccountthingssuchas etficientPCboardlayout,controlsignaldefinitionvs PC
layoutand completefunctionalflexibilityto support
devicewith no externallogic.
almostanyperipheral
Such designrepresentsthe madmumuse of the
availablePins.
t+-tt
^
-i--
ffi
cRott ^
for? c |lttEil
I . lNtut
O. OUTtUt
The modes for Port A and Port B can be separately
defined, while Port C is dividedinto two portionsas
required by the Port A and Port B definitions.All of
the output registers, including the status flip'flops'
will be reset wheneverthe modeis changed'Modes
may be combined so that their functionaldefinition
can be "tailored" to almost any l/O structure.For
in Mode0 to
instance;GroupB can be programmed
monitorsimple switch closingsor displaycomputa'
tional results, Group f could be programmedin
Mode 1 to monitora keyboardor tape readeron an
interrupt-drivenbasis.
rcr.f%
\
toar c (loiERl
l.l'|rut
0.OUT?iT
Whenthe reset inputgoes "high" all portswill be set
to the input modewith all24 gorllinesheldat a logic
"one" lev€l by the internal bus hold devices (see
Figure 4 Note). Atter the reset is removed the
82C55A can remain in the input mode with no additionalinitializationrequired.Thiseliminatesthe need
for pullup or pulldown devicesin "all CMOS" designs. During the execution of the systemprogram'
any of the other modes may be selectedby usinga
single output instruction. This allows a single
82C55A to service a variety of peripheraldevices
with a simple softwaremaintenanceroutine.
rr, q
cnort!
Port
WhenPortC is beingusedas status/controlfor
A or B,thesebilscanbe setor resetby usingtheBit
Set/Resetoperation
iustas if theyweredataouFut
ports.
3-128
82C5sA
lnterruptControlFunctlons
coirnoLroto
When the 82C55Ais programmodto op€rate in
mode1 or mode2, controlsignalsare providedthat
canbe usedas interruptrequestinputsto the CPU.
Theintemlptrequestsignals,generatedfrom port C,
can be inhibitedor enabledby settingor resetting
INTEflip.flop,usingthe bit set/reset
the associated
functionof portC.
Thisfunctionallowsthe Programmer
to disallowor
allowa specificllO deviceto intemrptthe CPUwithout affectinganyotherdevicein the interruptstructure.
INTEflip-flopdefinition:
291256-7
(BIT-SED-INTEis SET-lnterruptenable
(BIT-RESET)-INTE
is RESET-Interrupt
disable
Flgure7. Blt Set/ResetFormat
Note:
All Mask flip-flopsare automatically
reset during
modeselectionanddeviceReset.
3-129
intef
82C554
OperatlngModes
llode 0 (Baslc Input/Output).Thistunctionalconfigurationprovidessimpleinputand outputoperationsfor each of the threeports.No "handshaking"
is required,data is simplywrittento or roadfrom a
specifiedport.
l--
Definitions:
Mode0 BasicFunctional
o Twc 8-bitportsandtwo 4-bitports.
. Anyportcanbe inputor output.
. Outputsare latched.
o Inputsare not latched.
o 16 ditferentInput/Output
areposconfigurations
siblein thisMode.
ltr
l--*^--t
or.Do-
triODEo (BASICOUTPUT)
3-130
intef
82C55A
iIODE0 Port Deflnltlon
A
B
Da
D3
D1
D6
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
1
't
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
0
1
GROUPA
PORTC
PORTA
(UPPER)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
NPUT
OUTPUT
NPUT
OUTPUT
NPUT
OUTPUT
NPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
10
GROUPB
PORTC
PIORTB
(LOWER}
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
1'l
INPUT
INPUT
12
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
#
0
1
2
3
4
3
6
7
8
9
INPUT
INPUT
INPUT
INPUT
13
14
15
INPUT
INPUT
MODE0 Configuratlonr
cotTlot
roio
ro
c$rlRoL woFo a
o,
ol
t
0
J!
o.
olo
I
coi?RoL woRo tl
coairnol woRo rl
o, 03 o: o.
ot
02
o,
Do
o
0
t
o
or
oo
ot
or
I'l.i.lol'l'j
9afr4
PC,.PC.
Er'Eo
Plr{80
2 : 1 2 5 5 - 10
3-131
inbf
82C55A
MODE0 Configurations(Continued)
cox?tol iotD aa
coirtnol roeo a
o, Da o, o.
Dt
olo
D.
D3
D.
Or
Ot
0o
olololo
t^rt$
Wq
rcr4,
E:a$
rcfo
,t' rto
fti.t!
GOrtFOr
Dr
o,
tart\
oortYRo! roRD t3
Ot
or
Oo
Dr
De
totD
tL
a0
O.
O,
O?
O,
Oo
ffi
o^/\
rly'\
Er{r
rc7tc.
tcr4q
Erto
rqrq
ter4q
@||rROt ioeo ,rc
Dt Or Or O.
1D.Or0.o:orD,Do
Or
Or
Ot
Oo
rlolol'l'lol'lo
PAraA!
,f\
ft#,
rCy'Cr
rcfi.
tsr{o
,8r'q
'3r{e!
coitrRo! ron0 at
D,
Oa
O,
O.
Ot
D2
Or
oo
, rt\
'A?'\
tfr
jGfl0.
Ert%
fcfi
4
'lfli!
231256-11
3-132
82Cs5A
ilOOE0 Conllgura$onr(C;ontinued)
@ratiotrctDarl
tl0
coff?iotnofo'lt
0
rtt
0
I
o
cottrot roro a|l
orDr%oro:%oroo
rt0
0
0
231256-12
Opentlng lloder
ilOOE 1 (Strobed lnput/Output).This functional
providesa meansfor transferring
configuration
l/O
datato or froma specifiedport in conjunction
with
strobesor "handshaking"
signals.In mode1, PortA
and PortB use the lineson PortC to generateor
acceptthese"handshaking"
signals.
Mode 1 BasicfunctionalDefinitions:
o Two Grouos(GroupA and GroupB).
o Each group containsone 8-bit data port and one
4{it control/data port.
o The 8-bit data port can be either input or output
Both inputsand outputs ar€ latched.
o The 4-bit port is used for control and status of the
8-bit data port.
3-133
inbf
82C554
Input Control SlgnalDeflnltlon
Slt- (Strole Input). A "low" on this inputloads
dataintothe inputlalch.
coa{ltol
to;D
: rf,iE I
LJ-J
IBF (lnputBuffer FullF/F)
A "high" on this outputindicatesthat the datahas
beenloadedinto the inputlatchjn essence,an acknowledgement.
IBF is set by STBingulbeinglow
and is resetby the risingedgeof the RD input.
INTR(lnterruptRequert)
A "high" on this outputcan be usedto intemrptthe
GPU when an input deviceis requestingservice.
INTRis set by the STBis a "one",IBFis a "one"
and INTEis a "one". lt is resetbythefallingedgeof
FD. tnis orocedureallowsan input deviceto request servrcelrorn the CPUby simptystrobrngits
dataintothe port.
INTEA
Controlledby bit set/resetof PCa.
INTEB
Controlledby bit set/resetof PC2.
231256-',t3
FlgurcS.IUODE
1 Input
tt
1
llf
J
r{lt
E
-
1ar16<l\^
4,2
I
f,(tt3to
tftrfHttaL
tr
231256-11
Flgure9.ilODE1(StrobedInput)
3-134
intef
82C55A
OutputControlSlgnalDeflnl$on
O=6FlOutput Buffcr Fu[ F/F]. The 6EF outputwitl
go "low" to indicatethat th€ CpU has writtEndata
outto ths sp€cifiedpoq_Ib€6EF frp wi[ be set by
the risingedgeof the WR=input
and reset!y ffi
tnputbeinglow.
sor\o.%ororDr
ffi (ActnowledgeInput).A .,low"on this input
informsthe82G55AthatthedatafromportA or port
B hasbeenaccepted.In essencs,a responsefrom
the peripheral
deviceindicating
that it has received
the dataoutputby the CPU.
INTR(lntenuptRequert).A ,.high".onthisoutput
can be usedto intemJptthe CpU whenan output
devicehasaccepteddatratransmittedbv the CpU.
INTRis sEtwhenFeR is a "one,',6EF-isa ,,on€'.
anqINTEis a "on€". lt is rEsatby thefailingedgeof
wR.
rc:
I tFottll
INTEA
Controlled
by bit set/resetof pC5.
INTEB
Conkolledby bit set/resetof pC2.
231256-15
Flgurel0.llODE 1 Output
231256-16
Flgure11.MOOE1 (StrobedOutput)
3-135
intef
82C554
Combinations of MODE1
Port A and Port B chn be individuallydefinedas inputor outputin Mode 1 to supporta wide varietyof strobed
l/O applications.
tart\
fc.
fl^
rq
tlFa
cofireoL rroFo
@.{trol
rc?
66Fr
tc.
aGtr
||oiD
tcr-tt{tR^
fct
2
tsr.r
ofr
iEr.
fort A - tstaoa€oouTrutl
toRrS -(stioB€ottrutl
loFla-|stiotEotir?uYl
foFtl-(slRoBEDoulruT)
231256-17
Operating Modes
Output Operatlons
i/IODE 2 (Strobed Bidirectional Bus l/O).This
functionalconfigurationprovidesa meansfor communicatingwith a peripheraldeviceor structureon a
single 8-bit bus for both transmittingand receiving
data (bidirectionalbus l/O). "Handshaking"signals
are provrdedto maintainproperbus flow disciplinein
a similar manner to MODE 1. Interruptgeneration
and enable/disablefunctionsare also available.
6EF (Output Buffer Full). The 6EF output will go
"low" to indicatethat the CPU has written data out
to port A.
MODE 2 Basic FunctionalDefinitions:
o Used in GroupA only.
o One 8-bit,bi-directional
bus port (PortA) anda 5port
(Port
C).
control
bit
. Both inputs and outputsare latched.
o The S-bit controlport (PortC) is used foi control
and status for the 8-bit, bi-directionalbus port
(Port A).
1 fihe INTE Flip-Flop Associated wlth
!E
OBF). Controlledby bit set/reset of PC5.
Bldirectional Bus l/O Control Signal Definition
INTR (lnterrupt Request).A highon this outputcan
be used to interruptthe GPUfor inputor outputoperations.
Iffi (lctnowledge). A "low" on this input enables
the tri-stateoutput buffer of Port A to send out the
data. CIhenrise,the output butfer will be in the high
impedancestate.
lnput Operations
SiE (StroUe Input). A "low" on this input loads
data into the inputlatch.
IBF (lnput Euffer Full F/F). A "high" on this output
indicatesthat data has been loaded into the input
latch.
INTE2 (The INTEFlip-Flop Assoclated with IBF).
Gontrolledby bit set/reset of PGa.
3-136
8rc55A
COTTROLrcNO
6-F^
tQr
I .ltt(rt
0.OUtrut
E-x^
ront I
I . ltrtt t
0. oultttT
ff^
tlFr
GiottSs€
0. rrOOC0
l.lrcOE I
231256-19
r/o
Figure13.MODEControtWord
231256-1I
Figure14.llODE2
o tlFn
,crrPfiEn Ltotzctat
oaTl Ftot
rlc6a toPctDtrcrAt
orYl FnoI
trc$lloc
Figure15.MODE2 (Bidirectionat)
iloTe
Any sequenceq!9!q m occurs beforeACK-.and $B occursbeforeFE is oermissible.
( I N T R= I B F r F i R . S F B . R E
+ OEF.Mffirfrffioffi1
3-137
intef
82C55A
MODE2 AND MODEO {OUTPUT}
rrooE 2 At{DirooE 0 0NPur)
c(xTtol
rN?ir
Ixlt^
ct^
6ii.
rm^
Iroto
E^
ooxtiol roao
4OrQoror4O,%
4OrtD.DtDrOtDo
tc.
F-!^
q
tlF^
Eln
rr,ffiffil
ffi^
I
ts"J
tl?a
r/o
tro
rqrto
MOOE 2 Ai.IO MODE I {INPUT)
MODE 2AND MODE I {OUTPUTI
tc!
rq
ttti^
rlrt\
r44
rct
fcr
txrL
o-%
@t{?nol
ffi^
fi)Ro
,c,
ff.
rq
fr^
sDr|\D.DrO?DrOo
tc.
mr
tc.
fi^
rC!
Itt^
q
ttf^
tlrttt
rq.rq
frF.
lc2
G
Frr
fcr
tlar
ntRr
r%
fffrr
3-138
intef
82C55A
ModeD,eflnltlon
Summary
MODEO
MODE1
MODE2
IN
OUT
IN
our
PAo
PAr
PAz
PAg
PAI
PAs
PA6
PAz
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Pfu
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PBr
PBz
PBs
PBa
PBs
PBe
PBz
PCo
PCr
PC2
PC3
PCr
PCs
PCe
PC7
GROUPA ONLY
€
MODEO
ORMODE1
ONLY
our
OUT
OUT
INTRs INTRs
lBFs oEFs
t/o
tlo
t/o
INTRa INTRI
INTRa
ffis
Affis
srEA t/o
SrB-a
t/o
t/o. ACRA
t/o mFA
lBFl
SpecialMode ComblnationConslderations
Thereare severalcombinationsof modespossible.
For anycombination,
some or all of the PortC lines
are usedfor con:rolcr stetus.The remainingbrtsar:
eitherinputsor outputsas oefinedby a "Set Mode"
command.
Duringa read of Port C, the state of all the Port C
lines,exceptthe ACK and STB lines,will be placed
on the data bus. In place of the Affi and STE tine
states,flag statuswill appearon the data bus in the
PC2. PC4, and PC6 bit positionsas illustratedby
Figure18.
Througha "WritePortC" command,only the PortC
pins programmedas outputs in a Mode 0 group can
be written.No other pins can be atfectedby a "Write
PortC" command,nor can the interruptenableflags
be accessed.To write to any Port C output programmedas an output in a Mode 'l group or to
lBFg
4ffi1
0-er4
changean interruptenableflag,the "Set/Reset Port
C Bit" commandmust be used.
With a "Set/Reset PortC Bit" command,any Pcrt C
line prog.ammed
rg INTF, i3F
as an output(inctud:
and OBF) can be written,or an interruptenacle flag
can be either set or reset. Port C lines programmed
as inputs,includingFffi and ffi lines,associated
with Port C are not atfected by a "Set/Reset Port C
Bit" command.Writinqto the correspondingPoft C
bit positionsof the iCX anO STB lines with the
"Set/Reset Port C Bit" commandwill atfect the
GroupA and GroupB intenuptenableflags,as illustratedin Figure18.
Current Drlve Capabillty
Any outputon Port A, B or C can sink or source2.5
mA. This featureallowsthe 82C55Ato directtydriva
Darlington type drivers and high-vottage disptays
that requiresuch sink or sourcecunent.
3-139
82C5sA
INPUTCONFIGURATION
D3
D5
Oa
D2
D1
Reading Port C Status
Dr
In Mode 0, Port C transfersdata to or from the peripheraldevice.Whenthe 82C55Ais programmed
to
function in Modes 1 or 2, Port C generatesor accepts "hand-shaking"signalswith the peripheraldevice. Readingthe contentsof Port C allowsthe programmer to test or verify the "starus" of each peripheral device and change the program llow accordingly.
D6
r / O t/o
lBFl
INTEl
INTRI INTEg
OUTPUTCONFIGURATIONS
D6 D5 D4 D3
D2
D1
Oe-r1INTEI
De
t/o l / O i l N T R aINTEs OB-FBINTRs
GROUPA
There is no special instructionto read the statusinformation from Port C. A normal read operationof
Port G is executed to performthis function.
lBFs INTRs
GROUPB
GROUPA
D7
Ds
GBOUPB
Figure17a.MODE1 StatusWordFormat
97
D5
D5
Da
D3
D2
D1
Ds
Al INTE1| IBFAI INTE2lINTRA
GROUPA
GROUPB
(Defined By Moct€ 0 or Mod€ 1 Selectrcn)
Flgure17b.MODE2 StatusWordFormat
lnterruot EnableFlao
INTEB
INTEA2
INTEA1
Position
Alternate Port C Pln SiEnal(Mode)
PC2
PC4
PC6
ffia (OutputMode1)orSTEs(lnputMode1)
STB1(lnputMode1 or Mode2)
AGr (OutputMode1 or Mode2
Figure 18.InterruptEnableFlagsIn Modes 7 and2
3-140
82CssA
'Notice: Sfressesabovethose listed under "Absolute Ma(imumRatings"maycausepermanentdamage to the devica.Thisis a stressrating only and
functionaloparationof the device at these or any
otherconditionsabovethoseindicatedin the operetionalsectionsof thissgecificationis not implied.*posure to absolutemascimum
rating conditionsfor
extendedpeiods mayaffect devicereliability.
ABSOLUTEMAXIMUMRATINGSAmbientTemperature
UnderBias.. . .ffC to + 70'C
StorageTemperature ..- 65'Cto+ 150'C
SupplyVoltage
0.5to + 8.0V
....+ 4Vto + 7V
OperatingVoltage
.GND-2V to f 6.5V
Voltage
on anylnput..
Voltage
on anyOuput . .GND-0.5Vto V66 + 0.5V
PowerDissipation
.....1Watt
D.C.CHARACTERISTICS
TA = 0'Cto70'C,VCC- +5V t10o/o,GND:0VOn
Symbol
Parameter
= -40oCto *85'GforExtendedTemperture)
Test Condltlonr
Mln
Max
Unlts
0.8
V
Vcc
v
0.4
V
161: 2.5 mA
V
V
lox : -2.5 mA
IOH: -100 pA
: Vqg to 0V
V161
(Note1)
V1p= V66 to 0V
(Note2)
Vru
InputLowVoltage
-0.5
vpt
InputHighVoltage
2.0
Vol
OutputLowVoltage
Vox
OutputHighVoltage
Irt
Input LeakageCunent
t1
pA
lorl
OutputFloatLeakageCurrent
r10
pA
lom
Darlington
DriveCurrent
r2.5
(Note+)
mA
PortsA, B,C
Re1 = 500O
Vs1 : 1.7V
lpxu
Port Hold Low LeakageCunent
+50
+ 300
pA
Vggl : 1.0V
Port A only
lpsx
PortHold HighLeakageCunent
-50
-300
pA
Vggl:
3.0V
Ports A. 5. C
lpnto
Port Hold Low OverdriveCunent
-350
pA
lpxxo
Port Hold HighOverdriveCunent
+350
pA
Vggl : 0.8V
V9g1 : 3.0V
lcc
V66 SupplyCunent
10
mA
(Note3)
lccsa
V66 SupplyCunent-Standby
10
pA
V66: 5.5V
VrN= VCCor GND
PortConditions
ll llP : Open/High
OlP = OpenOnly
with DataBus :
High/Low
6 : High
Reset : Low
PureInputs :
Low/High
3.0
Vss - 0.4
NOTES:
1. PinsAr, Ao,eS, WF-,FD, Reset.
2. OalaBus: PortsB. C.
3. Oulputsopen.
4. Limitoutputcurrentto 4.0 mA.
3-141
intel
82C55A
CAPACITANCE
TA : 25'C, V66 :QfrlP : gY
Symbol
Parameter
Mln
Max
Unlts
ctru
InputCapacitance
10
pF
Gvo
l/O Capacitance
20
pF
TestCondltions
plns
Unmeasured
returnedto GND
fc : 1 MHz(S)
NOTE:
5. Samplednot 100o/o
tested.
A.C. CHARACTERISTICS
TA : 0otO 70'C, VCC= +5V t10o/o,GND = 0V
TA : -40oC to +85'C for ExtendedTemperature
BUS PAFAMETERS
READ CYCLE
Symbol
82C55A.2
Parameter
llln
Unlls
llax
tln
AddressStableBeforeFE t
0
ns
tne
AddressHoldTimeAtterFE f
0
ns
tRn
ffiPulseWidth
ns
150
tno
tor
DataDelayfromFD I
FE f to DataFloating
tFv
RecoveryTimebetweenFD/WH
10
Test
Gondltions
't20
ns
75
ns
200
ns
WRITE CYCLE
Symbol
82C55A-2
Parameter
llin
Unlts
llax
Teat
Condltlons
tlw
AddressStableBeforeWF I
0
ns
twe
Address
HoldTimeAfterWH't
20
ns
PortsA & B
20
ns
PortC
tww
WFIPulseWidth
100
ns
tow
DataSetupTimeBeforeWFif
100
two
DataHoldTimeAfterWFf
30
ns
ns
ns
30
3-142
PortsA & B
PortC
intef
82C55A
OTHERTIMINGS
Symbol
82C55A-2
Parametcr
Mln
twg
WFi: ltoOutput
trn
txR
Peripheral
DataBeforeFD
PeripheralDataAtterFD-
tnx
ffi
tst
tps
ilar
Unl|!
Condltlonr
350
ns
0
ns
0
ns
200
ns
SmPub€width
100
ns
20
tpx
Per.DatraBeforeSE Xign
Per.DatraAfterffiHigfl
tlo
A ffi :0 to Ou p u t
PulseWidth
Tert
150
tnoa
WFI=ltoOEF:O
Affi = 0toOE|F:1
tsrg
ffi=0tolBF:1
150
ns
ns
ns
ns
ns
ns
ns
tnrg
ffi=ltotBF:0
FiE: OtoINTR: 0
STE=ltolNTR:1
150
ns
200
ns
150
Affi=ltoINTR:1
150
WR:Oto|NTR: O
200
ns
ns
ns
see note 1
ns
seencte2
tro
twoa
tRtt
tgr
tnrr
twr
tnes
ffi
- 1 to OutputFloat
ResetPulseWidth
50
175
20
250
150
500
NOTE
t. INTHT mayoccuras earlyas WF l.
2. Pulsewidthof initialRes€tpulseafterpoweron mustbe at least50 pSec.Subseguent
Resetpulsesmaybe 5oo ns
minimum.
3-143
WAVEFORMS
roDE 0 (BASTC
INPUT)
n12fi-22
. moDE0 (BAS|COUTPUn
+rr-<l
Nt1256-23
3-144
intet
WAVEFORMS(Continueo)
MODEI (STROEED
rlrPur)
tl
|lF
lttt
F6
ritrjTtto___
2€RrrHtiar.
231256-24
MODEI (STROBED
OUTPUn
;T
6t
|f?e
rcf
qrTlrt
231256-25
82C554
WAVEFORMS(continued)
MODE2 (B|DTRECTTOiTAL)
Anysequence
whereWFIoccursb€loreFfi nHOffi occursbeforeFiEis permissible.
+ GF.Fi-moflffirffi;
1 N T F= I B F T F i A S T S T E o F D
WRITE TIMING
BEAD TIMING
t-r. c3
AO-r,Gl
l-D^?l
I
rer
ti.F.,
ltJs
16
m
oata ttJs
lrr
231256-27
A.C. TESTINGINPUT,OUTPUTWAVEFORM
A.C. TESTING LOAD CIRCUIT
Y:rr'
Iq-irct
231256-29
231256-30
'Vgrf ls S€t At V8riousVohag€sOuringT€stingTo Guarantee
The Specification.C1 InctudesJig Capacitance.
A.C. T€sttng InputsAre friven At 2.4V Fot A Logic 1 And 0.45V
For A Logic 0 Timing Measuoments Ar€ Mad€ At 2.0V For A
Logic 1 And 0.8 For A Logic0.
3-146
APPENDIX D
FOR SIGNAL*MATH
CONFIGURINGTHE ADA2OOO
JumperSettings
WhenrunningSIGNAL*MATH, you haveto changesomeof theADM000's on-boardjumpersfrom their
facory-serpositions.BeforeusingSIGNAL*MATH on theADA2000board,checkthefollowingjumpers:
. E2 - Baseaddress
. P3 - 8254 timerrcounterI/O configuradon
. P4,P5 &P7 - Interrupts
. P6- End-of-ConvertMonitor
Theboardlayoutis shownin FigureD-1.
ift
tl !
I
tl
tl
tl
.O
Fig. D-1 -
ADA2000Board Layout
P2 - BaseAddress
SIGNAL*MATH assumesthatthebaseaddressof your ADA2000is the factoryseuingof 300 hex (768
decimal).If you changethis setting,you must run the ADAINST programandresetthebaseaddress.
NOTE: Whenusingthe ADAINST program,you canenterthebaseaddressin decimalor hexadecimal
nouation.
Whenenteringa hex value,you mustpreredefte numberby a dollar sign(for example,$300).
D-3
P3 -8254 Timer/CounterVO Configuration
The 8254mustbe configuredwith thesix jumpersplacedbetweenthepins asshownin FigureD-2. After
settingthejumpers,verify thateachis in dreproperlocation.Any remainingjumpersmustbe removedfrom theP3
headerconnector.
l*
XTAL
ECo
+5V
E@
lg
ls
co0
co0
cKl
XTAL
ECI
+5V
EGI
col
col
ct<2
ls
XTAL
&2
+5V
EG2
coz
c@.
l*
ls
Ele
Els
Ig
Fig. D-2 -8254 Timer/CounterJumpers,P3
P4,P5 & P7 -Interrupts
To selectIRQ channelsandintenuptsourcesfor SIGNAL*MATI{, you mustinstall two jumperson P5 andone
jumperon P7.First installa jumperon P5-OUT2,anda secondjumperacrossthepair of P5 pins for the IRQ
installa jumperon theend-of-convert
intemrptheader,F/, acrossthepins of your de,sired
channelyou select.Then,
IRQ channel.The IRQ selectedon P7 must be different from the IRQ seton P5! FigureD-3 showsOUT2
jumperedto IRQ3 andEOCjumperedto IRQ4.Makesurethatno jumpersareinstalledon P4.
lRoT
lR06
P7
tRos
lR04
lR03
lR02
OUTO
OUTl
OUT2
o
o
l!
i
o
7
6
5
4
3
2
E
Fig.D-3- Timer/Counter
Out& End-of-Convert
Intenupt
P5& P7
Jumpers,
P6 - End-of-ConvertMonitor
WhenrunningSIGNAL*MATH, placea jumperbetweenEOC andPA7, as shownin FigureD-4.
tr;
P6
Fig.D-4- End-of-Convert
MonitorJumper,P6
D4
Running ADAINST
After thejumpersare setand the ADA2000 boardis installedin the computer,you are readyto configure
SIGNAL*il4ATH so that it is compatiblewith your board'sseuings.This is doneby running the ADAINST driver
insallation prograrn.After running the program,openADA2000-DG from theOpena File menu.You will seea
scr@nsimilar o the screenshownin Figue D-5 below. Tte facory default serings are shownin the illustration.
Your secingsmay or rnaynot rnarchthe default settings,dependingon whetheryou havemadechangesto these
seuingsbefore.
BaseAddress. The board'sbaseaddressseuingis enteredin the upperright block, as shownin the diagram.
The factory settingfor all Real Time Devicesboardsis 3CI hex (768 decimal).The baseaddresscanbe entercdasa
decimalor hexadecimalvalue (hex ralues must be precededby a dollar sign (for example,$300)).Refero your
board's manrul if you needhelp in determiningtheconect valueto enter.
EOC IT @nd-of-Convert Intenupt). In this block, enterthe IRQ channelnumberwhich correspondsto your
jumper sating on F/.
Timer IT (fimer/Counter Interrupt). In this bloclK,ent€rthe IRQ channelnumberwhich correspondso your
jurnper settingon P5.
LabTech SW IT (LABTECH NOTEBOOK Software Internrpt). This setsthe softwareintemrpt address
whereLABTECH NOTEBOOK's labLINX driver is insulled. The facory seuingis $CI. This settingcanbe
igtored whenrunning SIGNAL*MATH.
A"/DParameters. Six .AlD boardparametersare listed:resolution,numberof channels,actirieDMA channel,
gain, loss,and input voltagepolarity.
Endof-Convert
Interrupt
Channel
Timer/Counter
lnterruptChannel
BasE AddrEss
llet$i4,,r.:,:::r:,
irr,
Software
Interrupt
Address
A/D DMA
Channel
Select;
D/A DMA
Channel
Select;
ExternalGain
& Loss
External Gain
& Loss
A/D Unipolarl
Bipolar
Select
D/AUnipolar/
Bipolar
Select
Fig.D-5- ADAINST.EXE
Screen
D-5
Resolutionandnumberofchannelsare fixed by the programfor your board.
The DIvIA channelnumberblock is not valid on the ADA2000, and shouldbe left blank.
The next two blocks,gain ard loss,areprovidedso that you can malreadjustmensfor external gain or loss,
other than the programmablegain settingsamilable on theboard.If your input signalis externally auenuated,then
you can adjustfor this by seninga valueotherthan I for loss.If you harrean extemalgain factor, thenyou can
adjust for this condition.Numbersmustbe enteredaswhole decimd values.The facory default setringfor gain and
lossis l.
For a bipolar input range,an X shouldbe placedbeforeBipolar on the screen(default setting). For rmipolar
operation,removehe X.
D/A Parameters Six D/A boardparametersarc listed:resolution,numberof channels,active DMA channel,
gain, loss,and input voltagepolarity. Resolutionand numberof chanrplsare fixed- For the ADA2000, DIvIA is not
usedand shouldbe left blar*. Gain andlossareprovidedso that you can makeadjusfrnentsfor externalgain or
loss,as describedabovefc the A7Dparameters.
For a bipolar orilput range,an X strouldbe placedbeforeBipolar on
(default
the smeen
sering). For unipolaroperation,removethe X.
D-6
APPENDIX E
FORATLANTIS
CONFIGURINGTHE ADA2OOO
E-l
Jumper Settings
WhenrunningATLAI.{TIS,you haveto changesomeof theADA20@'s on-boardjumpersfrom their facorysetposirions.Before using ATLANTIS on the ADM000 board,checkthe following jumpers:
c /) - Baseaddress
. P3 - 8254 imerlcounter I/O configuration
. P4,P5 &n * Intemrps
. P6- End-of-ConvertMonitor
The boardlayout is shownin FigureE-1.
iilil Il
UI
nt
C='t
M'1
qiiffi$g'Effi'-ruffi
;*0++E+mF%#trrJ$U
U
ltl
I tl
I ll
IH
UJ
-'--:t-l,i
=- =::
i- 3.:fl
l-'O=iliilli; ln,=,h-',#
0-'0-=l
-EE-;l
ll'
'[r
"ri-:l
P--'
ll.
:
Gi
L_l
tl
I
tt
ttl
-o ll l|l
r
cfI-J
'I-t
-rf-l'E-uuilLl
l.l
rf
J
Fig. E-1 -
ADA2000Board Layout
P2 - BaseAddress
thatthebaseaddressof your ADA2ffiO is thefacory settingof 300 hex (seeChapter1). If
ATLANTIS assumes
you changedthis setting,you must run the ATINST programandresetthe baseaddress.
NOTE: The ATINST prognm requiresthebaseaddressto be enteredin decimalnotation.
E-3
P3 - 8254Timer/CounterUO Configuration
The 8254 mustbe configuredwith the six jumpersplacedbetweenthe pins as shownin Figure E-2. After
settingthejumpers,verify thateachis in theproperlocation.Any remainingjumpersmustbe removedfrom theF{}
headerconnector.
Ig
XTAL
ECo
+5V
E@
ls
ls
coo
coo
cKl
XTAL
FCl
+5V
EGl
l8
El:
E
l_q
cor
d6T
u<2
lx
XTAL
&2
+5V
EC€
co2
co2
ls
l3
P3
Fig.E-2-8254 Timer/Counter
Jumpers,
P4,P5 & VI - Interrupts
To selectan IRQ channelandan intemrpt sourcefor ATLAI.ITIS, you must install two jumperson P5, the
timer/counteroutputintemrptheader.Jumpersmustbe installedacrossthe OUT2 pins and acrossthe pins of your
desiredIRQ channel.FigureE-3 showsOUT2 jumperedto IRQ3. lvfakesurethat no jumpersare installedacrossthe
IRQ pins on headerconnectors
P4 andYl.
tRoT
tR06
tRos
tR04
tR03
tR02
ouT0
OUTl
OUT2
Fig. E-3 -
End-of-ConvertInterruptJumper, P7
P6- End-of-ConvertMonitor
WhenrunningATLANTIS, placea jumperbetweenEOC andPA7, as shownin FigureE4.
.o
o
!
Fig.E-4- End-of-Convert
MonitorJumper,PG
E4
APPENDIX F
IryARRANTY
F-2
LIMITED
WARRANTY
Real Time Devices,Inc. warrantsthe hardwareandsoftwareproducs it manufacturesand producesto be frree
from defecs in materialsandworkmanshipfor one yearfollowing the dateof shipmentfrom REAL TIME DEVICES. This warrantyis limited to theoriginal purchaserof productand is not ransferable.
During the one yearwarrantyperiod,REAL TIME DEVICESwill repair or replace,at its option, any defective
producs or partsat no additionalcharge,providedthat theproductis returned,shippingprepaid,to REAL TIME
DEVICES. All replacedpars and producs becomethe propertyof REAL TIME DEVICES. Before returning any
product for repair, customersare reguired to contactthe factory for an RMA number.
THIS LIMITED WARRA}ITY DOESNOT EXTEND TO AI.IY PRODUCTSWHICH HAVE BEEN DAMAGED AS A RESULT OF ACCIDENT, MISUSE, ABUSE (suchas: useof incorrectinput voltages,improperor
insufficient ventilation, failure to follow the operatinginstructionsthat are providedby REAL TIME DEVICES,
"acts of God" or other contingenciesbeyondthe control of REAL TIME DEVICES), OR AS A RESULT OF
SERVICEOR MODIFICATION BY AT.iYONEOTTIERTHAN REAL TIME DEVICES. EXCEPT AS EXPRESSLYSETFORTH ABOVE, NO OTHER WARRANTIES ARE E)PRESSED OR IMPLIED, INCLUDING,
BUT NOT LIMITED TO, AI.IY IMPLIED WARRANTIES OF MERCHANTABILITY AND FTTNESSFOR A
PARTICULAR PURPOSE,AND REAL TIME DEVICESE}PRESSLY DISCLAIMS ALL WARRAI{TIES NOT
STATED TIEREIN.ALL IMPLIED WARRANTIES,INCLUDING IMPLIED WARRANTIES FOR
MECHANTABILITY AND FITNESSFOR A PARTICULAR PURPOSE,ARE LIMITED TO THE DURATION
NOTFREEFROMDEFECTSAS WARRANTED
OFTI{IS WARRANTY.INTHEEVENTTT{EPRODUCTIS
ABOVE, THE PIJRCHASER'SSOLEREMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED
ABOVE. LINDERNO CIRCUMSTANCESWILL REAL TIIvIEDEVICES BE LIABLE TO TI{E PIIRCHASER
oR ANY USERFOR AI.{Y DAMAGES,INCLUDING ANIYINCIDENTAL OR CONSEQUENTIAL DAMAGES,EXPENSES,LOST PROFITS,LOST SAVINGS,OR OTHERDAMAGES ARISING Of]T OF THE USE
OR INABILITY TO USETHE PRODUCT.
SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEDAMAGESFOR CONSUMERPRODUCTS,AND SOME STATESDO NOT ALLOW LIMTTAQTJENTTAL
TIONS ON HOW LONG AN IMPLIED WARRA].iTYLASTS,SOTHE ABOVE LIMITATIONS OR EXCLU.
SIONSMAY NOT APPLY TO YOU.
THIS WARRANTY GIVES YOU SPECIFICLEGAL RIGTITS,AI{D YOU MAY ALSO HAVE OTHER
RIGHTSWHICH VARY FROM STATETO STATE.
F-3
ADA2000 User-SelectedOptions
Base I/O Address:
(decimal)
(hex)
IRQ Channel Selection:
A/D EOC
IRQ CHANNEL:
PITOT'TO
IRQCTIANNEL:
PITOI,JTI
IRQ CHANNEL:
PITOUT2
IRQCIIANNEL:
PPI1rNTRA(1PC3)
IRQ CHANNEL:
PPT2TNTRA(2PC3)
IRQ CHANNEL:
PPI2INTRB (2PCO)
IRQCTIANNEL:
EXTINTI
IRQ CHANNEL:
EXTINT2
IRQ CHANNEL:
A/D EOC/PPI Bit Assignment:
A/D EOC
PA7
PC7